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[80.71.140.73]) by smtp.gmail.com with ESMTPSA id t6-20020a5d4606000000b0021b866397a7sm5713951wrq.1.2022.07.11.04.49.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jul 2022 04:49:52 -0700 (PDT) From: Emil Renner Berthing To: kernel-team@lists.ubuntu.com Subject: [SRU][J/allwinner-5.17][PATCH v3 1/4] phy: sun4i-usb: Rework HCI PHY (aka "pmu_unk1") handling Date: Mon, 11 Jul 2022 13:49:48 +0200 Message-Id: <20220711114951.99949-2-emil.renner.berthing@canonical.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220711114951.99949-1-emil.renner.berthing@canonical.com> References: <20220711114951.99949-1-emil.renner.berthing@canonical.com> MIME-Version: 1.0 X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Andre Przywara BugLink: https://bugs.launchpad.net/bugs/1981074 As Icenowy pointed out, newer manuals (starting with H6) actually document the register block at offset 0x800 as "HCI controller and PHY interface", also describe the bits in our "PMU_UNK1" register. Let's put proper names to those "unknown" variables and symbols. While we are at it, generalise the existing code by allowing a bitmap of bits to clear and set, to cover newer SoCs: The A100 and H616 use a different bit for the SIDDQ control. Signed-off-by: Andre Przywara Signed-off-by: Samuel Holland Link: https://lore.kernel.org/r/20220203013558.11490-3-samuel@sholland.org Signed-off-by: Vinod Koul (cherry picked from commit 1743dea7f06b939f67ba258bab993fa5ff6e43fb) Signed-off-by: Emil Renner Berthing --- drivers/phy/allwinner/phy-sun4i-usb.c | 30 ++++++++++++--------------- 1 file changed, 13 insertions(+), 17 deletions(-) diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c index 788dd5cdbb7d..142f4cafdc78 100644 --- a/drivers/phy/allwinner/phy-sun4i-usb.c +++ b/drivers/phy/allwinner/phy-sun4i-usb.c @@ -43,7 +43,7 @@ #define REG_PHYCTL_A33 0x10 #define REG_PHY_OTGCTL 0x20 -#define REG_PMU_UNK1 0x10 +#define REG_HCI_PHY_CTL 0x10 #define PHYCTL_DATA BIT(7) @@ -82,6 +82,7 @@ /* A83T specific control bits for PHY0 */ #define PHY_CTL_VBUSVLDEXT BIT(5) #define PHY_CTL_SIDDQ BIT(3) +#define PHY_CTL_H3_SIDDQ BIT(1) /* A83T specific control bits for PHY2 HSIC */ #define SUNXI_EHCI_HS_FORCE BIT(20) @@ -115,9 +116,9 @@ struct sun4i_usb_phy_cfg { int hsic_index; enum sun4i_usb_phy_type type; u32 disc_thresh; + u32 hci_phy_ctl_clear; u8 phyctl_offset; bool dedicated_clocks; - bool enable_pmu_unk1; bool phy0_dual_route; int missing_phys; }; @@ -288,6 +289,12 @@ static int sun4i_usb_phy_init(struct phy *_phy) return ret; } + if (phy->pmu && data->cfg->hci_phy_ctl_clear) { + val = readl(phy->pmu + REG_HCI_PHY_CTL); + val &= ~data->cfg->hci_phy_ctl_clear; + writel(val, phy->pmu + REG_HCI_PHY_CTL); + } + if (data->cfg->type == sun8i_a83t_phy || data->cfg->type == sun50i_h6_phy) { if (phy->index == 0) { @@ -297,11 +304,6 @@ static int sun4i_usb_phy_init(struct phy *_phy) writel(val, data->base + data->cfg->phyctl_offset); } } else { - if (phy->pmu && data->cfg->enable_pmu_unk1) { - val = readl(phy->pmu + REG_PMU_UNK1); - writel(val & ~2, phy->pmu + REG_PMU_UNK1); - } - /* Enable USB 45 Ohm resistor calibration */ if (phy->index == 0) sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1); @@ -863,7 +865,6 @@ static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = { .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A10, .dedicated_clocks = false, - .enable_pmu_unk1 = false, }; static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = { @@ -872,7 +873,6 @@ static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = { .disc_thresh = 2, .phyctl_offset = REG_PHYCTL_A10, .dedicated_clocks = false, - .enable_pmu_unk1 = false, }; static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = { @@ -881,7 +881,6 @@ static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = { .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A10, .dedicated_clocks = true, - .enable_pmu_unk1 = false, }; static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = { @@ -890,7 +889,6 @@ static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = { .disc_thresh = 2, .phyctl_offset = REG_PHYCTL_A10, .dedicated_clocks = false, - .enable_pmu_unk1 = false, }; static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = { @@ -899,7 +897,6 @@ static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = { .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A10, .dedicated_clocks = true, - .enable_pmu_unk1 = false, }; static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = { @@ -908,7 +905,6 @@ static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = { .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A33, .dedicated_clocks = true, - .enable_pmu_unk1 = false, }; static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = { @@ -925,7 +921,7 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = { .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A33, .dedicated_clocks = true, - .enable_pmu_unk1 = true, + .hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ, .phy0_dual_route = true, }; @@ -935,7 +931,7 @@ static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = { .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A33, .dedicated_clocks = true, - .enable_pmu_unk1 = true, + .hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ, .phy0_dual_route = true, }; @@ -945,7 +941,7 @@ static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = { .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A33, .dedicated_clocks = true, - .enable_pmu_unk1 = true, + .hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ, .phy0_dual_route = true, }; @@ -955,7 +951,7 @@ static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = { .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A33, .dedicated_clocks = true, - .enable_pmu_unk1 = true, + .hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ, .phy0_dual_route = true, }; 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[80.71.140.73]) by smtp.gmail.com with ESMTPSA id t6-20020a5d4606000000b0021b866397a7sm5713951wrq.1.2022.07.11.04.49.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jul 2022 04:49:53 -0700 (PDT) From: Emil Renner Berthing To: kernel-team@lists.ubuntu.com Subject: [SRU][J/allwinner-5.17][PATCH v3 2/4] UBUNTU: SAUCE: phy: sun4i-usb: Add D1 variant Date: Mon, 11 Jul 2022 13:49:49 +0200 Message-Id: <20220711114951.99949-3-emil.renner.berthing@canonical.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220711114951.99949-1-emil.renner.berthing@canonical.com> References: <20220711114951.99949-1-emil.renner.berthing@canonical.com> MIME-Version: 1.0 X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Samuel Holland BugLink: https://bugs.launchpad.net/bugs/1981074 D1 has a register layout like A100 and H616, with the moved SIDDQ bit. Unlike H616 it does not have any dependencies between PHY instances. Signed-off-by: Samuel Holland Link: https://lore.kernel.org/r/20220203013558.11490-4-samuel@sholland.org Signed-off-by: Vinod Koul (cherry-pick from https://github.com/smaeul/linux.git riscv/d1-wip) Signed-off-by: Emil Renner Berthing --- drivers/phy/allwinner/phy-sun4i-usb.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c index 142f4cafdc78..997a5e5e8136 100644 --- a/drivers/phy/allwinner/phy-sun4i-usb.c +++ b/drivers/phy/allwinner/phy-sun4i-usb.c @@ -945,6 +945,15 @@ static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = { .phy0_dual_route = true, }; +static const struct sun4i_usb_phy_cfg sun20i_d1_cfg = { + .num_phys = 2, + .type = sun50i_h6_phy, + .phyctl_offset = REG_PHYCTL_A33, + .dedicated_clocks = true, + .hci_phy_ctl_clear = PHY_CTL_SIDDQ, + .phy0_dual_route = true, +}; + static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = { .num_phys = 2, .type = sun50i_a64_phy, @@ -976,6 +985,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = { { .compatible = "allwinner,sun8i-h3-usb-phy", .data = &sun8i_h3_cfg }, { .compatible = "allwinner,sun8i-r40-usb-phy", .data = &sun8i_r40_cfg }, { .compatible = "allwinner,sun8i-v3s-usb-phy", .data = &sun8i_v3s_cfg }, + { .compatible = "allwinner,sun20i-d1-usb-phy", .data = &sun20i_d1_cfg }, { .compatible = "allwinner,sun50i-a64-usb-phy", .data = &sun50i_a64_cfg}, { .compatible = "allwinner,sun50i-h6-usb-phy", .data = &sun50i_h6_cfg }, From patchwork Mon Jul 11 11:49:50 2022 Content-Type: text/plain; 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[80.71.140.73]) by smtp.gmail.com with ESMTPSA id t6-20020a5d4606000000b0021b866397a7sm5713951wrq.1.2022.07.11.04.49.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jul 2022 04:49:54 -0700 (PDT) From: Emil Renner Berthing To: kernel-team@lists.ubuntu.com Subject: [SRU][J/allwinner-5.17][PATCH v3 3/4] UBUNTU: SAUCE: PM / devfreq: Add dummy R329/D1 MBUS driver Date: Mon, 11 Jul 2022 13:49:50 +0200 Message-Id: <20220711114951.99949-4-emil.renner.berthing@canonical.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220711114951.99949-1-emil.renner.berthing@canonical.com> References: <20220711114951.99949-1-emil.renner.berthing@canonical.com> MIME-Version: 1.0 X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Samuel Holland BugLink: https://bugs.launchpad.net/bugs/1981074 Signed-off-by: Samuel Holland (cherry-pick from https://github.com/smaeul/linux.git riscv/d1-wip) Signed-off-by: Emil Renner Berthing --- drivers/devfreq/Kconfig | 6 ++++++ drivers/devfreq/Makefile | 1 + drivers/devfreq/sun50i-r329-mbus.c | 27 +++++++++++++++++++++++++++ 3 files changed, 34 insertions(+) create mode 100644 drivers/devfreq/sun50i-r329-mbus.c diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig index 87eb2b837e68..2823d72dae16 100644 --- a/drivers/devfreq/Kconfig +++ b/drivers/devfreq/Kconfig @@ -141,6 +141,12 @@ config ARM_SUN8I_A33_MBUS_DEVFREQ This adds the DEVFREQ driver for the MBUS controller in some Allwinner sun8i (A33 through H3) and sun50i (A64 and H5) SoCs. +config ARM_SUN50I_R329_MBUS_DEVFREQ + tristate "Allwinner R329 MBUS DEVFREQ Driver" + help + This adds the DEVFREQ driver for the MBUS controller in some + Allwinner sun20i (D1) and sun50i (R329) SoCs. + source "drivers/devfreq/event/Kconfig" endif # PM_DEVFREQ diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile index 0b6be92a25d9..017ce88f6d0b 100644 --- a/drivers/devfreq/Makefile +++ b/drivers/devfreq/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx-bus.o obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ) += sun8i-a33-mbus.o +obj-$(CONFIG_ARM_SUN50I_R329_MBUS_DEVFREQ) += sun50i-r329-mbus.o obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o # DEVFREQ Event Drivers diff --git a/drivers/devfreq/sun50i-r329-mbus.c b/drivers/devfreq/sun50i-r329-mbus.c new file mode 100644 index 000000000000..983a366a1f13 --- /dev/null +++ b/drivers/devfreq/sun50i-r329-mbus.c @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// Copyright (C) 2022 Samuel Holland +// + +#include +#include +#include + +static const struct of_device_id sun50i_r329_mbus_of_match[] = { + { .compatible = "allwinner,sun20i-d1-mbus" }, + { .compatible = "allwinner,sun50i-r329-mbus" }, + { }, +}; +MODULE_DEVICE_TABLE(of, sun50i_r329_mbus_of_match); + +static struct platform_driver sun50i_r329_mbus_driver = { + .driver = { + .name = "sun50i-r329-mbus", + .of_match_table = sun50i_r329_mbus_of_match, + }, +}; +module_platform_driver(sun50i_r329_mbus_driver); + +MODULE_AUTHOR("Samuel Holland "); +MODULE_DESCRIPTION("Allwinner R329 MBUS DEVFREQ Driver"); +MODULE_LICENSE("GPL v2"); From patchwork Mon Jul 11 11:49:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Emil Renner Berthing X-Patchwork-Id: 1654841 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=canonical.com header.i=@canonical.com header.a=rsa-sha256 header.s=20210705 header.b=N5CwwxpR; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; 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[80.71.140.73]) by smtp.gmail.com with ESMTPSA id t6-20020a5d4606000000b0021b866397a7sm5713951wrq.1.2022.07.11.04.49.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jul 2022 04:49:54 -0700 (PDT) From: Emil Renner Berthing To: kernel-team@lists.ubuntu.com Subject: [SRU][J/allwinner-5.17][PATCH v3 4/4] UBUNTU: [Config] Enable additional Allwinner D1 options Date: Mon, 11 Jul 2022 13:49:51 +0200 Message-Id: <20220711114951.99949-5-emil.renner.berthing@canonical.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220711114951.99949-1-emil.renner.berthing@canonical.com> References: <20220711114951.99949-1-emil.renner.berthing@canonical.com> MIME-Version: 1.0 X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" BugLink: https://bugs.launchpad.net/bugs/1981074 CONFIG_SUN6I_RTC_CCU=y is needed to export the iosc clock for the random number generator in the crypto peripheral or the driver won't probe. CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG=y enables support for the "true random number generator" now that the crypto driver works. CONFIG_ARM_SUN50I_R329_MBUS_DEVFREQ=y enables the newly added dummy driver that the display engine depends on. Add annotations for the clock drivers, crypto driver and the new dummy devfreq driver while we're here. Signed-off-by: Emil Renner Berthing --- debian.allwinner/config/annotations | 16 ++++++++++++++++ debian.allwinner/config/config.common.ubuntu | 5 +++-- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/debian.allwinner/config/annotations b/debian.allwinner/config/annotations index 06efec7fbf99..dc779e4bb1d2 100644 --- a/debian.allwinner/config/annotations +++ b/debian.allwinner/config/annotations @@ -155,6 +155,11 @@ CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG policy<{'riscv64': 'n'}> # Menu: Cryptographic API >> Hardware crypto devices >> Freescale CAAM Job Ring driver backend # Menu: Cryptographic API >> Hardware crypto devices >> Support for Allwinner cryptographic offloader +CONFIG_CRYPTO_DEV_SUN8I_CE policy<{'riscv64': 'y'}> +CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG policy<{'riscv64': 'y'}> +CONFIG_CRYPTO_DEV_SUN8I_CE_HASH policy<{'riscv64': 'y'}> +CONFIG_CRYPTO_DEV_SUN8I_CE_PRNG policy<{'riscv64': 'y'}> +CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG policy<{'riscv64': 'y'}> # Menu: Cryptographic API >> Hardware crypto devices >> Support for OMAP crypto HW accelerators @@ -462,6 +467,14 @@ CONFIG_COMMON_CLK_FIXED_MMIO policy<{'riscv64': 'y'}> # Menu: Device Drivers >> Common Clock Framework >> Clock driver for MediaTek SoC >> Clock driver for MediaTek MT8183 # Menu: Device Drivers >> Common Clock Framework >> Clock support for Allwinner SoCs +CONFIG_SUNXI_CCU policy<{'riscv64': 'y'}> +CONFIG_SUN20I_D1_CCU policy<{'riscv64': 'y'}> +CONFIG_SUN20I_D1_R_CCU policy<{'riscv64': 'y'}> +CONFIG_SUN6I_RTC_CCU policy<{'riscv64': 'y'}> +CONFIG_SUN8I_DE2_CCU policy<{'riscv64': 'y'}> +CONFIG_SUN8I_R_CCU policy<{'riscv64': 'y'}> + +CONFIG_SUN6I_RTC_CCU note # Menu: Device Drivers >> Common Clock Framework >> Ingenic SoCs drivers @@ -772,6 +785,9 @@ CONFIG_DEVFREQ_GOV_PERFORMANCE policy<{'riscv64': 'y'}> CONFIG_DEVFREQ_GOV_POWERSAVE policy<{'riscv64': 'y'}> CONFIG_DEVFREQ_GOV_USERSPACE policy<{'riscv64': 'y'}> CONFIG_DEVFREQ_GOV_PASSIVE policy<{'riscv64': 'y'}> +CONFIG_ARM_SUN50I_R329_MBUS_DEVFREQ policy<{'riscv64': 'y'}> + +CONFIG_ARM_SUN50I_R329_MBUS_DEVFREQ note # Menu: Device Drivers >> Generic Dynamic Voltage and Frequency Scaling (DVFS) support >> DEVFREQ-Event device Support CONFIG_PM_DEVFREQ_EVENT policy<{'riscv64': 'y'}> diff --git a/debian.allwinner/config/config.common.ubuntu b/debian.allwinner/config/config.common.ubuntu index d74825fa6340..722cec25cc7b 100644 --- a/debian.allwinner/config/config.common.ubuntu +++ b/debian.allwinner/config/config.common.ubuntu @@ -270,6 +270,7 @@ CONFIG_ARCNET_COM90xxIO=m CONFIG_ARCNET_RAW=m CONFIG_ARCNET_RIM_I=m CONFIG_ARCX_ANYBUS_CONTROLLER=m +CONFIG_ARM_SUN50I_R329_MBUS_DEVFREQ=y CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ=m CONFIG_AS3935=m CONFIG_AS73211=m @@ -1277,7 +1278,7 @@ CONFIG_CRYPTO_DEV_SUN8I_CE=y CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG=y CONFIG_CRYPTO_DEV_SUN8I_CE_HASH=y CONFIG_CRYPTO_DEV_SUN8I_CE_PRNG=y -# CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG is not set +CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG=y CONFIG_CRYPTO_DEV_SUN8I_SS=y CONFIG_CRYPTO_DEV_SUN8I_SS_DEBUG=y CONFIG_CRYPTO_DEV_SUN8I_SS_HASH=y @@ -7254,7 +7255,7 @@ CONFIG_SUN50I_DE2_BUS=y CONFIG_SUN50I_IOMMU=y CONFIG_SUN5I_HSTIMER=y CONFIG_SUN6I_MSGBOX=y -CONFIG_SUN6I_RTC_CCU=m +CONFIG_SUN6I_RTC_CCU=y CONFIG_SUN8I_DE2_CCU=y # CONFIG_SUN8I_DSP_REMOTEPROC is not set CONFIG_SUN8I_MSGBOX=y