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Miller" , Jakub Kicinski , Madalin Bucur , netdev@vger.kernel.org Cc: Russell King , Paolo Abeni , linux-arm-kernel@lists.infradead.org, Eric Dumazet , linux-kernel@vger.kernel.org, Sean Anderson , Kishon Vijay Abraham I , Krzysztof Kozlowski , Rob Herring , Vinod Koul , devicetree@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH net-next v2 01/35] dt-bindings: phy: Add QorIQ SerDes binding Date: Tue, 28 Jun 2022 18:13:30 -0400 Message-Id: <20220628221404.1444200-2-sean.anderson@seco.com> X-Mailer: git-send-email 2.35.1.1320.gc452695387.dirty In-Reply-To: <20220628221404.1444200-1-sean.anderson@seco.com> References: <20220628221404.1444200-1-sean.anderson@seco.com> X-ClientProxiedBy: BL1P222CA0011.NAMP222.PROD.OUTLOOK.COM (2603:10b6:208:2c7::16) To DB7PR03MB4972.eurprd03.prod.outlook.com (2603:10a6:10:7d::22) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3d1e0234-b661-4db6-81cc-08da59538cbf X-MS-TrafficTypeDiagnostic: DB6PR03MB3013:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: pw7IRmaMfp8kPOgleu0iwyX+kaemhCxR4+nVnFljBw4BmN09/F39oCkrQZmuo6DWN9yWhkQuivh54+C1lCf7YZr/mAsdhxjWN6OPh4q1L00ek/lpqtKnNYsarLKE/SnxbLz/rVQ1Lt3eN3e8QcvMtRa1TzKGmm4O78sWqMpBBid3GEdVxE2hUih2ArU3UEEQZra7znYzaliXO63lK9gzm0Fg4PNTUFW1jC3ZQWFUSX2i7zU26Zm9pKNb3EBO2Zqa9iNJ2Lt/3PSBZEgUSxoah5gbUTUXWzP7vq7lDd4Gft9sgN50rOZ/LxgQJybM86XlcvqlPLS3efqN3FKtfx1eYkfgnR3qg4ljG/T2mO8fSEqPCNzf/jz3YdBLaRcO/W6CGRVz50dY2/4HXQYZb147z68w5lLjWCMdGHwBFWFl2QYKltRpapnLvDRgMcgCRzE9O23fn+bdV+ayd+tuKcvzRjGIFEnl5E5JPH+4OXYBZjHR9CP8Xnp+QaZooKXNTS45ha82XjRvID6QMB13xIiThqF5S6HlP0MxBTtz/AtfrWTuOTe4PYDj8PGBlzz5ilap6hsJHO+meYP3eoyUUopE690ZxtKrHegwwacFsgjztR4iu6dl/RZDYfZUIaY63hNUkjiqUUyRNggsUMmsZW8OLWzaAPzLoe4u0fdu/3InzxyBWpiExTa3yEFUtUMIEuChRMAu5U5RCDa0atyOOD2e5vl+ePGuczsNqKcrI5Pfb/1/Ien9uNXm5Dr13X2TZsSUK0pfxIjZB0l6mMG8pFXYCTUYSez1Z9K9tCMmQvRAKoL6bOzqHQY5XU+18crytoC6UyTOzHf+0RwNWMg0ZDwUCAastGNrhvGDUm8gM8Q/OtTtCyRcSoG5VYCWqR7FeWfhiIYgs4r99dP7dpe+Nluu+UxMrFxzp8jXXj2ghn+VnGSeYQ988Xw0dd5D2i7nOlNSDVIfA5YbCTmAVipYNQevtqrgDYTvBEVSMq2udZMLmxPN/gpiR6QFxf6TJcxwDxTSnl5YgB/Z0vteaqNAHtx79/vEzYoH8piNwoWamV037ExxN3UVB1vIGqGA/6oqCpH5peR2fV96UynfEdVEN7TCPg3K6CuNoJsqO2w6DlIJjF1RZQAGaQuXHSKt9z95qrZvYGBg5C4ltd2c7BJUw1hliNb2fN+bISSOlSCces7+zphdBZn22ct7Ozdc+lPX6NQzlbRI/1Z0cJ4uUlK/4NmTNME8hdwP1htbT7ZVk9h3WTwUxsX+MDjG5yJfIR5l2osnT3ZvQmgZJiukKBuoeXxPe3GfCGIjhZmGKD7cAgwZuNudDSiotC2Zn/mBo5SzW/gkjS6vlVhwHvupM3/8UVBtLGAMyYWqpZjMupezVwv3t3xUD5t1HVb1MjkIZdoFOxfBKsUjMkcVhk+9EM/Lerlw9/2Td/+gDO+oNgCCNa0lCmUVbqNPYz1RBXTEovsopLdJXxZH67QVEx+AIpTRdJKs8YORUv2kdw3QKNMzAdWUgKXncXYe8sr6kS58UsUrk8NSf869Z7JzPKCl/7C37FFOT04P0GU9FBEjWMga7rIr0CzM//T1fisc9YJTwrg23eO8s6PPZODHm0QqYfZUQtOjRQ== X-OriginatorOrg: seco.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3d1e0234-b661-4db6-81cc-08da59538cbf X-MS-Exchange-CrossTenant-AuthSource: DB7PR03MB4972.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Jun 2022 22:14:20.5646 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: bebe97c3-6438-442e-ade3-ff17aa50e733 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: LtUQLoHLKOQIyUUFuoQnsRtp8rMbTVgG6jxHFLNARlr1y9chZUIgGxzT6OaiJ2V743ap8m23MjXGSW7xEjzIrg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR03MB3013 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds a binding for the SerDes module found on QorIQ processors. The phy reference has two cells, one for the first lane and one for the last. This should allow for good support of multi-lane protocols when (if) they are added. There is no protocol option, because the driver is designed to be able to completely reconfigure lanes at runtime. Generally, the phy consumer can select the appropriate protocol using set_mode. For the most part there is only one protocol controller (consumer) per lane/protocol combination. The exception to this is the B4860 processor, which has some lanes which can be connected to multiple MACs. For that processor, I anticipate the easiest way to resolve this will be to add an additional cell with a "protocol controller instance" property. Each serdes has a unique set of supported protocols (and lanes). The support matrix is stored in the driver and is selected based on the compatible string. It is anticipated that a new compatible string will need to be added for each serdes on each SoC that drivers support is added for. There is no "generic" compatible string for this reason. There are two PLLs, each of which can be used as the master clock for each lane. Each PLL has its own reference. For the moment they are required, because it simplifies the driver implementation. Absent reference clocks can be modeled by a fixed-clock with a rate of 0. Signed-off-by: Sean Anderson --- Changes in v2: - Add #clock-cells. This will allow using assigned-clocks* to configure the PLLs. - Allow a value of 1 for phy-cells. This allows for compatibility with the similar (but according to Ioana Ciornei different enough) lynx-28g binding. - Document phy cells in the description - Document the structure of the compatible strings - Fix example binding having too many cells in regs - Move compatible first - Refer to the device in the documentation, rather than the binding - Remove minItems - Rename to fsl,lynx-10g.yaml - Use list for clock-names .../devicetree/bindings/phy/fsl,lynx-10g.yaml | 93 +++++++++++++++++++ 1 file changed, 93 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml diff --git a/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml b/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml new file mode 100644 index 000000000000..b5a6f631df9f --- /dev/null +++ b/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/fsl,lynx-10g.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP Lynx 10G SerDes + +maintainers: + - Sean Anderson + +description: | + These Lynx "SerDes" devices are found in NXP's QorIQ line of processors. The + SerDes provides up to eight lanes. Each lane may be configured individually, + or may be combined with adjacent lanes for a multi-lane protocol. The SerDes + supports a variety of protocols, including up to 10G Ethernet, PCIe, SATA, and + others. The specific protocols supported for each lane depend on the + particular SoC. + +properties: + compatible: + description: | + Each compatible is of the form "fsl,-serdes-". + Although many registers are compatible between different SoCs, the + supported protocols and lane assignments tend to be unique to each SerDes. + Additionally, the method of activating protocols may also be unique. + Because of this, each SerDes instance will need its own compatible string. + In cases where two SoCs share the same SerDes implementation (such as the + LS1046A and LS1026A), both SoCs should share the same compatible strings. + enum: + - fsl,ls1046a-serdes-1 + - fsl,ls1046a-serdes-2 + + "#clock-cells": + const: 1 + description: | + The cell contains the index of the PLL, starting from 0. Note that when + assigning a rate to a PLL, the PLLs' rates are divided by 1000 to avoid + overflow. A rate of 5000000 corresponds to 5GHz. + + "#phy-cells": + minimum: 1 + maximum: 2 + description: | + The cells contain the following arguments: + - The first lane in the group. Lanes are numbered based on the register + offsets, not the I/O ports. This corresponds to the letter-based ("Lane + A") naming scheme, and not the number-based ("Lane 0") naming scheme. On + most SoCs, "Lane A" is "Lane 0", but not always. + - Last lane. For single-lane protocols, this should be the same as the + first lane. + If no lanes in a SerDes can be grouped, then #phy-cells may be 1, and the + first cell will specify the only lane in the group. + + clocks: + maxItems: 2 + description: | + Clock for each PLL reference clock input. + + clock-names: + items: + - enum: &clocks + - ref0 + - ref1 + - enum: *clocks + + reg: + maxItems: 1 + +required: + - "#clock-cells" + - "#phy-cells" + - compatible + - clocks + - clock-names + - reg + +additionalProperties: false + +examples: + - | + serdes1: phy@1ea0000 { + #clock-cells = <1>; + #phy-cells = <2>; + compatible = "fsl,ls1046a-serdes-1"; + reg = <0x1ea0000 0x2000>; + clocks = <&clk_100mhz>, <&clk_156mhz>; + clock-names = "ref0", "ref1"; + assigned-clocks = <&serdes1 0>; + assigned-clock-rates = <5000000>; + }; + +... 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Signed-off-by: Sean Anderson Reviewed-by: Rob Herring --- Changes in v2: - New .../bindings/net/fsl,fman-dtsec.yaml | 144 ++++++++++++++++++ .../devicetree/bindings/net/fsl-fman.txt | 128 +--------------- 2 files changed, 145 insertions(+), 127 deletions(-) create mode 100644 Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml diff --git a/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml b/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml new file mode 100644 index 000000000000..809df1589f20 --- /dev/null +++ b/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml @@ -0,0 +1,144 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/fsl,fman-dtsec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP FMan MAC + +maintainers: + - Madalin Bucur + +description: | + Each FMan has several MACs, each implementing an Ethernet interface. Earlier + versions of FMan used the Datapath Three Speed Ethernet Controller (dTSEC) for + 10/100/1000 MBit/s speeds, and the 10-Gigabit Ethernet Media Access Controller + (10GEC) for 10 Gbit/s speeds. Later versions of FMan use the Multirate + Ethernet Media Access Controller (mEMAC) to handle all speeds. + +properties: + compatible: + enum: + - fsl,fman-dtsec + - fsl,fman-xgec + - fsl,fman-memac + + cell-index: + maximum: 64 + description: | + FManV2: + register[bit] MAC cell-index + ============================================================ + FM_EPI[16] XGEC 8 + FM_EPI[16+n] dTSECn n-1 + FM_NPI[11+n] dTSECn n-1 + n = 1,..,5 + + FManV3: + register[bit] MAC cell-index + ============================================================ + FM_EPI[16+n] mEMACn n-1 + FM_EPI[25] mEMAC10 9 + + FM_NPI[11+n] mEMACn n-1 + FM_NPI[10] mEMAC10 9 + FM_NPI[11] mEMAC9 8 + n = 1,..8 + + FM_EPI and FM_NPI are located in the FMan memory map. + + 2. SoC registers: + + - P2041, P3041, P4080 P5020, P5040: + register[bit] FMan MAC cell + Unit index + ============================================================ + DCFG_DEVDISR2[7] 1 XGEC 8 + DCFG_DEVDISR2[7+n] 1 dTSECn n-1 + DCFG_DEVDISR2[15] 2 XGEC 8 + DCFG_DEVDISR2[15+n] 2 dTSECn n-1 + n = 1,..5 + + - T1040, T2080, T4240, B4860: + register[bit] FMan MAC cell + Unit index + ============================================================ + DCFG_CCSR_DEVDISR2[n-1] 1 mEMACn n-1 + DCFG_CCSR_DEVDISR2[11+n] 2 mEMACn n-1 + n = 1,..6,9,10 + + EVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in + the specific SoC "Device Configuration/Pin Control" Memory + Map. + + reg: + maxItems: 1 + + fsl,fman-ports: + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 2 + description: | + An array of two references: the first is the FMan RX port and the second + is the TX port used by this MAC. + + ptp-timer: + $ref: /schemas/types.yaml#/definitions/phandle + description: A reference to the IEEE1588 timer + + pcsphy-handle: + $ref: /schemas/types.yaml#/definitions/phandle + description: A reference to the PCS (typically found on the SerDes) + + tbi-handle: + $ref: /schemas/types.yaml#/definitions/phandle + description: A reference to the (TBI-based) PCS + +required: + - compatible + - cell-index + - reg + - fsl,fman-ports + - ptp-timer + +allOf: + - $ref: "ethernet-controller.yaml#" + - if: + properties: + compatible: + contains: + const: fsl,fman-dtsec + then: + required: + - tbi-handle + - if: + properties: + compatible: + contains: + const: fsl,fman-memac + then: + required: + - pcsphy-handle + +unevaluatedProperties: false + +examples: + - | + ethernet@e0000 { + compatible = "fsl,fman-dtsec"; + cell-index = <0>; + reg = <0xe0000 0x1000>; + fsl,fman-ports = <&fman1_rx8 &fman1_tx28>; + ptp-timer = <&ptp_timer>; + tbi-handle = <&tbi0>; + }; + - | + ethernet@e8000 { + cell-index = <4>; + compatible = "fsl,fman-memac"; + reg = <0xe8000 0x1000>; + fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>; + ptp-timer = <&ptp_timer0>; + pcsphy-handle = <&pcsphy4>; + phy-handle = <&sgmii_phy1>; + phy-connection-type = "sgmii"; + }; diff --git a/Documentation/devicetree/bindings/net/fsl-fman.txt b/Documentation/devicetree/bindings/net/fsl-fman.txt index 801efc7d6818..b9055335db3b 100644 --- a/Documentation/devicetree/bindings/net/fsl-fman.txt +++ b/Documentation/devicetree/bindings/net/fsl-fman.txt @@ -232,133 +232,7 @@ port@81000 { ============================================================================= FMan dTSEC/XGEC/mEMAC Node -DESCRIPTION - -mEMAC/dTSEC/XGEC are the Ethernet network interfaces - -PROPERTIES - -- compatible - Usage: required - Value type: - Definition: A standard property. - Must include one of the following: - - "fsl,fman-dtsec" for dTSEC MAC - - "fsl,fman-xgec" for XGEC MAC - - "fsl,fman-memac" for mEMAC MAC - -- cell-index - Usage: required - Value type: - Definition: Specifies the MAC id. - - The cell-index value may be used by the FMan or the SoC, to - identify the MAC unit in the FMan (or SoC) memory map. - In the tables below there's a description of the cell-index - use, there are two tables, one describes the use of cell-index - by the FMan, the second describes the use by the SoC: - - 1. FMan Registers - - FManV2: - register[bit] MAC cell-index - ============================================================ - FM_EPI[16] XGEC 8 - FM_EPI[16+n] dTSECn n-1 - FM_NPI[11+n] dTSECn n-1 - n = 1,..,5 - - FManV3: - register[bit] MAC cell-index - ============================================================ - FM_EPI[16+n] mEMACn n-1 - FM_EPI[25] mEMAC10 9 - - FM_NPI[11+n] mEMACn n-1 - FM_NPI[10] mEMAC10 9 - FM_NPI[11] mEMAC9 8 - n = 1,..8 - - FM_EPI and FM_NPI are located in the FMan memory map. - - 2. SoC registers: - - - P2041, P3041, P4080 P5020, P5040: - register[bit] FMan MAC cell - Unit index - ============================================================ - DCFG_DEVDISR2[7] 1 XGEC 8 - DCFG_DEVDISR2[7+n] 1 dTSECn n-1 - DCFG_DEVDISR2[15] 2 XGEC 8 - DCFG_DEVDISR2[15+n] 2 dTSECn n-1 - n = 1,..5 - - - T1040, T2080, T4240, B4860: - register[bit] FMan MAC cell - Unit index - ============================================================ - DCFG_CCSR_DEVDISR2[n-1] 1 mEMACn n-1 - DCFG_CCSR_DEVDISR2[11+n] 2 mEMACn n-1 - n = 1,..6,9,10 - - EVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in - the specific SoC "Device Configuration/Pin Control" Memory - Map. - -- reg - Usage: required - Value type: - Definition: A standard property. - -- fsl,fman-ports - Usage: required - Value type: - Definition: An array of two phandles - the first references is - the FMan RX port and the second is the TX port used by this - MAC. - -- ptp-timer - Usage required - Value type: - Definition: A phandle for 1EEE1588 timer. - -- pcsphy-handle - Usage required for "fsl,fman-memac" MACs - Value type: - Definition: A phandle for pcsphy. - -- tbi-handle - Usage required for "fsl,fman-dtsec" MACs - Value type: - Definition: A phandle for tbiphy. - -EXAMPLE - -fman1_tx28: port@a8000 { - cell-index = <0x28>; - compatible = "fsl,fman-v2-port-tx"; - reg = <0xa8000 0x1000>; -}; - -fman1_rx8: port@88000 { - cell-index = <0x8>; - compatible = "fsl,fman-v2-port-rx"; - reg = <0x88000 0x1000>; -}; - -ptp-timer: ptp_timer@fe000 { - compatible = "fsl,fman-ptp-timer"; - reg = <0xfe000 0x1000>; -}; - -ethernet@e0000 { - compatible = "fsl,fman-dtsec"; - cell-index = <0>; - reg = <0xe0000 0x1000>; - fsl,fman-ports = <&fman1_rx8 &fman1_tx28>; - ptp-timer = <&ptp-timer>; - tbi-handle = <&tbi0>; -}; +Refer to Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml ============================================================================ FMan IEEE 1588 Node From patchwork Tue Jun 28 22:13:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 1649722 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; 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That is, if the phy interface is RGMII, it assumed that RGMII is supported. For some interfaces, it is assumed that the RCW/bootloader has set up the SerDes properly. This is generally OK, but restricts runtime reconfiguration. The actual link state is never reported. To address these shortcomings, the driver will need additional information. First, it needs to know how to access the PCS/PMAs (in order to configure them and get the link status). The SGMII PCS/PMA is the only currently-described PCS/PMA. Add the XFI and QSGMII PCS/PMAs as well. The XFI (and 1GBase-KR) PCS/PMA is a c45 "phy" which sits on the same MDIO bus as SGMII PCS/PMA. By default they will have conflicting addresses, but they are also not enabled at the same time by default. Therefore, we can let the XFI PCS/PMA be the default when phy-connection-type is xgmii. This will allow for backwards-compatibility. QSGMII, however, cannot work with the current binding. This is because the QSGMII PCS/PMAs are only present on one MAC's MDIO bus. At the moment this is worked around by having every MAC write to the PCS/PMA addresses (without checking if they are present). This only works if each MAC has the same configuration, and only if we don't need to know the status. Because the QSGMII PCS/PMA will typically be located on a different MDIO bus than the MAC's SGMII PCS/PMA, there is no fallback for the QSGMII PCS/PMA. mEMACs (across all SoCs) support the following protocols: - MII - RGMII - SGMII, 1000Base-X, and 1000Base-KX - 2500Base-X (aka 2.5G SGMII) - QSGMII - 10GBase-R (aka XFI) and 10GBase-KR - XAUI and HiGig Each line documents a set of orthogonal protocols (e.g. XAUI is supported if and only if HiGig is supported). Additionally, - XAUI implies support for 10GBase-R - 10GBase-R is supported if and only if RGMII is not supported - 2500Base-X implies support for 1000Base-X - MII implies support for RGMII To switch between different protocols, we must reconfigure the SerDes. This is done by using the standard phys property. We can also use it to validate whether different protocols are supported (e.g. using phy_validate). This will work for serial protocols, but not RGMII or MII. Additionally, we still need to be compatible when there is no SerDes. While we can detect 10G support by examining the port speed (as set by fsl,fman-10g-port), we cannot determine support for any of the other protocols based on the existing binding. In fact, the binding works against us in some respects, because pcsphy-handle is required even if there is no possible PCS/PMA for that MAC. To allow for backwards- compatibility, we use a boolean-style property for RGMII (instead of presence/absence-style). When the property for RGMII is missing, we will assume that it is supported. The exception is MII, since no existing device trees use it (as far as I could tell). Unfortunately, QSGMII support will be broken for old device trees. There is nothing we can do about this because of the PCS/PMA situation (as described above). Signed-off-by: Sean Anderson --- Changes in v2: - Better document how we select which PCS to use in the default case .../bindings/net/fsl,fman-dtsec.yaml | 52 +++++++++++++++++-- .../devicetree/bindings/net/fsl-fman.txt | 5 +- 2 files changed, 51 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml b/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml index 809df1589f20..ecb772258164 100644 --- a/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml +++ b/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml @@ -85,9 +85,41 @@ properties: $ref: /schemas/types.yaml#/definitions/phandle description: A reference to the IEEE1588 timer + phys: + description: A reference to the SerDes lane(s) + maxItems: 1 + + phy-names: + items: + - const: serdes + pcsphy-handle: - $ref: /schemas/types.yaml#/definitions/phandle - description: A reference to the PCS (typically found on the SerDes) + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 1 + maxItems: 3 + description: | + A reference to the various PCSs (typically found on the SerDes). If + pcs-names is absent, and phy-connection-type is "xgmii", then the first + reference will be assumed to be for "xfi". Otherwise, if pcs-names is + absent, then the first reference will be assumed to be for "sgmii". + + pcs-names: + $ref: /schemas/types.yaml#/definitions/string-array + minItems: 1 + maxItems: 3 + contains: + enum: + - sgmii + - qsgmii + - xfi + description: The type of each PCS in pcsphy-handle. + + rgmii: + enum: [0, 1] + description: 1 indicates RGMII is supported, and 0 indicates it is not. + + mii: + description: If present, indicates that MII is supported. tbi-handle: $ref: /schemas/types.yaml#/definitions/phandle @@ -100,6 +132,10 @@ required: - fsl,fman-ports - ptp-timer +dependencies: + pcs-names: [pcsphy-handle] + mii: [rgmii] + allOf: - $ref: "ethernet-controller.yaml#" - if: @@ -117,7 +153,11 @@ allOf: const: fsl,fman-memac then: required: - - pcsphy-handle + - rgmii + else: + properties: + rgmii: false + mii: false unevaluatedProperties: false @@ -138,7 +178,11 @@ examples: reg = <0xe8000 0x1000>; fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>; ptp-timer = <&ptp_timer0>; - pcsphy-handle = <&pcsphy4>; + pcsphy-handle = <&pcsphy4>, <&qsgmiib_pcs1>; + pcs-names = "sgmii", "qsgmii"; + rgmii = <0>; phy-handle = <&sgmii_phy1>; phy-connection-type = "sgmii"; + phys = <&serdes1 1>; + phy-names = "serdes"; }; diff --git a/Documentation/devicetree/bindings/net/fsl-fman.txt b/Documentation/devicetree/bindings/net/fsl-fman.txt index b9055335db3b..bda4b41af074 100644 --- a/Documentation/devicetree/bindings/net/fsl-fman.txt +++ b/Documentation/devicetree/bindings/net/fsl-fman.txt @@ -320,8 +320,9 @@ For internal PHY device on internal mdio bus, a PHY node should be created. See the definition of the PHY node in booting-without-of.txt for an example of how to define a PHY (Internal PHY has no interrupt line). - For "fsl,fman-mdio" compatible internal mdio bus, the PHY is TBI PHY. -- For "fsl,fman-memac-mdio" compatible internal mdio bus, the PHY is PCS PHY, - PCS PHY addr must be '0'. +- For "fsl,fman-memac-mdio" compatible internal mdio bus, the PHY is PCS PHY. + The PCS PHY address should correspond to the value of the appropriate + MDEV_PORT. EXAMPLE