From patchwork Wed Jun 22 23:28:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 1646821 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=sR9tuy2p; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4LT02T60Vpz9sGT for ; Thu, 23 Jun 2022 09:29:05 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377397AbiFVX3D (ORCPT ); Wed, 22 Jun 2022 19:29:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42426 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377315AbiFVX3B (ORCPT ); Wed, 22 Jun 2022 19:29:01 -0400 Received: from mail-pg1-x52b.google.com (mail-pg1-x52b.google.com [IPv6:2607:f8b0:4864:20::52b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2F13442496 for ; Wed, 22 Jun 2022 16:29:00 -0700 (PDT) Received: by mail-pg1-x52b.google.com with SMTP id g186so17492370pgc.1 for ; Wed, 22 Jun 2022 16:29:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=taA4YjgWvV99Z+5gpnQ8XrMulC3QNgu40JSaIUYRH3Y=; b=sR9tuy2ptgdw2x4wFEKvJRZgW4d3TfkX7t5Fx3nsCw5Xmb/z4txTlsUDixofKjVYUB rYLrmILD9S8Xncnj/AjuEppmrxhFSF89CWcGFQFhLA+T1FipS0laYeulDAA1XX/7WRHb uuLXJ1ieKgiAsa7+AL0pXuDIfcfez5mn0Qte01Cicwqh1av9XlBxyvkwEiElfWhS98k4 Wmq5Kv72pM0sNGFnFFw1Ej+mgfo63B2Ncue66uzAqJ6fuo9XeunNqaT2xfw9H38SXNPj 1FGD+XG1ICaR71bo3F653Ya1nYCCQFDGdSjzyNsaH6MlnYJq9WCGtizwOhlEI6nXfu2A NZbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=taA4YjgWvV99Z+5gpnQ8XrMulC3QNgu40JSaIUYRH3Y=; b=hKG0Zs34p/zCvnx/Lm0bBf8DGWnjCl5XeSB3pfrZ2Q5BjYHLXm+QMZTqPy/ebY8vxz fubqqij4LUJKd4zlB8fhGH6TcsHv7ZXC2LYYt6KsBudntuYuGQZOAWzqsTZtudoqL2nW AAAagUYdPzdZIMa9fxKQbUwscxu62UqxsvhT4u+KY90WOxTGzejjRkE8mKlqShLPXOYc SG2s0+spRVC20Qydp0c2IKSjk4PqAhuTtrtxeVOmhdyxYtQzkMlnIhcds0pvsfXJmbjz ZuZ/Wu6MIzDgOuxzVguMo7VA30/YjpNjh6as3sU7RR/b35EfGa0reklJ1nQRMmMLVges Po8g== X-Gm-Message-State: AJIora8i2yij1DRIutU1L874+hz4pU4Eb1UFjeL2RpoRTuleQhGbjSEo iBu1mkCGCMCinR1labIS/ADWbw== X-Google-Smtp-Source: AGRyM1voV+0Ov7WIkdT3h2SRcQMkpYlYcQeORgjCSvM1Q0xARrs/81EAYxIJfHB7wbmXr2oxcz/+tA== X-Received: by 2002:a05:6a00:b4f:b0:525:3505:53db with SMTP id p15-20020a056a000b4f00b00525350553dbmr11858683pfo.22.1655940539689; Wed, 22 Jun 2022 16:28:59 -0700 (PDT) Received: from prec5560.. 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[71.212.119.14]) by smtp.gmail.com with ESMTPSA id h2-20020a170902f70200b001622c377c3esm13297863plo.117.2022.06.22.16.28.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jun 2022 16:28:59 -0700 (PDT) From: Robert Foss To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzk+dt@kernel.org, jonathan@marek.ca, robert.foss@linaro.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Konrad Dybcio Cc: Dmitry Baryshkov , Rob Herring Subject: [PATCH v7 3/6] dt-bindings: clock: Add Qcom SM8350 GPUCC bindings Date: Thu, 23 Jun 2022 01:28:43 +0200 Message-Id: <20220622232846.852771-4-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220622232846.852771-1-robert.foss@linaro.org> References: <20220622232846.852771-1-robert.foss@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM8350 SoCs. Signed-off-by: Robert Foss Reviewed-by: Dmitry Baryshkov Reviewed-by: Rob Herring --- Changes since v3 - Separate from qcom,gpucc - Remove clock-names - Make example sm8350 based - Changed author to me due to size of changes Changes since v5 - Add Ack - Rob Changes since v5 - Reverted split from dispcc-sm8250 - Re-added tags from v3 .../bindings/clock/qcom,gpucc-sm8350.yaml | 72 +++++++++++++++++++ include/dt-bindings/clock/qcom,gpucc-sm8350.h | 52 ++++++++++++++ 2 files changed, 124 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml create mode 100644 include/dt-bindings/clock/qcom,gpucc-sm8350.h diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml new file mode 100644 index 000000000000..0a0546c079a9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gpucc-sm8350.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller Binding + +maintainers: + - Robert Foss + +description: | + Qualcomm graphics clock control module which supports the clocks, resets and + power domains on Qualcomm SoCs. + + See also: + dt-bindings/clock/qcom,gpucc-sm8350.h + +properties: + compatible: + enum: + - qcom,sm8350-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 div branch source + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@3d90000 { + compatible = "qcom,sm8350-gpucc"; + reg = <0 0x03d90000 0 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/include/dt-bindings/clock/qcom,gpucc-sm8350.h b/include/dt-bindings/clock/qcom,gpucc-sm8350.h new file mode 100644 index 000000000000..2ca857f5bfd2 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gpucc-sm8350.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CB_CLK 1 +#define GPU_CC_CRC_AHB_CLK 2 +#define GPU_CC_CX_APB_CLK 3 +#define GPU_CC_CX_GMU_CLK 4 +#define GPU_CC_CX_QDSS_AT_CLK 5 +#define GPU_CC_CX_QDSS_TRIG_CLK 6 +#define GPU_CC_CX_QDSS_TSCTR_CLK 7 +#define GPU_CC_CX_SNOC_DVM_CLK 8 +#define GPU_CC_CXO_AON_CLK 9 +#define GPU_CC_CXO_CLK 10 +#define GPU_CC_FREQ_MEASURE_CLK 11 +#define GPU_CC_GMU_CLK_SRC 12 +#define GPU_CC_GX_GMU_CLK 13 +#define GPU_CC_GX_QDSS_TSCTR_CLK 14 +#define GPU_CC_GX_VSENSE_CLK 15 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 16 +#define GPU_CC_HUB_AHB_DIV_CLK_SRC 17 +#define GPU_CC_HUB_AON_CLK 18 +#define GPU_CC_HUB_CLK_SRC 19 +#define GPU_CC_HUB_CX_INT_CLK 20 +#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 21 +#define GPU_CC_MND1X_0_GFX3D_CLK 22 +#define GPU_CC_MND1X_1_GFX3D_CLK 23 +#define GPU_CC_PLL0 24 +#define GPU_CC_PLL1 25 +#define GPU_CC_SLEEP_CLK 26 + +/* GPU_CC resets */ +#define GPUCC_GPU_CC_ACD_BCR 0 +#define GPUCC_GPU_CC_CB_BCR 1 +#define GPUCC_GPU_CC_CX_BCR 2 +#define GPUCC_GPU_CC_FAST_HUB_BCR 3 +#define GPUCC_GPU_CC_GFX3D_AON_BCR 4 +#define GPUCC_GPU_CC_GMU_BCR 5 +#define GPUCC_GPU_CC_GX_BCR 6 +#define GPUCC_GPU_CC_XO_BCR 7 + +/* GPU_CC GDSCRs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif From patchwork Wed Jun 22 23:28:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 1646822 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=ei6RTPZ9; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4LT02V3cSnz9sGq for ; Thu, 23 Jun 2022 09:29:06 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377349AbiFVX3E (ORCPT ); Wed, 22 Jun 2022 19:29:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42422 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377329AbiFVX3D (ORCPT ); Wed, 22 Jun 2022 19:29:03 -0400 Received: from mail-pl1-x62b.google.com (mail-pl1-x62b.google.com [IPv6:2607:f8b0:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9FCDE424BA for ; Wed, 22 Jun 2022 16:29:01 -0700 (PDT) Received: by mail-pl1-x62b.google.com with SMTP id c4so480374plc.8 for ; Wed, 22 Jun 2022 16:29:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pmY3BQeKr6HNZamJdk1pXbKYfHfWmqktvBcsQ334LDY=; b=ei6RTPZ9vH8DnF9G3PzTLop0ewfGFU+23vFIWb/JTqsVuaRsiNKUg18nd2RATOjyv4 ThKjrjGyiTwUB/rZCHdslMD8wamkoDYmXS9GZGqKCNAFo41w/Ll1XRxiyiZrQaBz6RxB HSG8/Uqyz5UjETN7k/Dmr+2N+mefCv68mE+L3iWA62YlEiW3QLxIoWGkjFWgK8eIbJgF f3kCsf6JV84VqTw/aH9i3cfw8OUGxZrW9SpfRYBngoIVQNVtQlt9iFYdFbrijyYm5jWZ clVCiy4srX+mFkVZg33d9MViJAPLs1zAF0+0kSC7thkYn6XdGB9jX6e01hMQxTWgZnr/ ItDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pmY3BQeKr6HNZamJdk1pXbKYfHfWmqktvBcsQ334LDY=; b=C4wWIJWYLRKufAV3kvNJf/RrTVZEDTh0VCNXDAkhwkOVCUEz/4iPfs4OM+P4Ta6Yla RZ4tAuSgJmvmbLS8ux2dksWan619ngHssdVKglDs8VfcuUNxH2p7ADCqmRwLtO8pHoHP wGDOS+eo6UcvawSU7FADcMEDmGHmJ168hnkOwUP2gPidv1Q1jiDogllIyGD3k/Daj4h5 l5yKiEtXOSv9o2piMOyG/EvfmR9BuVwPB7ZW76bcUVRcqbHNHA7+RUC5X6Dlktt/ckFJ btS48Wn8Ytcp65O8Fkz5wffOfjhtYETOY9e/lLtO9fEGwfb3D9N9/h3glh2+VV3Jr5gH QWDw== X-Gm-Message-State: AJIora/nZH7Oyiqxycfx+RDeHvdsF/Kmn310X3UFISQSbif827ay7+dN LxmKet4QqvJGLn+D8x8nY3oixQ== X-Google-Smtp-Source: AGRyM1vN3xfnz9Nx4yEi9yMlLNM4FNrHnm75NNKNj02YiMc9gRXLTOFU8gkF6GNx6+fluTT9yEf/PA== X-Received: by 2002:a17:902:ccc1:b0:168:d8ce:4a66 with SMTP id z1-20020a170902ccc100b00168d8ce4a66mr35676949ple.160.1655940541313; Wed, 22 Jun 2022 16:29:01 -0700 (PDT) Received: from prec5560.. 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[71.212.119.14]) by smtp.gmail.com with ESMTPSA id h2-20020a170902f70200b001622c377c3esm13297863plo.117.2022.06.22.16.29.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jun 2022 16:29:01 -0700 (PDT) From: Robert Foss To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzk+dt@kernel.org, jonathan@marek.ca, robert.foss@linaro.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Konrad Dybcio Cc: Rob Herring Subject: [PATCH v7 5/6] dt-bindings: clock: Add Qcom SM8350 DISPCC bindings Date: Thu, 23 Jun 2022 01:28:45 +0200 Message-Id: <20220622232846.852771-6-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220622232846.852771-1-robert.foss@linaro.org> References: <20220622232846.852771-1-robert.foss@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Jonathan Marek Add sm8350 DISPCC bindings, which are simply a symlink to the sm8250 bindings. Update the documentation with the new compatible. Signed-off-by: Jonathan Marek Signed-off-by: Robert Foss Reviewed-by: Rob Herring Reviewed-by: Dmitry Baryshkov Reviewed-by: Vinod Koul --- Changes since v2 - Add SoB - Bjorn Changes since v3 - Separate from qcom,dispcc-sm8x50 - Remove clock-names - Make example sm8350 based - Changed author to me due to size of changes Changes since v4 - Add RB - Rob Changes since v5 - Reverted split from dispcc-sm8250 - Re-added tags from v3 .../devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml | 6 ++++-- include/dt-bindings/clock/qcom,dispcc-sm8350.h | 1 + 2 files changed, 5 insertions(+), 2 deletions(-) create mode 120000 include/dt-bindings/clock/qcom,dispcc-sm8350.h diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml index 31497677e8de..7a8d375e055e 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml @@ -4,18 +4,19 @@ $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250 +title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250/SM8350 maintainers: - Jonathan Marek description: | Qualcomm display clock control module which supports the clocks, resets and - power domains on SM8150 and SM8250. + power domains on SM8150/SM8250/SM8350. See also: dt-bindings/clock/qcom,dispcc-sm8150.h dt-bindings/clock/qcom,dispcc-sm8250.h + dt-bindings/clock/qcom,dispcc-sm8350.h properties: compatible: @@ -23,6 +24,7 @@ properties: - qcom,sc8180x-dispcc - qcom,sm8150-dispcc - qcom,sm8250-dispcc + - qcom,sm8350-dispcc clocks: items: diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8350.h b/include/dt-bindings/clock/qcom,dispcc-sm8350.h new file mode 120000 index 000000000000..0312b4544acb --- /dev/null +++ b/include/dt-bindings/clock/qcom,dispcc-sm8350.h @@ -0,0 +1 @@ +qcom,dispcc-sm8250.h \ No newline at end of file