From patchwork Mon Jun 13 20:35:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Desnoyers X-Patchwork-Id: 1643013 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; secure) header.d=sourceware.org header.i=@sourceware.org header.a=rsa-sha256 header.s=default header.b=AslfeEy+; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=sourceware.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=libc-alpha-bounces+incoming=patchwork.ozlabs.org@sourceware.org; receiver=) Received: from sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LMNdT44tfz9ryY for ; Tue, 14 Jun 2022 06:36:29 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B79933851C0C for ; Mon, 13 Jun 2022 20:36:25 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B79933851C0C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1655152585; bh=6XtVJuA38s/HTKYd25VGZgqkXCEsLJ/aBV2ZMXs+J6k=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=AslfeEy+swymplSZDO1IQxhQLkCMsbuniiumzRAYDQCtoqjvVfLQkKR+T7S9nm0TZ WJsIP8EQtHYWZY6H4Vf+dmBqVXoi0vLnjtef1H+EJIGr43WmQLfPcZhJ7a504j7hr0 amo99WwKZKNJtGn25X+F+cD4aDFdKkgaPKI1KNXc= X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mail.efficios.com (mail.efficios.com [167.114.26.124]) by sourceware.org (Postfix) with ESMTPS id 1D20C3858C27 for ; Mon, 13 Jun 2022 20:36:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 1D20C3858C27 Received: from localhost (localhost [127.0.0.1]) by mail.efficios.com (Postfix) with ESMTP id 26DED3B5A24; Mon, 13 Jun 2022 16:36:09 -0400 (EDT) Received: from mail.efficios.com ([127.0.0.1]) by localhost (mail03.efficios.com [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id 2g-Ba2PGBL9m; Mon, 13 Jun 2022 16:36:05 -0400 (EDT) Received: from localhost (localhost [127.0.0.1]) by mail.efficios.com (Postfix) with ESMTP id 410B33B5A22; Mon, 13 Jun 2022 16:36:05 -0400 (EDT) DKIM-Filter: OpenDKIM Filter v2.10.3 mail.efficios.com 410B33B5A22 X-Virus-Scanned: amavisd-new at efficios.com Received: from mail.efficios.com ([127.0.0.1]) by localhost (mail03.efficios.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id 13k5H5f3qR5Y; Mon, 13 Jun 2022 16:36:05 -0400 (EDT) Received: from thinkos.internal.efficios.com (192-222-180-24.qc.cable.ebox.net [192.222.180.24]) by mail.efficios.com (Postfix) with ESMTPSA id 1F3593B5576; Mon, 13 Jun 2022 16:36:05 -0400 (EDT) To: Florian Weimer Subject: [PATCH] linux: add RISC-V rseq signature Date: Mon, 13 Jun 2022 16:35:54 -0400 Message-Id: <20220613203554.824652-1-mathieu.desnoyers@efficios.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Mathieu Desnoyers via Libc-alpha From: Mathieu Desnoyers Reply-To: Mathieu Desnoyers Cc: Mathieu Desnoyers , libc-alpha@sourceware.org, Michael Jeanson Errors-To: libc-alpha-bounces+incoming=patchwork.ozlabs.org@sourceware.org Sender: "Libc-alpha" From: Michael Jeanson The rseq syscall for the RISC-V architecture was added in Linux 5.18. Signed-off-by: Michael Jeanson Signed-off-by: Mathieu Desnoyers --- sysdeps/unix/sysv/linux/riscv/bits/rseq.h | 43 +++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 sysdeps/unix/sysv/linux/riscv/bits/rseq.h diff --git a/sysdeps/unix/sysv/linux/riscv/bits/rseq.h b/sysdeps/unix/sysv/linux/riscv/bits/rseq.h new file mode 100644 index 0000000000..7cb4e5f284 --- /dev/null +++ b/sysdeps/unix/sysv/linux/riscv/bits/rseq.h @@ -0,0 +1,43 @@ +/* Restartable Sequences Linux RISC-V architecture header. + Copyright (C) 2021-2022 Free Software Foundation, Inc. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#ifndef _SYS_RSEQ_H +# error "Never use directly; include instead." +#endif + +#include + +/* + RSEQ_SIG is a signature required before each abort handler code. + + It is a 32-bit value that maps to actual architecture code compiled + into applications and libraries. It needs to be defined for each + architecture. When choosing this value, it needs to be taken into + account that generating invalid instructions may have ill effects on + tools like objdump, and may also have impact on the CPU speculative + execution efficiency in some cases. + + Select the instruction "csrw mhartid, x0" as the RSEQ_SIG. Unlike + other architectures, the ebreak instruction has no immediate field for + distinguishing purposes. Hence, ebreak is not suitable as RSEQ_SIG. + "csrw mhartid, x0" can also satisfy the RSEQ requirement because it + is an uncommon instruction and will raise an illegal instruction + exception when executed in all modes. */ + +#if __BYTE_ORDER == __LITTLE_ENDIAN +#define RSEQ_SIG 0xf1401073 +#endif