From patchwork Mon Jun 13 11:57:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 1642869 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4LMF4X07PYz9s75 for ; Tue, 14 Jun 2022 00:55:56 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1386383AbiFMOzy (ORCPT ); Mon, 13 Jun 2022 10:55:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45626 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1387207AbiFMOy7 (ORCPT ); Mon, 13 Jun 2022 10:54:59 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 8C6FED2444; Mon, 13 Jun 2022 04:57:46 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.91,297,1647270000"; d="scan'208";a="122758903" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 13 Jun 2022 20:57:22 +0900 Received: from localhost.localdomain (unknown [10.166.15.32]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id E8150422104E; Mon, 13 Jun 2022 20:57:21 +0900 (JST) From: Yoshihiro Shimoda To: lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com, krzk+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com Cc: marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH 1/7] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host Date: Mon, 13 Jun 2022 20:57:06 +0900 Message-Id: <20220613115712.2831386-2-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220613115712.2831386-1-yoshihiro.shimoda.uh@renesas.com> References: <20220613115712.2831386-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,KHOP_HELO_FCRDNS, SPF_HELO_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Document bindings for Renesas R-Car Gen4 and R-Car S4-8 (R8A779F0) PCIe host module. Signed-off-by: Yoshihiro Shimoda --- .../bindings/pci/rcar-gen4-pci-host.yaml | 104 ++++++++++++++++++ 1 file changed, 104 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml diff --git a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml new file mode 100644 index 000000000000..8caa9824d6ca --- /dev/null +++ b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml @@ -0,0 +1,104 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022 Renesas Electronics Corp. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/rcar-gen4-pci-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car Gen4 PCIe Host + +maintainers: + - Yoshihiro Shimoda + +allOf: + - $ref: snps,dw-pcie.yaml# + +properties: + compatible: + items: + - const: renesas,r8a779f0-pcie # R-Car S4-8 + - const: renesas,rcar-gen4-pcie # R-Car Gen4 + - const: snps,dw-pcie + + interrupts: + maxItems: 6 + + interrupt-names: + items: + - const: msi + - const: err + - const: fatal + - const: nonfatal + - const: lp + - const: vndmsg + + clocks: + maxItems: 2 + + clock-names: + items: + - const: pcie + - const: pcie_bus + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - power-domains + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie: pcie@e65d0000 { + compatible = "renesas,r8a779f0-pcie", "renesas,rcar-gen4-pcie", + "snps,dw-pcie"; + reg = <0 0xe65d0000 0 0x3000>, <0 0xe65d3000 0 0x2000>, + <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x1000>, + <0 0xfe000000 0 0x10000>; + reg-names = "dbi", "atu", "app", "phy", "config"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x81000000 0 0x00000000 0 0xfe000000 0 0x00010000 + 0x82000000 0 0x30000000 0 0x30000000 0 0x10000000>; + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = , + , + , + , + , + ; + interrupt-names = "msi", "err", "fatal", "nonfatal", "lp", "vndmsg"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 624>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 624>; + num-lanes = <2>; + snps,enable-cdm-check; + max-link-speed = <2>; + }; + }; From patchwork Mon Jun 13 11:57:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 1642873 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4LMF540GjCz9s2R for ; Tue, 14 Jun 2022 00:56:24 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1386364AbiFMO4S (ORCPT ); Mon, 13 Jun 2022 10:56:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51888 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357922AbiFMOzz (ORCPT ); Mon, 13 Jun 2022 10:55:55 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 8F960D2470; Mon, 13 Jun 2022 04:57:53 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.91,297,1647270000"; d="scan'208";a="124235797" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 13 Jun 2022 20:57:22 +0900 Received: from localhost.localdomain (unknown [10.166.15.32]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 12BF24221054; Mon, 13 Jun 2022 20:57:22 +0900 (JST) From: Yoshihiro Shimoda To: lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com, krzk+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com Cc: marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH 2/7] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Endpoint Date: Mon, 13 Jun 2022 20:57:07 +0900 Message-Id: <20220613115712.2831386-3-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220613115712.2831386-1-yoshihiro.shimoda.uh@renesas.com> References: <20220613115712.2831386-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,KHOP_HELO_FCRDNS, SPF_HELO_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Document bindings for Renesas R-Car Gen4 and R-Car S4-8 (R8A779F0) PCIe endpoint module. Signed-off-by: Yoshihiro Shimoda --- .../bindings/pci/rcar-gen4-pci-ep.yaml | 111 ++++++++++++++++++ 1 file changed, 111 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml diff --git a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml new file mode 100644 index 000000000000..654efdb3a51e --- /dev/null +++ b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022 Renesas Electronics Corp. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/rcar-gen4-pci-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car Gen4 PCIe Endpoint + +maintainers: + - Yoshihiro Shimoda + +allOf: + - $ref: snps,dw-pcie-ep.yaml# + +properties: + compatible: + items: + - const: renesas,r8a779f0-pcie-ep # R-Car S4-8 + - const: renesas,rcar-gen4-pcie-ep # R-Car Gen4 + - const: snps,dw-pcie-ep + + reg: + maxItems: 4 + + reg-names: + items: + - const: dbi + - const: atu + - const: appl + - const: addr_space + + interrupts: + maxItems: 6 + + interrupt-names: + items: + - const: msi + - const: err + - const: fatal + - const: nonfatal + - const: lp + - const: vndmsg + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: pcie + - const: pcie_bus + + num-ib-windows: true + + num-ob-windows: true + + max-link-speed: true + + num-lanes: true + +required: + - compatible + - reg + - reg-names + - interrupts + - resets + - power-domains + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie0_ep: pcie-ep@e65d0000 { + compatible = "renesas,r8a779f0-pcie-ep", "renesas,rcar-gen4-pcie-ep", + "snps,dw-pcie-ep"; + reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d1000 0 0x1000>, + <0 0xe65d3000 0 0x2000>, <0 0xfe000000 0 0x400000>; + reg-names = "dbi", "atu", "appl", "addr_space"; + interrupts = , + , + , + , + , + ; + interrupt-names = "msi", "err", "fatal", "nonfatal", "lp", "vndmsg"; + clocks = <&cpg CPG_MOD 624>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 624>; + num-lanes = <2>; + max-link-speed = <2>; + num-ib-windows = <16>; + num-ob-windows = <16>; + }; + }; From patchwork Mon Jun 13 11:57:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 1642874 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4LMF580jvzz9s75 for ; Tue, 14 Jun 2022 00:56:28 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1356375AbiFMO4T (ORCPT ); Mon, 13 Jun 2022 10:56:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51892 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1386390AbiFMOzz (ORCPT ); Mon, 13 Jun 2022 10:55:55 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 49C35D2473; Mon, 13 Jun 2022 04:57:54 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.91,297,1647270000"; d="scan'208";a="122758907" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 13 Jun 2022 20:57:22 +0900 Received: from localhost.localdomain (unknown [10.166.15.32]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 31EDB422104E; Mon, 13 Jun 2022 20:57:22 +0900 (JST) From: Yoshihiro Shimoda To: lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com, krzk+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com Cc: marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH 3/7] PCI: renesas: Add R-Car Gen4 PCIe Host support Date: Mon, 13 Jun 2022 20:57:08 +0900 Message-Id: <20220613115712.2831386-4-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220613115712.2831386-1-yoshihiro.shimoda.uh@renesas.com> References: <20220613115712.2831386-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,KHOP_HELO_FCRDNS, SPF_HELO_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add R-Car Gen4 PCIe Host support. This controller is based on Synopsys Designware PCIe. Signed-off-by: Yoshihiro Shimoda --- drivers/pci/controller/dwc/Kconfig | 9 + drivers/pci/controller/dwc/Makefile | 1 + .../pci/controller/dwc/pcie-rcar-gen4-host.c | 235 ++++++++++++++++++ drivers/pci/controller/dwc/pcie-rcar-gen4.c | 198 +++++++++++++++ drivers/pci/controller/dwc/pcie-rcar-gen4.h | 59 +++++ 5 files changed, 502 insertions(+) create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4-host.c create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4.c create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4.h diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index 62ce3abf0f19..3ddccc9c38c5 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -384,4 +384,13 @@ config PCIE_FU740 Say Y here if you want PCIe controller support for the SiFive FU740. +config PCIE_RCAR_GEN4 + bool "Renesas R-Car Gen4 PCIe Host controller" + depends on ARCH_RENESAS || COMPILE_TEST + depends on PCI_MSI_IRQ_DOMAIN + select PCIE_DW_HOST + help + Say Y here if you want PCIe host controller support on R-Car Gen4 SoCs. + This uses the DesignWare core. + endmenu diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile index 8ba7b67f5e50..b3f285e685f9 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_PCIE_TEGRA194) += pcie-tegra194.o obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o obj-$(CONFIG_PCIE_VISCONTI_HOST) += pcie-visconti.o +obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4.o pcie-rcar-gen4-host.o # The following drivers are for devices that use the generic ACPI # pci_root.c driver but don't support standard ECAM config access. diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4-host.c b/drivers/pci/controller/dwc/pcie-rcar-gen4-host.c new file mode 100644 index 000000000000..788cd0206528 --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4-host.c @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCIe host controller driver for Renesas R-Car Gen4 Series SoCs + * Copyright (C) 2022 Renesas Electronics Corporation + */ + +#include +#include +#include +#include +#include + +#include "pcie-rcar-gen4.h" +#include "pcie-designware.h" + +/* ASPM L1 PM Substates */ +#define L1PSCAP(x) (0x01bc + (x)) + +static int rcar_gen4_pcie_host_init(struct pcie_port *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + int ret; + + dw_pcie_setup_rc(pp); + + dw_pcie_dbi_ro_wr_en(pci); + + /* Set Max Link Width */ + rcar_gen4_pcie_set_max_link_width(pci, pci->num_lanes); + + dw_pcie_dbi_ro_wr_dis(pci); + + if (!dw_pcie_link_up(pci)) { + ret = pci->ops->start_link(pci); + if (ret) + return ret; + } + + /* Ignore errors, the link may come up later */ + if (dw_pcie_wait_for_link(pci)) + dev_info(pci->dev, "PCIe link down\n"); + + return 0; +} + +static const struct dw_pcie_host_ops rcar_gen4_pcie_host_ops = { + .host_init = rcar_gen4_pcie_host_init, +}; + +static int rcar_gen4_add_pcie_port(struct rcar_gen4_pcie *pcie, + struct platform_device *pdev) +{ + struct dw_pcie *pci = pcie->pci; + struct pcie_port *pp = &pci->pp; + u32 val; + int ret; + + if (IS_ENABLED(CONFIG_PCI_MSI)) { + pp->msi_irq = platform_get_irq_byname(pdev, "msi"); + if (pp->msi_irq < 0) + return pp->msi_irq; + + /* Enable MSI interrupt signal */ + val = rcar_gen4_pcie_readl(pcie, PCIEINTSTS0EN); + val |= MSI_CTRL_INT; + rcar_gen4_pcie_writel(pcie, PCIEINTSTS0EN, val); + } + + pp->ops = &rcar_gen4_pcie_host_ops; + + ret = dw_pcie_host_init(pp); + if (ret) { + dev_err(&pdev->dev, "Failed to initialize host\n"); + return ret; + } + + return 0; +} + +static void rcar_gen4_remove_pcie_port(struct rcar_gen4_pcie *pcie) +{ + dw_pcie_host_deinit(&pcie->pci->pp); +} + +static void rcar_gen4_pcie_init_rc(struct rcar_gen4_pcie *pcie, u32 num_lanes) +{ + struct dw_pcie *pci = pcie->pci; + int val; + + /* Device type selection - Root Complex */ + val = rcar_gen4_pcie_readl(pcie, PCIEMSR0); + val |= DEVICE_TYPE_RC; + if (num_lanes < 4) + val |= BIFUR_MOD_SET_ON; + rcar_gen4_pcie_writel(pcie, PCIEMSR0, val); + + dw_pcie_dbi_ro_wr_en(pci); + + /* Enable L1 Substates */ + val = dw_pcie_readl_dbi(pci, L1PSCAP(PCI_L1SS_CTL1)); + val &= ~PCI_L1SS_CTL1_L1SS_MASK; + val |= PCI_L1SS_CTL1_PCIPM_L1_2 | PCI_L1SS_CTL1_PCIPM_L1_1 | + PCI_L1SS_CTL1_ASPM_L1_2 | PCI_L1SS_CTL1_ASPM_L1_1; + dw_pcie_writel_dbi(pci, L1PSCAP(PCI_L1SS_CTL1), val); + + /* Disable BARs */ + dw_pcie_writel_dbi(pci, SHADOW_REG(BAR0MASKF), 0x0); + dw_pcie_writel_dbi(pci, SHADOW_REG(BAR1MASKF), 0x0); + + /* Set Root Control */ + val = dw_pcie_readl_dbi(pci, EXPCAP(PCI_EXP_RTCTL)); + val |= PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE | + PCI_EXP_RTCTL_SEFEE | PCI_EXP_RTCTL_PMEIE | + PCI_EXP_RTCTL_CRSSVE; + dw_pcie_writel_dbi(pci, EXPCAP(PCI_EXP_RTCTL), val); + + /* Set Interrupt Disable, SERR# Enable, Parity Error Response */ + val = dw_pcie_readl_dbi(pci, PCI_COMMAND); + val |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR | + PCI_COMMAND_INTX_DISABLE; + dw_pcie_writel_dbi(pci, PCI_COMMAND, val); + + /* Enable SERR */ + val = dw_pcie_readb_dbi(pci, PCI_BRIDGE_CONTROL); + val |= PCI_BRIDGE_CTL_SERR; + dw_pcie_writeb_dbi(pci, PCI_BRIDGE_CONTROL, val); + + /* Device control */ + val = dw_pcie_readl_dbi(pci, EXPCAP(PCI_EXP_DEVCTL)); + val |= PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | + PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE; + dw_pcie_writel_dbi(pci, EXPCAP(PCI_EXP_DEVCTL), val); + + dw_pcie_dbi_ro_wr_dis(pci); +} + +static int rcar_gen4_pcie_get_resources(struct rcar_gen4_pcie *pcie, + struct platform_device *pdev) +{ + struct dw_pcie *pci = pcie->pci; + struct resource *res; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); + pci->dbi_base = devm_pci_remap_cfg_resource(pci->dev, res); + if (IS_ERR(pci->dbi_base)) + return PTR_ERR(pci->dbi_base); + + /* Renesas-specific registers */ + pcie->base = devm_platform_ioremap_resource_byname(pdev, "app"); + if (IS_ERR(pcie->base)) + return PTR_ERR(pcie->base); + + return rcar_gen4_pcie_devm_clk_and_reset_get(pcie, pci->dev); +} + +static int rcar_gen4_pcie_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct rcar_gen4_pcie *pcie; + struct device_node *np = dev->of_node; + int err; + u32 num_lanes; + + pcie = rcar_gen4_pcie_devm_alloc(dev); + if (!pcie) + return -ENOMEM; + + err = rcar_gen4_pcie_pm_runtime_enable(dev); + if (err < 0) { + dev_err(dev, "pm_runtime_get_sync failed\n"); + return err; + } + + err = rcar_gen4_pcie_get_resources(pcie, pdev); + if (err < 0) { + dev_err(dev, "failed to request resource: %d\n", err); + goto err_pm_put; + } + + err = of_property_read_u32(np, "num-lanes", &num_lanes); + if (err < 0) { + dev_err(dev, "num-lanes not found %d\n", err); + goto err_pm_put; + } + + platform_set_drvdata(pdev, pcie); + + err = rcar_gen4_pcie_prepare(pcie); + if (err < 0) + goto err_pm_put; + rcar_gen4_pcie_init_rc(pcie, num_lanes); + + err = rcar_gen4_add_pcie_port(pcie, pdev); + if (err < 0) + goto err_host_disable; + + return 0; + +err_host_disable: + rcar_gen4_pcie_unprepare(pcie); + +err_pm_put: + rcar_gen4_pcie_pm_runtime_disable(dev); + + return err; +} + +static int rcar_gen4_pcie_remove(struct platform_device *pdev) +{ + struct rcar_gen4_pcie *pcie = platform_get_drvdata(pdev); + + rcar_gen4_remove_pcie_port(pcie); + rcar_gen4_pcie_unprepare(pcie); + rcar_gen4_pcie_pm_runtime_disable(&pdev->dev); + + return 0; +} + +static const struct of_device_id rcar_gen4_pcie_of_match[] = { + { .compatible = "renesas,rcar-gen4-pcie", }, + {}, +}; + +static struct platform_driver rcar_gen4_pcie_driver = { + .driver = { + .name = "pcie-rcar-gen4", + .of_match_table = rcar_gen4_pcie_of_match, + }, + .probe = rcar_gen4_pcie_probe, + .remove = rcar_gen4_pcie_remove, +}; +builtin_platform_driver(rcar_gen4_pcie_driver); + +MODULE_DESCRIPTION("Renesas R-Car Gen4 PCIe host controller driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c new file mode 100644 index 000000000000..48c3fc0b5e67 --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c @@ -0,0 +1,198 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCIe host/endpoint controller driver for Renesas R-Car Gen4 Series SoCs + * Copyright (C) 2022 Renesas Electronics Corporation + */ + +#include +#include +#include +#include +#include +#include + +#include "pcie-rcar-gen4.h" +#include "pcie-designware.h" + +/* Link Capabilities - Maximum Link Width */ +#define PCI_EXP_LNKCAP_MLW_X1 BIT(4) +#define PCI_EXP_LNKCAP_MLW_X2 BIT(5) +#define PCI_EXP_LNKCAP_MLW_X4 BIT(6) + +/* ASPM L1 PM Substates */ +#define L1PSCAP(x) (0x01bc + (x)) + +/* Renesas-specific */ +#define PCIEMSR0 0x0000 +#define BIFUR_MOD_SET_ON (0x1 << 0) +#define DEVICE_TYPE_RC (0x4 << 2) + +#define PCIERSTCTRL1 0x0014 +#define APP_HOLD_PHY_RST BIT(16) +#define APP_LTSSM_ENABLE BIT(0) + +#define DWC_VERSION 0x520a + +#define to_rcar_gen4_pcie(x) dev_get_drvdata((x)->dev) + +u32 rcar_gen4_pcie_readl(struct rcar_gen4_pcie *pcie, u32 reg) +{ + return readl(pcie->base + reg); +} + +void rcar_gen4_pcie_writel(struct rcar_gen4_pcie *pcie, u32 reg, u32 val) +{ + writel(val, pcie->base + reg); +} + +static void rcar_gen4_pcie_ltssm_enable(struct rcar_gen4_pcie *pcie, + bool enable) +{ + u32 val; + + val = rcar_gen4_pcie_readl(pcie, PCIERSTCTRL1); + if (enable) { + val |= APP_LTSSM_ENABLE; + val &= ~APP_HOLD_PHY_RST; + } else { + val &= ~APP_LTSSM_ENABLE; + val |= APP_HOLD_PHY_RST; + } + rcar_gen4_pcie_writel(pcie, PCIERSTCTRL1, val); +} + +static int rcar_gen4_pcie_link_up(struct dw_pcie *pci) +{ + struct rcar_gen4_pcie *pcie = to_rcar_gen4_pcie(pci); + u32 val, mask; + + val = rcar_gen4_pcie_readl(pcie, PCIEINTSTS0); + mask = RDLH_LINK_UP | SMLH_LINK_UP; + + return (val & mask) == mask; +} + +static int rcar_gen4_pcie_start_link(struct dw_pcie *pci) +{ + struct rcar_gen4_pcie *pcie = to_rcar_gen4_pcie(pci); + + rcar_gen4_pcie_ltssm_enable(pcie, true); + + return 0; +} + +static void rcar_gen4_pcie_stop_link(struct dw_pcie *pci) +{ + struct rcar_gen4_pcie *pcie = to_rcar_gen4_pcie(pci); + + rcar_gen4_pcie_ltssm_enable(pcie, false); +} + +void rcar_gen4_pcie_set_max_link_width(struct dw_pcie *pci, int num_lanes) +{ + u32 val = dw_pcie_readl_dbi(pci, EXPCAP(PCI_EXP_LNKCAP)); + + val &= ~PCI_EXP_LNKCAP_MLW; + switch (num_lanes) { + case 1: + val |= PCI_EXP_LNKCAP_MLW_X1; + break; + case 2: + val |= PCI_EXP_LNKCAP_MLW_X2; + break; + case 4: + val |= PCI_EXP_LNKCAP_MLW_X4; + break; + default: + dev_info(pci->dev, "invalid num-lanes %d\n", num_lanes); + val |= PCI_EXP_LNKCAP_MLW_X1; + break; + } + dw_pcie_writel_dbi(pci, EXPCAP(PCI_EXP_LNKCAP), val); +} + +int rcar_gen4_pcie_prepare(struct rcar_gen4_pcie *pcie) +{ + struct dw_pcie *pci = pcie->pci; + int ret; + + ret = clk_prepare_enable(pcie->bus_clk); + if (ret) { + dev_err(pci->dev, "failed to enable bus clock: %d\n", ret); + return ret; + } + + ret = reset_control_deassert(pcie->rst); + if (ret) + goto err_clk_disable; + + return 0; + +err_clk_disable: + clk_disable_unprepare(pcie->bus_clk); + + return ret; +} + +void rcar_gen4_pcie_unprepare(struct rcar_gen4_pcie *pcie) +{ + reset_control_assert(pcie->rst); + clk_disable_unprepare(pcie->bus_clk); +} + +int rcar_gen4_pcie_pm_runtime_enable(struct device *dev) +{ + pm_runtime_enable(dev); + return pm_runtime_get_sync(dev); +} + +void rcar_gen4_pcie_pm_runtime_disable(struct device *dev) +{ + pm_runtime_put(dev); + pm_runtime_disable(dev); +} + +int rcar_gen4_pcie_devm_clk_and_reset_get(struct rcar_gen4_pcie *pcie, + struct device *dev) +{ + pcie->bus_clk = devm_clk_get(dev, "pcie_bus"); + if (IS_ERR(pcie->bus_clk)) { + dev_err(dev, "cannot get pcie bus clock\n"); + return PTR_ERR(pcie->bus_clk); + } + + pcie->rst = devm_reset_control_get(dev, NULL); + if (IS_ERR(pcie->rst)) { + dev_err(dev, "failed to get Cold-reset\n"); + return PTR_ERR(pcie->rst); + } + + return 0; +} + +static const struct dw_pcie_ops dw_pcie_ops = { + .start_link = rcar_gen4_pcie_start_link, + .stop_link = rcar_gen4_pcie_stop_link, + .link_up = rcar_gen4_pcie_link_up, +}; + +struct rcar_gen4_pcie *rcar_gen4_pcie_devm_alloc(struct device *dev) +{ + struct rcar_gen4_pcie *pcie; + struct dw_pcie *pci; + + pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); + if (!pcie) + return NULL; + + pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); + if (!pci) + return NULL; + + pci->dev = dev; + pci->ops = &dw_pcie_ops; + pci->version = DWC_VERSION; + pcie->pci = pci; + + return pcie; +} diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.h b/drivers/pci/controller/dwc/pcie-rcar-gen4.h new file mode 100644 index 000000000000..bd01d0ffcac9 --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * PCIe host/endpoint controller driver for Renesas R-Car Gen4 Series SoCs + * Copyright (C) 2022 Renesas Electronics Corporation + */ + +#ifndef _PCIE_RCAR_GEN4_H_ +#define _PCIE_RCAR_GEN4_H_ + +#include +#include +#include +#include + +#include "pcie-designware.h" + +/* PCI Express capability */ +#define EXPCAP(x) (0x0070 + (x)) +/* PCI Shadow offset */ +#define SHADOW_REG(x) (0x2000 + (x)) +/* BAR Mask registers */ +#define BAR0MASKF 0x0010 +#define BAR1MASKF 0x0014 +#define BAR2MASKF 0x0018 +#define BAR3MASKF 0x001c +#define BAR4MASKF 0x0020 +#define BAR5MASKF 0x0024 + +/* Renesas-specific */ +#define PCIEMSR0 0x0000 +#define BIFUR_MOD_SET_ON (0x1 << 0) +#define DEVICE_TYPE_EP (0x0 << 2) +#define DEVICE_TYPE_RC (0x4 << 2) + +#define PCIEINTSTS0 0x0084 +#define PCIEINTSTS0EN 0x0310 +#define MSI_CTRL_INT BIT(26) +#define SMLH_LINK_UP BIT(7) +#define RDLH_LINK_UP BIT(6) + +struct rcar_gen4_pcie { + struct dw_pcie *pci; + void __iomem *base; + struct clk *bus_clk; + struct reset_control *rst; +}; + +extern u32 rcar_gen4_pcie_readl(struct rcar_gen4_pcie *pcie, u32 reg); +extern void rcar_gen4_pcie_writel(struct rcar_gen4_pcie *pcie, u32 reg, u32 val); +extern void rcar_gen4_pcie_set_max_link_width(struct dw_pcie *pci, int num_lanes); +extern int rcar_gen4_pcie_prepare(struct rcar_gen4_pcie *pcie); +extern void rcar_gen4_pcie_unprepare(struct rcar_gen4_pcie *pcie); +extern int rcar_gen4_pcie_pm_runtime_enable(struct device *dev); +extern void rcar_gen4_pcie_pm_runtime_disable(struct device *dev); +extern int rcar_gen4_pcie_devm_clk_and_reset_get(struct rcar_gen4_pcie *pcie, + struct device *dev); +extern struct rcar_gen4_pcie *rcar_gen4_pcie_devm_alloc(struct device *dev); + +#endif /* _PCIE_RCAR_GEN4_H_ */ From patchwork Mon Jun 13 11:57:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 1642870 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4LMF4q2V1Cz9s2R for ; Tue, 14 Jun 2022 00:56:11 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1386348AbiFMO4I (ORCPT ); Mon, 13 Jun 2022 10:56:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46402 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1386354AbiFMOz0 (ORCPT ); Mon, 13 Jun 2022 10:55:26 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id E8B1BD31AB; Mon, 13 Jun 2022 04:57:59 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.91,297,1647270000"; d="scan'208";a="124235800" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 13 Jun 2022 20:57:22 +0900 Received: from localhost.localdomain (unknown [10.166.15.32]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 54574422104E; Mon, 13 Jun 2022 20:57:22 +0900 (JST) From: Yoshihiro Shimoda To: lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com, krzk+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com Cc: marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH 4/7] PCI: renesas: Add R-Car Gen4 PCIe Endpoint support Date: Mon, 13 Jun 2022 20:57:09 +0900 Message-Id: <20220613115712.2831386-5-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220613115712.2831386-1-yoshihiro.shimoda.uh@renesas.com> References: <20220613115712.2831386-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,KHOP_HELO_FCRDNS, SPF_HELO_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add R-Car Gen4 PCIe Endpoint support. This controller is based on Synopsys Designware PCIe. Signed-off-by: Yoshihiro Shimoda --- drivers/pci/controller/dwc/Kconfig | 9 + drivers/pci/controller/dwc/Makefile | 1 + .../pci/controller/dwc/pcie-rcar-gen4-ep.c | 253 ++++++++++++++++++ drivers/pci/controller/dwc/pcie-rcar-gen4.h | 1 + 4 files changed, 264 insertions(+) create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4-ep.c diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index 3ddccc9c38c5..503ead1a4358 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -393,4 +393,13 @@ config PCIE_RCAR_GEN4 Say Y here if you want PCIe host controller support on R-Car Gen4 SoCs. This uses the DesignWare core. +config PCIE_RCAR_GEN4_EP + bool "Renesas R-Car Gen4 PCIe Endpoint controller" + depends on ARCH_RENESAS || COMPILE_TEST + depends on PCI_ENDPOINT + select PCIE_DW_EP + help + Say Y here if you want PCIe endpoint controller support on R-Car Gen4 + SoCs. This uses the DesignWare core. + endmenu diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile index b3f285e685f9..3d40346efd27 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o obj-$(CONFIG_PCIE_VISCONTI_HOST) += pcie-visconti.o obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4.o pcie-rcar-gen4-host.o +obj-$(CONFIG_PCIE_RCAR_GEN4_EP) += pcie-rcar-gen4.o pcie-rcar-gen4-ep.o # The following drivers are for devices that use the generic ACPI # pci_root.c driver but don't support standard ECAM config access. diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4-ep.c b/drivers/pci/controller/dwc/pcie-rcar-gen4-ep.c new file mode 100644 index 000000000000..622e32c7a410 --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4-ep.c @@ -0,0 +1,253 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCIe Endpoint driver for Renesas R-Car Gen4 Series SoCs + * Copyright (C) 2022 Renesas Electronics Corporation + */ + +#include +#include +#include +#include +#include + +#include "pcie-rcar-gen4.h" +#include "pcie-designware.h" + +/* Configuration */ +#define PCICONF3 0x000c +#define MULTI_FUNC BIT(23) + +struct rcar_gen4_pcie_ep { + struct rcar_gen4_pcie *pcie; + struct dw_pcie *pci; + u32 num_lanes; +}; + +static void rcar_gen4_pcie_ep_init(struct dw_pcie_ep *ep) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + enum pci_barno bar; + + for (bar = BAR_0; bar <= BAR_5; bar++) + dw_pcie_ep_reset_bar(pci, bar); +} + +static int rcar_gen4_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, + enum pci_epc_irq_type type, + u16 interrupt_num) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + + switch (type) { + case PCI_EPC_IRQ_LEGACY: + return dw_pcie_ep_raise_legacy_irq(ep, func_no); + case PCI_EPC_IRQ_MSI: + return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); + case PCI_EPC_IRQ_MSIX: + return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num); + default: + dev_err(pci->dev, "UNKNOWN IRQ type\n"); + return -EINVAL; + } + + return 0; +} + +static const struct pci_epc_features rcar_gen4_pcie_epc_features = { + .linkup_notifier = false, + .msi_capable = true, + .msix_capable = false, + .align = SZ_1M, +}; + +static const struct pci_epc_features* +rcar_gen4_pcie_ep_get_features(struct dw_pcie_ep *ep) +{ + return &rcar_gen4_pcie_epc_features; +} + +static const struct dw_pcie_ep_ops pcie_ep_ops = { + .ep_init = rcar_gen4_pcie_ep_init, + .raise_irq = rcar_gen4_pcie_ep_raise_irq, + .get_features = rcar_gen4_pcie_ep_get_features, +}; + +static int rcar_gen4_add_pcie_ep(struct rcar_gen4_pcie_ep *pcie_ep, + struct platform_device *pdev) +{ + struct rcar_gen4_pcie *pcie = pcie_ep->pcie; + struct dw_pcie *pci = pcie->pci; + struct dw_pcie_ep *ep; + struct resource *res; + int ret; + + ep = &pci->ep; + ep->ops = &pcie_ep_ops; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); + if (!res) + return -EINVAL; + + ep->addr_size = resource_size(res); + + ret = dw_pcie_ep_init(ep); + if (ret) { + dev_err(&pdev->dev, "failed to initialize endpoint\n"); + return ret; + } + + pci->ops->start_link(pci); + + return 0; +} + +static void rcar_gen4_remove_pcie_ep(struct rcar_gen4_pcie_ep *pcie_ep) +{ + dw_pcie_ep_exit(&pcie_ep->pcie->pci->ep); +} + +static void rcar_gen4_pcie_init_ep(struct rcar_gen4_pcie_ep *pcie_ep) +{ + struct rcar_gen4_pcie *pcie = pcie_ep->pcie; + struct dw_pcie *pci = pcie->pci; + int val; + + /* Device type selection - Endpoint */ + val = rcar_gen4_pcie_readl(pcie, PCIEMSR0); + val |= DEVICE_TYPE_EP; + if (pcie_ep->num_lanes < 4) + val |= BIFUR_MOD_SET_ON; + rcar_gen4_pcie_writel(pcie, PCIEMSR0, val); + + dw_pcie_dbi_ro_wr_en(pci); + + /* Single function */ + val = dw_pcie_readl_dbi(pci, PCICONF3); + val &= ~MULTI_FUNC; + dw_pcie_writel_dbi(pci, PCICONF3, val); + + /* Disable unused BARs */ + dw_pcie_writel_dbi(pci, SHADOW_REG(BAR2MASKF), 0x0); + dw_pcie_writel_dbi(pci, SHADOW_REG(BAR3MASKF), 0x0); + + /* Set Max Link Width */ + rcar_gen4_pcie_set_max_link_width(pci, pcie_ep->num_lanes); + + dw_pcie_dbi_ro_wr_dis(pci); +} + +static int rcar_gen4_pcie_ep_get_resources(struct rcar_gen4_pcie_ep *pcie_ep, + struct platform_device *pdev) +{ + struct rcar_gen4_pcie *pcie = pcie_ep->pcie; + struct dw_pcie *pci = pcie->pci; + struct device *dev = pci->dev; + struct device_node *np = dev->of_node; + struct resource *res; + int err; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); + pci->dbi_base = devm_pci_remap_cfg_resource(dev, res); + if (IS_ERR(pci->dbi_base)) + return PTR_ERR(pci->dbi_base); + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu"); + pci->atu_base = devm_ioremap_resource(dev, res); + if (IS_ERR(pci->atu_base)) + return PTR_ERR(pci->atu_base); + + /* Renesas-specific registers */ + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "appl"); + pcie->base = devm_ioremap_resource(dev, res); + if (IS_ERR(pcie->base)) + return PTR_ERR(pcie->base); + + err = of_property_read_u32(np, "num-lanes", &pcie_ep->num_lanes); + if (err < 0) { + dev_err(dev, "num-lanes not found %d\n", err); + return err; + } + + return rcar_gen4_pcie_devm_clk_and_reset_get(pcie, dev); +} + +static int rcar_gen4_pcie_ep_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct rcar_gen4_pcie_ep *pcie_ep; + struct rcar_gen4_pcie *pcie; + int err; + + pcie_ep = devm_kzalloc(dev, sizeof(*pcie_ep), GFP_KERNEL); + if (!pcie_ep) + return -ENOMEM; + + pcie = rcar_gen4_pcie_devm_alloc(dev); + if (!pcie) + return -ENOMEM; + pcie_ep->pcie = pcie; + + err = rcar_gen4_pcie_pm_runtime_enable(dev); + if (err < 0) { + dev_err(dev, "pm_runtime_get_sync failed\n"); + return err; + } + + err = rcar_gen4_pcie_ep_get_resources(pcie_ep, pdev); + if (err < 0) { + dev_err(dev, "failed to request resource: %d\n", err); + goto err_pm_put; + } + + pcie->priv = pcie_ep; + platform_set_drvdata(pdev, pcie); + + err = rcar_gen4_pcie_prepare(pcie); + if (err < 0) + goto err_pm_put; + rcar_gen4_pcie_init_ep(pcie_ep); + + err = rcar_gen4_add_pcie_ep(pcie_ep, pdev); + if (err < 0) + goto err_ep_disable; + + return 0; + +err_ep_disable: + rcar_gen4_pcie_unprepare(pcie); + +err_pm_put: + rcar_gen4_pcie_pm_runtime_disable(dev); + + return err; +} + +static int rcar_gen4_pcie_ep_remove(struct platform_device *pdev) +{ + struct rcar_gen4_pcie *pcie = platform_get_drvdata(pdev); + struct rcar_gen4_pcie_ep *pcie_ep = pcie->priv; + + rcar_gen4_remove_pcie_ep(pcie_ep); + rcar_gen4_pcie_unprepare(pcie_ep->pcie); + rcar_gen4_pcie_pm_runtime_disable(&pdev->dev); + + return 0; +} + +static const struct of_device_id rcar_gen4_pcie_of_match[] = { + { .compatible = "renesas,rcar-gen4-pcie-ep", }, + {}, +}; + +static struct platform_driver rcar_gen4_pcie_ep_driver = { + .driver = { + .name = "pcie-rcar-gen4-ep", + .of_match_table = rcar_gen4_pcie_of_match, + }, + .probe = rcar_gen4_pcie_ep_probe, + .remove = rcar_gen4_pcie_ep_remove, +}; +builtin_platform_driver(rcar_gen4_pcie_ep_driver); + +MODULE_DESCRIPTION("Renesas R-Car Gen4 PCIe endpoint controller driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.h b/drivers/pci/controller/dwc/pcie-rcar-gen4.h index bd01d0ffcac9..b6e285d8ebc0 100644 --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.h +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.h @@ -43,6 +43,7 @@ struct rcar_gen4_pcie { void __iomem *base; struct clk *bus_clk; struct reset_control *rst; + void *priv; }; extern u32 rcar_gen4_pcie_readl(struct rcar_gen4_pcie *pcie, u32 reg); From patchwork Mon Jun 13 11:57:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 1642872 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4LMF503Gh7z9s2R for ; Tue, 14 Jun 2022 00:56:20 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353628AbiFMO4N (ORCPT ); Mon, 13 Jun 2022 10:56:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51828 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1358277AbiFMOzr (ORCPT ); Mon, 13 Jun 2022 10:55:47 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 72EC7D31B4; Mon, 13 Jun 2022 04:58:01 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.91,297,1647270000"; d="scan'208";a="122758910" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 13 Jun 2022 20:57:22 +0900 Received: from localhost.localdomain (unknown [10.166.15.32]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 7088D4221054; Mon, 13 Jun 2022 20:57:22 +0900 (JST) From: Yoshihiro Shimoda To: lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com, krzk+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com Cc: marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH 5/7] MAINTAINERS: Update PCI DRIVER FOR RENESAS R-CAR for R-Car Gen4 Date: Mon, 13 Jun 2022 20:57:10 +0900 Message-Id: <20220613115712.2831386-6-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220613115712.2831386-1-yoshihiro.shimoda.uh@renesas.com> References: <20220613115712.2831386-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,KHOP_HELO_FCRDNS, SPF_HELO_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Update this entry for R-Car Gen4's source code. Signed-off-by: Yoshihiro Shimoda --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index b414f8245513..59bf5e2f940a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -15292,6 +15292,7 @@ L: linux-renesas-soc@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/pci/*rcar* F: drivers/pci/controller/*rcar* +F: drivers/pci/controller/dwc/*rcar* PCI DRIVER FOR SAMSUNG EXYNOS M: Jingoo Han From patchwork Mon Jun 13 11:57:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 1642875 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4LMF5W73wBz9s75 for ; Tue, 14 Jun 2022 00:56:47 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1386404AbiFMO4q (ORCPT ); Mon, 13 Jun 2022 10:56:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53952 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1385831AbiFMO4D (ORCPT ); Mon, 13 Jun 2022 10:56:03 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 30727D4111; Mon, 13 Jun 2022 04:58:04 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.91,297,1647270000"; d="scan'208";a="124235803" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 13 Jun 2022 20:57:22 +0900 Received: from localhost.localdomain (unknown [10.166.15.32]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 97A6E422104E; Mon, 13 Jun 2022 20:57:22 +0900 (JST) From: Yoshihiro Shimoda To: lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com, krzk+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com Cc: marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH 6/7] arm64: dts: renesas: r8a779f0: Add PCIe Host and Endpoint nodes Date: Mon, 13 Jun 2022 20:57:11 +0900 Message-Id: <20220613115712.2831386-7-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220613115712.2831386-1-yoshihiro.shimoda.uh@renesas.com> References: <20220613115712.2831386-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,KHOP_HELO_FCRDNS, SPF_HELO_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add PCIe Host and Endpoint nodes for R-Car S4-8 (R8A779F0). Signed-off-by: Yoshihiro Shimoda --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 133 ++++++++++++++++++++++ 1 file changed, 133 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index ad8c77edb126..97e0cbefb758 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -40,6 +40,13 @@ extalr_clk: extalr { clock-frequency = <0>; }; + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + pmu_a55 { compatible = "arm,cortex-a55-pmu"; interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; @@ -259,6 +266,132 @@ i2c5: i2c@e66e0000 { status = "disabled"; }; + pciec0: pcie@e65d0000 { + compatible = "renesas,r8a779f0-pcie", + "renesas,rcar-gen4-pcie", + "snps,dw-pcie"; + reg = <0 0xe65d0000 0 0x3000>, <0 0xe65d3000 0 0x2000>, + <0 0xe65d6200 0 0x0e00>, <0 0xfe000000 0 0x10000>; + reg-names = "dbi", "atu", "app", "config"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x81000000 0 0x00000000 0 0xfe000000 0 0x00010000 + 0x82000000 0 0x30000000 0 0x30000000 0 0x10000000>; + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = , + , + , + , + , + ; + interrupt-names = "msi", "err", "fatal", "nonfatal", "lp", "vndmsg"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 624>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 624>; + num-lanes = <2>; + snps,enable-cdm-check; + max-link-speed = <2>; + status = "disabled"; + }; + + pciec1: pcie@e65d8000 { + compatible = "renesas,r8a779f0-pcie", + "renesas,rcar-gen4-pcie", + "snps,dw-pcie"; + reg = <0 0xe65d8000 0 0x3000>, <0 0xe65db000 0 0x2000>, + <0 0xe65de200 0 0x0e00>, <0 0xee900000 0 0x10000>; + reg-names = "dbi", "atu", "app", "config"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x81000000 0 0x00000000 0 0xee900000 0 0x00010000 + 0x82000000 0 0xc0000000 0 0xc0000000 0 0x10000000>; + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = , + , + , + , + , + ; + interrupt-names = "msi", "err", "fatal", "nonfatal", "lp", "vndmsg"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 625>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 625>; + num-lanes = <2>; + snps,enable-cdm-check; + max-link-speed = <2>; + status = "disabled"; + }; + + pciec0_ep: pcie-ep@e65d0000 { + compatible = "renesas,r8a779f0-pcie-ep", + "renesas,rcar-gen4-pcie-ep", + "snps,dw-pcie-ep"; + reg = <0 0xe65d0000 0 0x3000>, <0 0xe65d3000 0 0x2000>, + <0 0xe65d6200 0 0x0e00>, <0 0xfe000000 0 0x400000>; + reg-names = "dbi", "atu", "appl", "addr_space"; + interrupts = , + , + , + , + , + ; + interrupt-names = "msi", "err", "fatal", "nonfatal", + "lp", "vndmsg"; + clocks = <&cpg CPG_MOD 624>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 624>; + num-lanes = <2>; + max-link-speed = <2>; + num-ib-windows = <16>; + num-ob-windows = <16>; + status = "disabled"; + }; + + pciec1_ep: pcie-ep@e65d8000 { + compatible = "renesas,r8a779f0-pcie-ep", + "renesas,rcar-gen4-pcie-ep", + "snps,dw-pcie-ep"; + reg = <0 0xe65d8000 0 0x3000>, <0 0xe65db000 0 0x2000>, + <0 0xe65de200 0 0x0e00>, <0 0xee900000 0 0x400000>; + reg-names = "dbi", "atu", "appl", "addr_space"; + interrupts = , + , + , + , + , + ; + interrupt-names = "msi", "err", "fatal", "nonfatal", + "lp", "vndmsg"; + clocks = <&cpg CPG_MOD 625>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 625>; + num-lanes = <2>; + max-link-speed = <2>; + num-ib-windows = <16>; + num-ob-windows = <16>; + status = "disabled"; + }; + scif3: serial@e6c50000 { compatible = "renesas,scif-r8a779f0", "renesas,rcar-gen4-scif", "renesas,scif"; From patchwork Mon Jun 13 11:57:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 1642876 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4LMF5Z0BVTz9s2R for ; Tue, 14 Jun 2022 00:56:50 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1386025AbiFMO4s (ORCPT ); Mon, 13 Jun 2022 10:56:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53126 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351910AbiFMO4F (ORCPT ); Mon, 13 Jun 2022 10:56:05 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 6DA52D4117; Mon, 13 Jun 2022 04:58:04 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.91,297,1647270000"; d="scan'208";a="122758913" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 13 Jun 2022 20:57:22 +0900 Received: from localhost.localdomain (unknown [10.166.15.32]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id B62DD422104E; Mon, 13 Jun 2022 20:57:22 +0900 (JST) From: Yoshihiro Shimoda To: lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com, krzk+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com Cc: marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH 7/7] arm64: dts: renesas: r8a779f0: spider: Enable PCIe Host ch0 Date: Mon, 13 Jun 2022 20:57:12 +0900 Message-Id: <20220613115712.2831386-8-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220613115712.2831386-1-yoshihiro.shimoda.uh@renesas.com> References: <20220613115712.2831386-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,KHOP_HELO_FCRDNS, SPF_HELO_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Enable PCIe Host controller channel 0 on R-Car S4-8 Spider board. Signed-off-by: Yoshihiro Shimoda --- .../boot/dts/renesas/r8a779f0-spider-cpu.dtsi | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi index 41aa8591b3b1..d5fe22355e20 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi @@ -5,6 +5,7 @@ * Copyright (C) 2021 Renesas Electronics Corp. */ +#include #include "r8a779f0.dtsi" / { @@ -31,6 +32,28 @@ &extalr_clk { clock-frequency = <32768>; }; +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + gpio_exp_20: gpio@20 { + compatible = "ti,tca9554"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + + pcie-perst-hog { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "PCIE_PERSTn"; + }; + }; +}; + &i2c4 { pinctrl-0 = <&i2c4_pins>; pinctrl-names = "default"; @@ -46,15 +69,35 @@ eeprom@50 { }; }; +&pcie_bus_clk { + clock-frequency = <100000000>; +}; + +&pciec0 { + pinctrl-0 = <&pcie0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + &pfc { pinctrl-0 = <&scif_clk_pins>; pinctrl-names = "default"; + i2c0_pins: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + i2c4_pins: i2c4 { groups = "i2c4"; function = "i2c4"; }; + pcie0_pins: pcie0 { + groups = "pcie0_clkreq_n"; + function = "pcie"; + }; + scif3_pins: scif3 { groups = "scif3_data", "scif3_ctrl"; function = "scif3";