From patchwork Mon Jun 6 22:05:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: will schmidt X-Patchwork-Id: 1639632 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=BvDqelUc; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LH6y960Q7z9sFk for ; Tue, 7 Jun 2022 08:06:08 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 826E338344E0 for ; Mon, 6 Jun 2022 22:06:04 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 826E338344E0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1654553164; bh=ITKO6y3RoRffnnJKXIXu7N/LCVF5uOITcOFr7GpmCjg=; h=Subject:To:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=BvDqelUchwEG6u96D9HM4dtTAAcHAvffT3U5+ShRjZOnqlt0JGmV6CsfAARQGh8Gu pzA1b8ymd4BbtEyF5pDKb/Qc/aU5iO4QEnapZOaK4uxDnFx9orYfxNEhJ3fKvucrK0 t7tDM1VNWh/7r8dRC9/7IXimofQX8uYeP/E5MnRQ= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id F04ED384D15E for ; Mon, 6 Jun 2022 22:05:43 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org F04ED384D15E Received: from pps.filterd (m0098404.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 256LFQHo007939; Mon, 6 Jun 2022 22:05:42 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3ghsb9gn4j-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 06 Jun 2022 22:05:41 +0000 Received: from m0098404.ppops.net (m0098404.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 256LkqKF003630; Mon, 6 Jun 2022 22:05:41 GMT Received: from ppma02wdc.us.ibm.com (aa.5b.37a9.ip4.static.sl-reverse.com [169.55.91.170]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3ghsb9gn4a-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 06 Jun 2022 22:05:41 +0000 Received: from pps.filterd (ppma02wdc.us.ibm.com [127.0.0.1]) by ppma02wdc.us.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 256LoL4Y001682; Mon, 6 Jun 2022 22:05:40 GMT Received: from b01cxnp22036.gho.pok.ibm.com (b01cxnp22036.gho.pok.ibm.com [9.57.198.26]) by ppma02wdc.us.ibm.com with ESMTP id 3gfy19g7pc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 06 Jun 2022 22:05:40 +0000 Received: from b01ledav006.gho.pok.ibm.com (b01ledav006.gho.pok.ibm.com [9.57.199.111]) by b01cxnp22036.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 256M5dUY12386632 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 6 Jun 2022 22:05:39 GMT Received: from b01ledav006.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9889AAC060; Mon, 6 Jun 2022 22:05:39 +0000 (GMT) Received: from b01ledav006.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 361A7AC059; Mon, 6 Jun 2022 22:05:39 +0000 (GMT) Received: from lexx (unknown [9.160.81.62]) by b01ledav006.gho.pok.ibm.com (Postfix) with ESMTP; Mon, 6 Jun 2022 22:05:39 +0000 (GMT) Message-ID: <9369d8551a904e8e131796ebd0227d0109856fc1.camel@vnet.ibm.com> Subject: [PATCH,RS6000 1/5] Clean-up MASK_ and RS6000_BTM_ definitions. To: gcc-patches@gcc.gnu.org Date: Mon, 06 Jun 2022 17:05:38 -0500 In-Reply-To: <21f1b472875d5c75e151e647c5182a74e426559f.camel@vnet.ibm.com> References: <21f1b472875d5c75e151e647c5182a74e426559f.camel@vnet.ibm.com> X-Mailer: Evolution 3.28.5 (3.28.5-18.el8) Mime-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: ZfJBvcljGraI-dmRCb-ATQjYHfXDtp7L X-Proofpoint-ORIG-GUID: BgCnDTRTNcrlOUGwXtN7Cb5i1SugWqbD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-06_07,2022-06-03_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 mlxlogscore=813 malwarescore=0 adultscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2204290000 definitions=main-2206060087 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: will schmidt via Gcc-patches From: will schmidt Reply-To: will schmidt Cc: David Edelsohn , Segher Boessenkool Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" [PATCH,RS6000 1/5] Clean-up MASK_ and RS6000_BTM_ definitions. Hi, This patch removes the defines that are no longer used, and updates the comment for the set of MASK_ defines. This patch removes the defines for MASK_REGNAMES, MASK_PROTOTYPE, RS6000_BTM_ALWAYS, RS6000_BTM_COMMON. gcc/ * config/rs6000/rs6000.c (RS6000_BTM_COMMON, RS6000_BTM_ALWAYS, MASK_REGNAMES, OPTION_MASK_REGNAMES, MASK_PROTOTYPE, OPTION_MASK_PROTOTYPE, MASK_UPDATE, OPTION_MASK_UPDATE): Remove. diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 3b8941a86584..2ff17a16e43c 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -503,12 +503,13 @@ extern int rs6000_vector_align[]; answers if the arguments are not in the normal range. */ #define TARGET_MINMAX (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \ && (TARGET_P9_MINMAX || !flag_trapping_math)) /* In switching from using target_flags to using rs6000_isa_flags, the options - machinery creates OPTION_MASK_ instead of MASK_. For now map - OPTION_MASK_ back into MASK_. */ + machinery creates OPTION_MASK_ instead of MASK_. The MASK_ + options that have not yet been replaced by their OPTION_MASK_ + equivalents are defined here. */ #define MASK_ALTIVEC OPTION_MASK_ALTIVEC #define MASK_CMPB OPTION_MASK_CMPB #define MASK_CRYPTO OPTION_MASK_CRYPTO #define MASK_DFP OPTION_MASK_DFP #define MASK_DIRECT_MOVE OPTION_MASK_DIRECT_MOVE @@ -534,11 +535,10 @@ extern int rs6000_vector_align[]; #define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT #define MASK_PPC_GPOPT OPTION_MASK_PPC_GPOPT #define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION #define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT #define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN -#define MASK_UPDATE OPTION_MASK_UPDATE #define MASK_VSX OPTION_MASK_VSX #define MASK_POWER10 OPTION_MASK_POWER10 #define MASK_P10_FUSION OPTION_MASK_P10_FUSION #ifndef IN_LIBGCC2 @@ -551,18 +551,10 @@ extern int rs6000_vector_align[]; #ifdef TARGET_LITTLE_ENDIAN #define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN #endif -#ifdef TARGET_REGNAMES -#define MASK_REGNAMES OPTION_MASK_REGNAMES -#endif - -#ifdef TARGET_PROTOTYPE -#define MASK_PROTOTYPE OPTION_MASK_PROTOTYPE -#endif - #ifdef TARGET_MODULO #define RS6000_BTM_MODULO OPTION_MASK_MODULO #endif @@ -2250,11 +2242,10 @@ extern int frame_pointer_needed; /* Builtin targets. For now, we reuse the masks for those options that are in target flags, and pick a random bit for ldbl128, which isn't in target_flags. */ -#define RS6000_BTM_ALWAYS 0 /* Always enabled. */ #define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */ #define RS6000_BTM_CMPB MASK_CMPB /* ISA 2.05: compare bytes. */ #define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */ #define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */ #define RS6000_BTM_P9_VECTOR MASK_P9_VECTOR /* ISA 3.0 vector. */ @@ -2275,32 +2266,10 @@ extern int frame_pointer_needed; #define RS6000_BTM_FLOAT128 MASK_FLOAT128_KEYWORD /* IEEE 128-bit float. */ #define RS6000_BTM_FLOAT128_HW MASK_FLOAT128_HW /* IEEE 128-bit float h/w. */ #define RS6000_BTM_MMA MASK_MMA /* ISA 3.1 MMA. */ #define RS6000_BTM_P10 MASK_POWER10 -#define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \ - | RS6000_BTM_VSX \ - | RS6000_BTM_P8_VECTOR \ - | RS6000_BTM_P9_VECTOR \ - | RS6000_BTM_P9_MISC \ - | RS6000_BTM_MODULO \ - | RS6000_BTM_CRYPTO \ - | RS6000_BTM_FRE \ - | RS6000_BTM_FRES \ - | RS6000_BTM_FRSQRTE \ - | RS6000_BTM_FRSQRTES \ - | RS6000_BTM_HTM \ - | RS6000_BTM_POPCNTD \ - | RS6000_BTM_CELL \ - | RS6000_BTM_DFP \ - | RS6000_BTM_HARD_FLOAT \ - | RS6000_BTM_LDBL128 \ - | RS6000_BTM_POWERPC64 \ - | RS6000_BTM_FLOAT128 \ - | RS6000_BTM_FLOAT128_HW \ - | RS6000_BTM_MMA \ - | RS6000_BTM_P10) enum rs6000_builtin_type_index { RS6000_BTI_NOT_OPAQUE, RS6000_BTI_opaque_V4SI, From patchwork Mon Jun 6 22:05:47 2022 Content-Type: text/plain; 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Mon, 06 Jun 2022 22:05:48 +0000 Received: from b01ledav003.gho.pok.ibm.com (b01ledav003.gho.pok.ibm.com [9.57.199.108]) by b01cxnp22035.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 256M5mjO38732098 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 6 Jun 2022 22:05:48 GMT Received: from b01ledav003.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id F3053B205F; Mon, 6 Jun 2022 22:05:47 +0000 (GMT) Received: from b01ledav003.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8B057B2065; Mon, 6 Jun 2022 22:05:47 +0000 (GMT) Received: from lexx (unknown [9.160.81.62]) by b01ledav003.gho.pok.ibm.com (Postfix) with ESMTP; Mon, 6 Jun 2022 22:05:47 +0000 (GMT) Message-ID: <82211644fb1f61894e5b99a7c5fdb8e73539ddc0.camel@vnet.ibm.com> Subject: [PATCH,RS6000 2/5] Rework the RS6000_BTM defines. To: gcc-patches@gcc.gnu.org Date: Mon, 06 Jun 2022 17:05:47 -0500 In-Reply-To: <21f1b472875d5c75e151e647c5182a74e426559f.camel@vnet.ibm.com> References: <21f1b472875d5c75e151e647c5182a74e426559f.camel@vnet.ibm.com> X-Mailer: Evolution 3.28.5 (3.28.5-18.el8) Mime-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: EXVp8D3qCYG2ppYuv2zByGXzpBrbA5-1 X-Proofpoint-ORIG-GUID: 9xMDEctfwSGDdjBniC7ZazPvpORKFACT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-06_07,2022-06-03_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 mlxscore=0 suspectscore=0 phishscore=0 clxscore=1015 adultscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 bulkscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2204290000 definitions=main-2206060087 X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: will schmidt via Gcc-patches From: will schmidt Reply-To: will schmidt Cc: David Edelsohn , Segher Boessenkool Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" [PATCH,RS6000 2/5) Rework the RS6000_BTM defines. The RS6000_BTM_ definitions are mostly unused after the rs6000 builtin code was reworked. The remaining references can be replaced with the OPTION_MASK_ and MASK_ equivalents. This patch remvoes the defines: RS6000_BTM_FRES, RS6000_BTM_FRSQRTE, RS6000_BTM_FRSQRTES, RS6000_BTM_POPCNTD, RS6000_BTM_CELL, RS6000_BTM_DFP, RS6000_BTM_HARD_FLOAT, RS6000_BTM_LDBL128, RS6000_BTM_64BIT, RS6000_BTM_POWERPC64, RS6000_BTM_FLOAT128, RS6000_BTM_FLOAT128_HW RS6000_BTM_MMA, RS6000_BTM_P10. I note that the BTM -> OPTION_MASK mappings are not always 1-to-1. in particular the BTM_FRES and BTM_FRSQRTE values were both mapped to OPTION_MASK_PPC_GFXOPT, while the BTM_FRE and BTM_FRSQRTES both mapped to OPTION_MASK_POPCNTB. In total I spent quite a bit of time double-checking these since it looked like copy/paste errors. I split some of these changes out into a subsequent patch to limit the amount of potential confusion in any particular patch. gcc/ * config/rs6000/rs6000-c.cc: Update comments. * config/rs6000/rs6000.cc (RS6000_BTM_FRES, RS6000_BTM_FRSQRTE, RS6000_BTM_FRSQRTES, RS6000_BTM_POPCNTD, RS6000_BTM_CELL, RS6000_BTM_64BIT, RS6000_BTM_POWERPC64, RS6000_BTM_DFP, RS6000_BTM_HARD_FLOAT,RS6000_BTM_LDBL128, RS6000_BTM_FLOAT128, RS6000_BTM_FLOAT128_HW, RS6000_BTM_MMA, RS6000_BTM_P10): Replace with OPTION_MASK_PPC_GFXOPT, OPTION_MASK_PPC_GFXOPT, OPTION_MASK_POPCNTB, OPTION_MASK_POPCNTD, OPTION_MASK_FPRND, MASK_64BIT, MASK_POWERPC64, OPTION_MASK_DFP, OPTION_MASK_SOFT_FLOAT, OPTION_MASK_MULTIPLE, OPTION_MASK_FLOAT128_KEYWORD, OPTION_MASK_FLOAT128_HW, OPTION_MASK_MMA, OPTION_MASK_POWER10. * config/rs6000/rs6000.h (RS6000_BTM_FRES, RS6000_BTM_FRSQRTE, RS6000_BTM_FRSQRTES, RS6000_BTM_POPCNTD, RS6000_BTM_CELL, RS6000_BTM_DFP, RS6000_BTM_HARD_FLOAT, RS6000_BTM_LDBL128, RS6000_BTM_64BIT, RS6000_BTM_POWERPC64, RS6000_BTM_FLOAT128, RS6000_BTM_FLOAT128_HW, RS6000_BTM_MMA, RS6000_BTM_P10): Delete. diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc index 9c8cbd7a66e4..4c99afc761ae 100644 --- a/gcc/config/rs6000/rs6000-c.cc +++ b/gcc/config/rs6000/rs6000-c.cc @@ -594,13 +594,13 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags, via the target attribute/pragma. */ if ((flags & OPTION_MASK_FLOAT128_HW) != 0) rs6000_define_or_undefine_macro (define_p, "__FLOAT128_HARDWARE__"); /* options from the builtin masks. */ - /* Note that RS6000_BTM_CELL is enabled only if (rs6000_cpu == - PROCESSOR_CELL) (e.g. -mcpu=cell). */ - if ((bu_mask & RS6000_BTM_CELL) != 0) + /* Note that OPTION_MASK_FPRND is enabled only if + (rs6000_cpu == PROCESSOR_CELL) (e.g. -mcpu=cell). */ + if ((bu_mask & OPTION_MASK_FPRND) != 0) rs6000_define_or_undefine_macro (define_p, "__PPU__"); /* Tell the user if we support the MMA instructions. */ if ((flags & OPTION_MASK_MMA) != 0) rs6000_define_or_undefine_macro (define_p, "__MMA__"); diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index d4defc855d02..253110910bfa 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -3381,32 +3381,32 @@ rs6000_builtin_mask_calculate (void) { return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0) | ((TARGET_CMPB) ? RS6000_BTM_CMPB : 0) | ((TARGET_VSX) ? RS6000_BTM_VSX : 0) | ((TARGET_FRE) ? RS6000_BTM_FRE : 0) - | ((TARGET_FRES) ? RS6000_BTM_FRES : 0) - | ((TARGET_FRSQRTE) ? RS6000_BTM_FRSQRTE : 0) - | ((TARGET_FRSQRTES) ? RS6000_BTM_FRSQRTES : 0) - | ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0) - | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0) + | ((TARGET_FRES) ? OPTION_MASK_PPC_GFXOPT : 0) + | ((TARGET_FRSQRTE) ? OPTION_MASK_PPC_GFXOPT : 0) + | ((TARGET_FRSQRTES) ? OPTION_MASK_POPCNTB : 0) + | ((TARGET_POPCNTD) ? OPTION_MASK_POPCNTD : 0) + | ((rs6000_cpu == PROCESSOR_CELL) ? OPTION_MASK_FPRND : 0) | ((TARGET_P8_VECTOR) ? RS6000_BTM_P8_VECTOR : 0) | ((TARGET_P9_VECTOR) ? RS6000_BTM_P9_VECTOR : 0) | ((TARGET_P9_MISC) ? RS6000_BTM_P9_MISC : 0) | ((TARGET_MODULO) ? RS6000_BTM_MODULO : 0) - | ((TARGET_64BIT) ? RS6000_BTM_64BIT : 0) - | ((TARGET_POWERPC64) ? RS6000_BTM_POWERPC64 : 0) + | ((TARGET_64BIT) ? MASK_64BIT : 0) + | ((TARGET_POWERPC64) ? MASK_POWERPC64 : 0) | ((TARGET_CRYPTO) ? RS6000_BTM_CRYPTO : 0) | ((TARGET_HTM) ? RS6000_BTM_HTM : 0) - | ((TARGET_DFP) ? RS6000_BTM_DFP : 0) - | ((TARGET_HARD_FLOAT) ? RS6000_BTM_HARD_FLOAT : 0) + | ((TARGET_DFP) ? OPTION_MASK_DFP : 0) + | ((TARGET_HARD_FLOAT) ? OPTION_MASK_SOFT_FLOAT : 0) | ((TARGET_LONG_DOUBLE_128 && TARGET_HARD_FLOAT - && !TARGET_IEEEQUAD) ? RS6000_BTM_LDBL128 : 0) - | ((TARGET_FLOAT128_TYPE) ? RS6000_BTM_FLOAT128 : 0) - | ((TARGET_FLOAT128_HW) ? RS6000_BTM_FLOAT128_HW : 0) - | ((TARGET_MMA) ? RS6000_BTM_MMA : 0) - | ((TARGET_POWER10) ? RS6000_BTM_P10 : 0)); + && !TARGET_IEEEQUAD) ? OPTION_MASK_MULTIPLE : 0) + | ((TARGET_FLOAT128_TYPE) ? OPTION_MASK_FLOAT128_KEYWORD : 0) + | ((TARGET_FLOAT128_HW) ? OPTION_MASK_FLOAT128_HW : 0) + | ((TARGET_MMA) ? OPTION_MASK_MMA : 0) + | ((TARGET_POWER10) ? OPTION_MASK_POWER10 : 0)); } /* Implement TARGET_MD_ASM_ADJUST. All asm statements are considered to clobber the XER[CA] bit because clobbering that bit without telling the compiler worked just fine with versions of GCC before GCC 5, and @@ -24047,28 +24047,28 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] = static struct rs6000_opt_mask const rs6000_builtin_mask_names[] = { { "altivec", RS6000_BTM_ALTIVEC, false, false }, { "vsx", RS6000_BTM_VSX, false, false }, { "fre", RS6000_BTM_FRE, false, false }, - { "fres", RS6000_BTM_FRES, false, false }, - { "frsqrte", RS6000_BTM_FRSQRTE, false, false }, - { "frsqrtes", RS6000_BTM_FRSQRTES, false, false }, - { "popcntd", RS6000_BTM_POPCNTD, false, false }, - { "cell", RS6000_BTM_CELL, false, false }, + { "fres", OPTION_MASK_PPC_GFXOPT, false, false }, + { "frsqrte", OPTION_MASK_PPC_GFXOPT, false, false }, + { "frsqrtes", OPTION_MASK_POPCNTB, false, false }, + { "popcntd", OPTION_MASK_POPCNTD, false, false }, + { "cell", OPTION_MASK_FPRND, false, false }, { "power8-vector", RS6000_BTM_P8_VECTOR, false, false }, { "power9-vector", RS6000_BTM_P9_VECTOR, false, false }, { "power9-misc", RS6000_BTM_P9_MISC, false, false }, { "crypto", RS6000_BTM_CRYPTO, false, false }, { "htm", RS6000_BTM_HTM, false, false }, - { "hard-dfp", RS6000_BTM_DFP, false, false }, - { "hard-float", RS6000_BTM_HARD_FLOAT, false, false }, - { "long-double-128", RS6000_BTM_LDBL128, false, false }, - { "powerpc64", RS6000_BTM_POWERPC64, false, false }, - { "float128", RS6000_BTM_FLOAT128, false, false }, - { "float128-hw", RS6000_BTM_FLOAT128_HW,false, false }, - { "mma", RS6000_BTM_MMA, false, false }, - { "power10", RS6000_BTM_P10, false, false }, + { "hard-dfp", OPTION_MASK_DFP, false, false }, + { "hard-float", OPTION_MASK_SOFT_FLOAT, false, false }, + { "long-double-128", OPTION_MASK_MULTIPLE, false, false }, + { "powerpc64", MASK_POWERPC64, false, false }, + { "float128", OPTION_MASK_FLOAT128_KEYWORD, false, false }, + { "float128-hw", OPTION_MASK_FLOAT128_HW,false, false }, + { "mma", OPTION_MASK_MMA, false, false }, + { "power10", OPTION_MASK_POWER10, false, false }, }; /* Option variables that we want to support inside attribute((target)) and #pragma GCC target operations. */ diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 2ff17a16e43c..384c5f1599a5 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -2251,24 +2251,10 @@ extern int frame_pointer_needed; #define RS6000_BTM_P9_VECTOR MASK_P9_VECTOR /* ISA 3.0 vector. */ #define RS6000_BTM_P9_MISC MASK_P9_MISC /* ISA 3.0 misc. non-vector */ #define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */ #define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */ #define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */ -#define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */ -#define RS6000_BTM_FRSQRTE MASK_PPC_GFXOPT /* FRSQRTE instruction. */ -#define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */ -#define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */ -#define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */ -#define RS6000_BTM_DFP MASK_DFP /* Decimal floating point. */ -#define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */ -#define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */ -#define RS6000_BTM_64BIT MASK_64BIT /* 64-bit addressing. */ -#define RS6000_BTM_POWERPC64 MASK_POWERPC64 /* 64-bit registers. */ -#define RS6000_BTM_FLOAT128 MASK_FLOAT128_KEYWORD /* IEEE 128-bit float. */ -#define RS6000_BTM_FLOAT128_HW MASK_FLOAT128_HW /* IEEE 128-bit float h/w. */ -#define RS6000_BTM_MMA MASK_MMA /* ISA 3.1 MMA. */ -#define RS6000_BTM_P10 MASK_POWER10 enum rs6000_builtin_type_index { RS6000_BTI_NOT_OPAQUE, From patchwork Mon Jun 6 22:05:54 2022 Content-Type: text/plain; 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To: gcc-patches@gcc.gnu.org Date: Mon, 06 Jun 2022 17:05:54 -0500 In-Reply-To: <21f1b472875d5c75e151e647c5182a74e426559f.camel@vnet.ibm.com> References: <21f1b472875d5c75e151e647c5182a74e426559f.camel@vnet.ibm.com> X-Mailer: Evolution 3.28.5 (3.28.5-18.el8) Mime-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: YWqDUVK6UUR5vkVrgadqV-VRLsQRRSmI X-Proofpoint-GUID: gltnxEzV7l6kCotQoGoHZB_Ya76OJx_Z X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-06_07,2022-06-03_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 mlxscore=0 mlxlogscore=960 clxscore=1015 spamscore=0 priorityscore=1501 adultscore=0 impostorscore=0 phishscore=0 bulkscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2204290000 definitions=main-2206060087 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: will schmidt via Gcc-patches From: will schmidt Reply-To: will schmidt Cc: David Edelsohn , Segher Boessenkool Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" [PATCH, RS6000 3/5] Rework the RS6000_BTM defines, continued. The RS6000_BTM_ definitions are mostly unused after the rs6000 builtin code was reworked. This cleans up the remaining RS6000_BTM_ references by replacing them with their OPTION_MASK_ equivalents. This patch removes the defines RS6000_BTM_MODULO, RS6000_BTM_ALTIVEC, RS6000_BTM_CMPB, RS6000_BTM_VSX, RS6000_BTM_P8_VECTOR, RS6000_BTM_P9_VECTOR, RS6000_BTM_P9_MISC, RS6000_BTM_CRYPTO, RS6000_BTM_HTM, RS6000_BTM_FRE. gcc/ * config/rs6000/rs6000.cc (RS6000_BTM_ALTIVEC, RS6000_BTM_CMPB, RS6000_BTM_VSX, RS6000_BTM_FRE, RS6000_BTM_P8_VECTOR, RS6000_BTM_P9_VECTOR, RS6000_BTM_P9_MISC, RS6000_BTM_MODULO, RS6000_BTM_CRYPTO, RS6000_BTM_HTM): Replace with OPTION_MASK_ALTIVEC, OPTION_MASK_CMPB, OPTION_MASK_VSX, OPTION_MASK_POPCNTB, OPTION_MASK_P8_VECTOR, OPTION_MASK_P9_VECTOR, OPTION_MASK_P9_MISC, OPTION_MASK_MODULO, OPTION_MASK_CRYPTO, OPTION_MASK_HTM. * config/rs6000/rs6000.h (RS6000_BTM_MODULO, RS6000_BTM_ALTIVEC, RS6000_BTM_CMPB, RS6000_BTM_VSX, RS6000_BTM_P8_VECTOR, RS6000_BTM_P9_VECTOR, RS6000_BTM_P9_MISC, RS6000_BTM_CRYPTO, RS6000_BTM_HTM, RS6000_BTM_FRE): Remove. diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 253110910bfa..6b7a6db9a445 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -3377,27 +3377,27 @@ darwin_rs6000_override_options (void) bits, and some options are no longer in target_flags. */ HOST_WIDE_INT rs6000_builtin_mask_calculate (void) { - return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0) - | ((TARGET_CMPB) ? RS6000_BTM_CMPB : 0) - | ((TARGET_VSX) ? RS6000_BTM_VSX : 0) - | ((TARGET_FRE) ? RS6000_BTM_FRE : 0) + return (((TARGET_ALTIVEC) ? OPTION_MASK_ALTIVEC : 0) + | ((TARGET_CMPB) ? OPTION_MASK_CMPB : 0) + | ((TARGET_VSX) ? OPTION_MASK_VSX : 0) + | ((TARGET_FRE) ? OPTION_MASK_POPCNTB : 0) | ((TARGET_FRES) ? OPTION_MASK_PPC_GFXOPT : 0) | ((TARGET_FRSQRTE) ? OPTION_MASK_PPC_GFXOPT : 0) | ((TARGET_FRSQRTES) ? OPTION_MASK_POPCNTB : 0) | ((TARGET_POPCNTD) ? OPTION_MASK_POPCNTD : 0) | ((rs6000_cpu == PROCESSOR_CELL) ? OPTION_MASK_FPRND : 0) - | ((TARGET_P8_VECTOR) ? RS6000_BTM_P8_VECTOR : 0) - | ((TARGET_P9_VECTOR) ? RS6000_BTM_P9_VECTOR : 0) - | ((TARGET_P9_MISC) ? RS6000_BTM_P9_MISC : 0) - | ((TARGET_MODULO) ? RS6000_BTM_MODULO : 0) + | ((TARGET_P8_VECTOR) ? OPTION_MASK_P8_VECTOR : 0) + | ((TARGET_P9_VECTOR) ? OPTION_MASK_P9_VECTOR : 0) + | ((TARGET_P9_MISC) ? OPTION_MASK_P9_MISC : 0) + | ((TARGET_MODULO) ? OPTION_MASK_MODULO : 0) | ((TARGET_64BIT) ? MASK_64BIT : 0) | ((TARGET_POWERPC64) ? MASK_POWERPC64 : 0) - | ((TARGET_CRYPTO) ? RS6000_BTM_CRYPTO : 0) - | ((TARGET_HTM) ? RS6000_BTM_HTM : 0) + | ((TARGET_CRYPTO) ? OPTION_MASK_CRYPTO : 0) + | ((TARGET_HTM) ? OPTION_MASK_HTM : 0) | ((TARGET_DFP) ? OPTION_MASK_DFP : 0) | ((TARGET_HARD_FLOAT) ? OPTION_MASK_SOFT_FLOAT : 0) | ((TARGET_LONG_DOUBLE_128 && TARGET_HARD_FLOAT && !TARGET_IEEEQUAD) ? OPTION_MASK_MULTIPLE : 0) @@ -24044,23 +24044,23 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] = }; /* Builtin mask mapping for printing the flags. */ static struct rs6000_opt_mask const rs6000_builtin_mask_names[] = { - { "altivec", RS6000_BTM_ALTIVEC, false, false }, - { "vsx", RS6000_BTM_VSX, false, false }, - { "fre", RS6000_BTM_FRE, false, false }, + { "altivec", OPTION_MASK_ALTIVEC, false, false }, + { "vsx", OPTION_MASK_VSX, false, false }, + { "fre", OPTION_MASK_POPCNTB, false, false }, { "fres", OPTION_MASK_PPC_GFXOPT, false, false }, { "frsqrte", OPTION_MASK_PPC_GFXOPT, false, false }, { "frsqrtes", OPTION_MASK_POPCNTB, false, false }, { "popcntd", OPTION_MASK_POPCNTD, false, false }, { "cell", OPTION_MASK_FPRND, false, false }, - { "power8-vector", RS6000_BTM_P8_VECTOR, false, false }, - { "power9-vector", RS6000_BTM_P9_VECTOR, false, false }, - { "power9-misc", RS6000_BTM_P9_MISC, false, false }, - { "crypto", RS6000_BTM_CRYPTO, false, false }, - { "htm", RS6000_BTM_HTM, false, false }, + { "power8-vector", OPTION_MASK_P8_VECTOR, false, false }, + { "power9-vector", OPTION_MASK_P9_VECTOR, false, false }, + { "power9-misc", OPTION_MASK_P9_MISC, false, false }, + { "crypto", OPTION_MASK_CRYPTO, false, false }, + { "htm", OPTION_MASK_HTM, false, false }, { "hard-dfp", OPTION_MASK_DFP, false, false }, { "hard-float", OPTION_MASK_SOFT_FLOAT, false, false }, { "long-double-128", OPTION_MASK_MULTIPLE, false, false }, { "powerpc64", MASK_POWERPC64, false, false }, { "float128", OPTION_MASK_FLOAT128_KEYWORD, false, false }, diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 384c5f1599a5..72eb473acbc3 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -551,15 +551,10 @@ extern int rs6000_vector_align[]; #ifdef TARGET_LITTLE_ENDIAN #define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN #endif -#ifdef TARGET_MODULO -#define RS6000_BTM_MODULO OPTION_MASK_MODULO -#endif - - /* For power systems, we want to enable Altivec and VSX builtins even if the user did not use -maltivec or -mvsx to allow the builtins to be used inside of #pragma GCC target or the target attribute to change the code level for a given system. */ @@ -2238,25 +2233,10 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ /* #define MACHINE_no_sched_speculative_load */ /* General flags. */ extern int frame_pointer_needed; - -/* Builtin targets. For now, we reuse the masks for those options that are in - target flags, and pick a random bit for ldbl128, which isn't in - target_flags. */ -#define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */ -#define RS6000_BTM_CMPB MASK_CMPB /* ISA 2.05: compare bytes. */ -#define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */ -#define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */ -#define RS6000_BTM_P9_VECTOR MASK_P9_VECTOR /* ISA 3.0 vector. */ -#define RS6000_BTM_P9_MISC MASK_P9_MISC /* ISA 3.0 misc. non-vector */ -#define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */ -#define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */ -#define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */ - - enum rs6000_builtin_type_index { RS6000_BTI_NOT_OPAQUE, RS6000_BTI_opaque_V4SI, RS6000_BTI_V16QI, /* __vector signed char */ From patchwork Mon Jun 6 22:07:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: will schmidt X-Patchwork-Id: 1639636 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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Mon, 6 Jun 2022 22:07:54 GMT Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 85965124053; Mon, 6 Jun 2022 22:07:54 +0000 (GMT) Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 16345124052; Mon, 6 Jun 2022 22:07:54 +0000 (GMT) Received: from lexx (unknown [9.160.81.62]) by b01ledav002.gho.pok.ibm.com (Postfix) with ESMTP; Mon, 6 Jun 2022 22:07:53 +0000 (GMT) Message-ID: <3808197933afead6b0b065cfbb3a44df8045965c.camel@vnet.ibm.com> Subject: [PATCH,RS6000 4/5] Replace MASK_ with OPTION_MASK_ To: gcc-patches@gcc.gnu.org Date: Mon, 06 Jun 2022 17:07:53 -0500 In-Reply-To: <21f1b472875d5c75e151e647c5182a74e426559f.camel@vnet.ibm.com> References: <21f1b472875d5c75e151e647c5182a74e426559f.camel@vnet.ibm.com> X-Mailer: Evolution 3.28.5 (3.28.5-18.el8) X-TM-AS-GCONF: 00 X-Proofpoint-GUID: mqGNXgFD0u5vSWZ-QQKtBpNyNXAE5KEo X-Proofpoint-ORIG-GUID: dzBzR2X1VJTaw68g15swqMkebXEcJXMg X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-06_07,2022-06-03_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 suspectscore=0 adultscore=0 phishscore=0 spamscore=0 mlxlogscore=999 mlxscore=0 malwarescore=0 lowpriorityscore=0 clxscore=1015 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2204290000 definitions=main-2206060087 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UPPERCASE_50_75 autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: will schmidt via Gcc-patches From: will schmidt Reply-To: will schmidt Cc: David Edelsohn , Segher Boessenkool Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" [PATCH,RS6000 4/5] Replace MASK_ with OPTION_MASK_ This replaces the MASK_ references with OPTION_MASK_ and removes the now unused defines. This patch removes the defines for MASK_ALTIVEC, MASK_CMPB, MASK_CRYPTO, MASK_DFP, MASK_DIRECT_MOVE, MASK_DLMZB, MASK_EABI, MASK_FLOAT128_KEYWORD, MASK_FLOAT128_HW, MASK_FPRND, MASK_P8_FUSION, MASK_HARD_FLOAT, MASK_HTM, MASK_MFCRF, MASK_MMA, MASK_MULHW, MASK_MULTIPLE, MASK_NO_UPDATE. gcc/ * config/rs6000/aix71.h (TARGET_DEFAULT): Replace MASK_MFCRF with OPTION_MASK_MFCRF. * config/rs6000/darwin.h (TARGET_DEFAULT): Replace MASK_MULTIPLE with OPTION_MASK_MULTIPLE. * config/rs6000/darwin64-biarch.h (TARGET_DEFAULT): Same. * config/rs6000/default.h (TARGET_DEFAULT): Replace MASK_MFCRF with OPTION_MASK_MFCRF. * config/rs6000/eabi.h (TARGET_DEFAULT): Replace MASK_EABI with OPTION_MASK_EABI. * config/rs6000/eabialtivec.h (TARGET_DEFAULT): Same. * config/rs6000/linuxaltivec.h (TARGET_DEFAULT): Replace MASK_ALTIVEC with OPTION_MASK_ALTIVEC. * config/rs6000/rs6000-cpus.def (MASK_ALTIVEC, MASK_CMPB, MASK_CRYPTO, MASK_DFP, MASK_DIRECT_MOVE, MASK_DLMZB, MASK_EABI, MASK_FLOAT128_KEYWORD, MASK_FLOAT128_HW, MASK_FPRND, MASK_P8_FUSION, MASK_HARD_FLOAT, MASK_HTM, MASK_ISEL, MASK_MFCRF, MASK_MMA, MASK_MULHW, MASK_MULTIPLE, MASK_NO_UPDATE): Replace with OPTION_MASK_ALTIVEC, OPTION_MASK_CMPB, OPTION_MASK_CRYPTO, OPTION_MASK_DFP, OPTION_MASK_DIRECT_MOVE, OPTION_MASK_DLMZB, OPTION_MASK_EABI, OPTION_MASK_FLOAT128_KEYWORD, OPTION_MASK_FLOAT128_HW, OPTION_MASK_FPRND, OPTION_MASK_P8_FUSION, OPTION_MASK_HARD_FLOAT, OPTION_MASK_HTM, OPTION_MASK_ISEL, OPTION_MASK_MFCRF, OPTION_MASK_MMA, OPTION_MASK_MULHW, OPTION_MASK_MULTIPLE, OPTION_MASK_NO_UPDATE. * config/rs6000/rs6000.cc (rs6000_darwin_file_start): Replace MASK_MFCRF, MASK_ALTIVEC with OPTION_MASK_MFCRF, OPTION_MASK_ALTIVEC. * config/rs6000/rs6000.h (TARGET_DEFAULT): Replace MASK_MULTIPLE with OPTION_MASK_MULTIPLE. (MASK_ALTIVEC, MASK_CMPB, MASK_CRYPTO, MASK_DFP, MASK_DIRECT_MOVE, MASK_DLMZB, MASK_EABI, MASK_FLOAT128_KEYWORD, MASK_FLOAT128_HW, MASK_FPRND, MASK_P8_FUSION, MASK_HARD_FLOAT, MASK_HTM, MASK_ISEL, MASK_MFCRF, MASK_MMA, MASK_MULHW, MASK_MULTIPLE, MASK_NO_UPDATE): Delete. * config/rs6000/vxworks.h (TARGET_DEFAULT): Replace MASK_EABI with OPTION_MASK_EABI. diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h index 57e07bcc65ee..3f7e6e380ca8 100644 --- a/gcc/config/rs6000/aix71.h +++ b/gcc/config/rs6000/aix71.h @@ -135,13 +135,14 @@ do { \ #include "rs6000-cpus.def" #undef RS6000_CPU #undef TARGET_DEFAULT #ifdef RS6000_BI_ARCH -#define TARGET_DEFAULT (MASK_PPC_GPOPT | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64 | MASK_64BIT) +#define TARGET_DEFAULT (MASK_PPC_GPOPT | MASK_PPC_GFXOPT \ + | OPTION_MASK_MFCRF | MASK_POWERPC64 | MASK_64BIT) #else -#define TARGET_DEFAULT (MASK_PPC_GPOPT | MASK_PPC_GFXOPT | MASK_MFCRF) +#define TARGET_DEFAULT (MASK_PPC_GPOPT | MASK_PPC_GFXOPT | OPTION_MASK_MFCRF) #endif #undef PROCESSOR_DEFAULT #define PROCESSOR_DEFAULT PROCESSOR_POWER7 #undef PROCESSOR_DEFAULT64 diff --git a/gcc/config/rs6000/darwin.h b/gcc/config/rs6000/darwin.h index b5cef42610f7..ec02022c6a9f 100644 --- a/gcc/config/rs6000/darwin.h +++ b/gcc/config/rs6000/darwin.h @@ -365,11 +365,11 @@ /* Default target flag settings. Despite the fact that STMW/LMW serializes, it's still a big code size win to use them. Use FSEL by default as well. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_MULTIPLE | MASK_PPC_GFXOPT) +#define TARGET_DEFAULT (OPTION_MASK_MULTIPLE | MASK_PPC_GFXOPT) /* Darwin always uses IBM long double, never IEEE long double. */ #undef TARGET_IEEEQUAD #define TARGET_IEEEQUAD 0 diff --git a/gcc/config/rs6000/darwin64-biarch.h b/gcc/config/rs6000/darwin64-biarch.h index 57b0fab084e3..a53e567f8b73 100644 --- a/gcc/config/rs6000/darwin64-biarch.h +++ b/gcc/config/rs6000/darwin64-biarch.h @@ -19,11 +19,11 @@ along with GCC; see the file COPYING3. If not see . */ #undef TARGET_DEFAULT #define TARGET_DEFAULT (MASK_POWERPC64 | MASK_64BIT \ - | MASK_MULTIPLE | MASK_PPC_GFXOPT) + | OPTION_MASK_MULTIPLE | MASK_PPC_GFXOPT) #undef DARWIN_ARCH_SPEC #define DARWIN_ARCH_SPEC "%{m32:ppc;:ppc64}" /* Actually, there's really only 970 as an active option. */ diff --git a/gcc/config/rs6000/default64.h b/gcc/config/rs6000/default64.h index 4bf0feef2f8e..f3a81404eff3 100644 --- a/gcc/config/rs6000/default64.h +++ b/gcc/config/rs6000/default64.h @@ -22,14 +22,16 @@ along with GCC; see the file COPYING3. If not see #include "rs6000-cpus.def" #undef RS6000_CPU #if (TARGET_DEFAULT & MASK_LITTLE_ENDIAN) #undef TARGET_DEFAULT -#define TARGET_DEFAULT (ISA_2_7_MASKS_SERVER | MASK_POWERPC64 | MASK_64BIT | MASK_LITTLE_ENDIAN) +#define TARGET_DEFAULT (ISA_2_7_MASKS_SERVER | MASK_POWERPC64 | MASK_64BIT \ + | MASK_LITTLE_ENDIAN) #undef ASM_DEFAULT_SPEC #define ASM_DEFAULT_SPEC "-mpower8" #else #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_PPC_GFXOPT | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 | MASK_64BIT) +#define TARGET_DEFAULT (MASK_PPC_GFXOPT | MASK_PPC_GPOPT \ + | OPTION_MASK_MFCRF | MASK_POWERPC64 | MASK_64BIT) #undef ASM_DEFAULT_SPEC #define ASM_DEFAULT_SPEC "-mpower4" #endif diff --git a/gcc/config/rs6000/eabi.h b/gcc/config/rs6000/eabi.h index e58283fe5d4e..367de7bc2700 100644 --- a/gcc/config/rs6000/eabi.h +++ b/gcc/config/rs6000/eabi.h @@ -19,11 +19,11 @@ along with GCC; see the file COPYING3. If not see . */ /* Add -meabi to target flags. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT MASK_EABI +#define TARGET_DEFAULT OPTION_MASK_EABI /* Invoke an initializer function to set up the GOT. */ #define NAME__MAIN "__eabi" #define INVOKE__main diff --git a/gcc/config/rs6000/eabialtivec.h b/gcc/config/rs6000/eabialtivec.h index 63cb00fa8054..23cef799a045 100644 --- a/gcc/config/rs6000/eabialtivec.h +++ b/gcc/config/rs6000/eabialtivec.h @@ -19,11 +19,11 @@ along with GCC; see the file COPYING3. If not see . */ /* Add -meabi and -maltivec to target flags. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_EABI | MASK_ALTIVEC) +#define TARGET_DEFAULT (OPTION_MASK_EABI | OPTION_MASK_ALTIVEC) #undef ASM_DEFAULT_EXTRA #define ASM_DEFAULT_EXTRA " %{!mvsx:%{!maltivec:%{!no-maltivec:-maltivec}}}" #undef SUBSUBTARGET_OVERRIDE_OPTIONS diff --git a/gcc/config/rs6000/linuxaltivec.h b/gcc/config/rs6000/linuxaltivec.h index d2557ca57adb..55bae1188369 100644 --- a/gcc/config/rs6000/linuxaltivec.h +++ b/gcc/config/rs6000/linuxaltivec.h @@ -20,14 +20,14 @@ . */ /* Override rs6000.h and sysv4.h definition. */ #if (TARGET_DEFAULT & MASK_LITTLE_ENDIAN) #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_ALTIVEC | MASK_LITTLE_ENDIAN) +#define TARGET_DEFAULT (OPTION_MASK_ALTIVEC | MASK_LITTLE_ENDIAN) #else #undef TARGET_DEFAULT -#define TARGET_DEFAULT MASK_ALTIVEC +#define TARGET_DEFAULT OPTION_MASK_ALTIVEC #endif #undef ASM_DEFAULT_EXTRA #define ASM_DEFAULT_EXTRA " %{!mvsx:%{!maltivec:%{!mno-altivec:-maltivec}}}" diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 963947f69392..7d226493dc54 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -176,24 +176,29 @@ where the arguments are the fields of struct rs6000_ptt. */ RS6000_CPU ("401", PROCESSOR_PPC403, MASK_SOFT_FLOAT) RS6000_CPU ("403", PROCESSOR_PPC403, MASK_SOFT_FLOAT | MASK_STRICT_ALIGN) -RS6000_CPU ("405", PROCESSOR_PPC405, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB) -RS6000_CPU ("405fp", PROCESSOR_PPC405, MASK_MULHW | MASK_DLMZB) -RS6000_CPU ("440", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB) -RS6000_CPU ("440fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB) -RS6000_CPU ("464", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB) -RS6000_CPU ("464fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB) -RS6000_CPU ("476", PROCESSOR_PPC476, - MASK_SOFT_FLOAT | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB - | MASK_FPRND | MASK_CMPB | MASK_MULHW | MASK_DLMZB) +RS6000_CPU ("405", PROCESSOR_PPC405, MASK_SOFT_FLOAT | OPTION_MASK_MULHW + | OPTION_MASK_DLMZB) +RS6000_CPU ("405fp", PROCESSOR_PPC405, OPTION_MASK_MULHW | OPTION_MASK_DLMZB) +RS6000_CPU ("440", PROCESSOR_PPC440, MASK_SOFT_FLOAT | OPTION_MASK_MULHW + | OPTION_MASK_DLMZB) +RS6000_CPU ("440fp", PROCESSOR_PPC440, OPTION_MASK_MULHW | OPTION_MASK_DLMZB) +RS6000_CPU ("464", PROCESSOR_PPC440, MASK_SOFT_FLOAT | OPTION_MASK_MULHW + | OPTION_MASK_DLMZB) +RS6000_CPU ("464fp", PROCESSOR_PPC440, OPTION_MASK_MULHW | OPTION_MASK_DLMZB) +RS6000_CPU ("476", PROCESSOR_PPC476, MASK_SOFT_FLOAT | MASK_PPC_GFXOPT + | OPTION_MASK_MFCRF | MASK_POPCNTB + | OPTION_MASK_FPRND | OPTION_MASK_CMPB | OPTION_MASK_MULHW + | OPTION_MASK_DLMZB) RS6000_CPU ("476fp", PROCESSOR_PPC476, - MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND - | MASK_CMPB | MASK_MULHW | MASK_DLMZB) + MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | MASK_POPCNTB + | OPTION_MASK_FPRND + | OPTION_MASK_CMPB | OPTION_MASK_MULHW | OPTION_MASK_DLMZB) RS6000_CPU ("505", PROCESSOR_MPCCORE, 0) -RS6000_CPU ("601", PROCESSOR_PPC601, MASK_MULTIPLE) +RS6000_CPU ("601", PROCESSOR_PPC601, OPTION_MASK_MULTIPLE) RS6000_CPU ("602", PROCESSOR_PPC603, MASK_PPC_GFXOPT) RS6000_CPU ("603", PROCESSOR_PPC603, MASK_PPC_GFXOPT) RS6000_CPU ("603e", PROCESSOR_PPC603, MASK_PPC_GFXOPT) RS6000_CPU ("604", PROCESSOR_PPC604, MASK_PPC_GFXOPT) RS6000_CPU ("604e", PROCESSOR_PPC604e, MASK_PPC_GFXOPT) @@ -204,48 +209,51 @@ RS6000_CPU ("7400", PROCESSOR_PPC7400, POWERPC_7400_MASK) RS6000_CPU ("7450", PROCESSOR_PPC7450, POWERPC_7400_MASK) RS6000_CPU ("750", PROCESSOR_PPC750, MASK_PPC_GFXOPT) RS6000_CPU ("801", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT) RS6000_CPU ("821", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT) RS6000_CPU ("823", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT) -RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN | MASK_ISEL) -RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN | MASK_ISEL) +RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN | OPTION_MASK_ISEL) +RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN | OPTION_MASK_ISEL) RS6000_CPU ("a2", PROCESSOR_PPCA2, - MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_POPCNTB | MASK_CMPB - | MASK_NO_UPDATE) + MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_POPCNTB | OPTION_MASK_CMPB + | OPTION_MASK_NO_UPDATE) RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, MASK_SOFT_FLOAT) RS6000_CPU ("e300c3", PROCESSOR_PPCE300C3, 0) -RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, MASK_PPC_GFXOPT | MASK_ISEL) +RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, MASK_PPC_GFXOPT | OPTION_MASK_ISEL) RS6000_CPU ("e500mc64", PROCESSOR_PPCE500MC64, - MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL) + MASK_POWERPC64 | MASK_PPC_GFXOPT | OPTION_MASK_ISEL) RS6000_CPU ("e5500", PROCESSOR_PPCE5500, - MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL) + MASK_POWERPC64 | MASK_PPC_GFXOPT | OPTION_MASK_ISEL) RS6000_CPU ("e6500", PROCESSOR_PPCE6500, POWERPC_7400_MASK | MASK_POWERPC64 - | MASK_MFCRF | MASK_ISEL) + | OPTION_MASK_MFCRF | OPTION_MASK_ISEL) RS6000_CPU ("860", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT) -RS6000_CPU ("970", PROCESSOR_POWER4, - POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64) -RS6000_CPU ("cell", PROCESSOR_CELL, - POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64) +RS6000_CPU ("970", PROCESSOR_POWER4, POWERPC_7400_MASK | MASK_PPC_GPOPT + | OPTION_MASK_MFCRF | MASK_POWERPC64) +RS6000_CPU ("cell", PROCESSOR_CELL, POWERPC_7400_MASK | MASK_PPC_GPOPT + | OPTION_MASK_MFCRF | MASK_POWERPC64) RS6000_CPU ("ec603e", PROCESSOR_PPC603, MASK_SOFT_FLOAT) RS6000_CPU ("G3", PROCESSOR_PPC750, MASK_PPC_GFXOPT) RS6000_CPU ("G4", PROCESSOR_PPC7450, POWERPC_7400_MASK) -RS6000_CPU ("G5", PROCESSOR_POWER4, - POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64) -RS6000_CPU ("titan", PROCESSOR_TITAN, MASK_MULHW | MASK_DLMZB) +RS6000_CPU ("G5", PROCESSOR_POWER4, POWERPC_7400_MASK | MASK_PPC_GPOPT + | OPTION_MASK_MFCRF | MASK_POWERPC64) +RS6000_CPU ("titan", PROCESSOR_TITAN, OPTION_MASK_MULHW | OPTION_MASK_DLMZB) RS6000_CPU ("power3", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64) RS6000_CPU ("power4", PROCESSOR_POWER4, MASK_POWERPC64 | MASK_PPC_GPOPT - | MASK_PPC_GFXOPT | MASK_MFCRF) + | MASK_PPC_GFXOPT | OPTION_MASK_MFCRF) RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT - | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB) + | MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | MASK_POPCNTB) RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT - | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND) + | MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | MASK_POPCNTB + | OPTION_MASK_FPRND) RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT - | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND - | MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION) + | MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | MASK_POPCNTB + | OPTION_MASK_FPRND | OPTION_MASK_CMPB | OPTION_MASK_DFP + | MASK_RECIP_PRECISION) RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT - | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND - | MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION) + | MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | MASK_POPCNTB + | OPTION_MASK_FPRND | OPTION_MASK_CMPB | OPTION_MASK_DFP + | MASK_RECIP_PRECISION) RS6000_CPU ("power7", PROCESSOR_POWER7, MASK_POWERPC64 | ISA_2_6_MASKS_SERVER) RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER | OPTION_MASK_HTM) RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER | OPTION_MASK_HTM) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 6b7a6db9a445..2faac05b5045 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -20727,15 +20727,15 @@ rs6000_darwin_file_start (void) const char *arg; const char *name; HOST_WIDE_INT if_set; } mapping[] = { { "ppc64", "ppc64", MASK_64BIT }, - { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 }, + { "970", "ppc970", MASK_PPC_GPOPT | OPTION_MASK_MFCRF | MASK_POWERPC64 }, { "power4", "ppc970", 0 }, { "G5", "ppc970", 0 }, { "7450", "ppc7450", 0 }, - { "7400", "ppc7400", MASK_ALTIVEC }, + { "7400", "ppc7400", OPTION_MASK_ALTIVEC }, { "G4", "ppc7400", 0 }, { "750", "ppc750", 0 }, { "740", "ppc750", 0 }, { "G3", "ppc750", 0 }, { "604e", "ppc604e", 0 }, diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 72eb473acbc3..4d180bd95e59 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -277,11 +277,11 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); #endif #else /* The option machinery will define this. */ #endif -#define TARGET_DEFAULT (MASK_MULTIPLE) +#define TARGET_DEFAULT (OPTION_MASK_MULTIPLE) /* Define generic processor types based upon current deployment. */ #define PROCESSOR_COMMON PROCESSOR_PPC601 #define PROCESSOR_POWERPC PROCESSOR_PPC604 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A @@ -506,29 +506,10 @@ extern int rs6000_vector_align[]; /* In switching from using target_flags to using rs6000_isa_flags, the options machinery creates OPTION_MASK_ instead of MASK_. The MASK_ options that have not yet been replaced by their OPTION_MASK_ equivalents are defined here. */ -#define MASK_ALTIVEC OPTION_MASK_ALTIVEC -#define MASK_CMPB OPTION_MASK_CMPB -#define MASK_CRYPTO OPTION_MASK_CRYPTO -#define MASK_DFP OPTION_MASK_DFP -#define MASK_DIRECT_MOVE OPTION_MASK_DIRECT_MOVE -#define MASK_DLMZB OPTION_MASK_DLMZB -#define MASK_EABI OPTION_MASK_EABI -#define MASK_FLOAT128_KEYWORD OPTION_MASK_FLOAT128_KEYWORD -#define MASK_FLOAT128_HW OPTION_MASK_FLOAT128_HW -#define MASK_FPRND OPTION_MASK_FPRND -#define MASK_P8_FUSION OPTION_MASK_P8_FUSION -#define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT -#define MASK_HTM OPTION_MASK_HTM -#define MASK_ISEL OPTION_MASK_ISEL -#define MASK_MFCRF OPTION_MASK_MFCRF -#define MASK_MMA OPTION_MASK_MMA -#define MASK_MULHW OPTION_MASK_MULHW -#define MASK_MULTIPLE OPTION_MASK_MULTIPLE -#define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE #define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR #define MASK_P9_VECTOR OPTION_MASK_P9_VECTOR #define MASK_P9_MISC OPTION_MASK_P9_MISC #define MASK_POPCNTB OPTION_MASK_POPCNTB #define MASK_POPCNTD OPTION_MASK_POPCNTD diff --git a/gcc/config/rs6000/vxworks.h b/gcc/config/rs6000/vxworks.h index 4f6d116929b6..6f11de6c5792 100644 --- a/gcc/config/rs6000/vxworks.h +++ b/gcc/config/rs6000/vxworks.h @@ -225,11 +225,11 @@ along with GCC; see the file COPYING3. If not see #undef LINK_SPEC #define LINK_SPEC VXWORKS_LINK_SPEC " " VXWORKS_RELAX_LINK_SPEC #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_EABI | MASK_STRICT_ALIGN) +#define TARGET_DEFAULT (OPTION_MASK_EABI | MASK_STRICT_ALIGN) #undef PROCESSOR_DEFAULT #define PROCESSOR_DEFAULT PROCESSOR_PPC604 /* Only big endian PPC is supported by VxWorks. */ From patchwork Mon Jun 6 22:07:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: will schmidt X-Patchwork-Id: 1639635 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=OWQ1TtBV; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; 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Mon, 6 Jun 2022 22:07:51 GMT Received: from b03cxnp07028.gho.boulder.ibm.com (b03cxnp07028.gho.boulder.ibm.com [9.17.130.15]) by ppma05wdc.us.ibm.com with ESMTP id 3gfy19gay1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 06 Jun 2022 22:07:51 +0000 Received: from b03ledav005.gho.boulder.ibm.com (b03ledav005.gho.boulder.ibm.com [9.17.130.236]) by b03cxnp07028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 256M7oYQ26673476 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 6 Jun 2022 22:07:50 GMT Received: from b03ledav005.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3BBA0BE051; Mon, 6 Jun 2022 22:07:50 +0000 (GMT) Received: from b03ledav005.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 960A4BE058; Mon, 6 Jun 2022 22:07:49 +0000 (GMT) Received: from lexx (unknown [9.160.81.62]) by b03ledav005.gho.boulder.ibm.com (Postfix) with ESMTP; Mon, 6 Jun 2022 22:07:49 +0000 (GMT) Message-ID: <7bfb91c2fff8856ee8f2f4f9d6f87115097bf85b.camel@vnet.ibm.com> Subject: [PATCH,RS6000 5/5] Replace MASK_ usage with OPTION_MASK_ To: gcc-patches@gcc.gnu.org Date: Mon, 06 Jun 2022 17:07:30 -0500 In-Reply-To: <21f1b472875d5c75e151e647c5182a74e426559f.camel@vnet.ibm.com> References: <21f1b472875d5c75e151e647c5182a74e426559f.camel@vnet.ibm.com> X-Mailer: Evolution 3.28.5 (3.28.5-18.el8) X-TM-AS-GCONF: 00 X-Proofpoint-GUID: wI-k9O2N62l6yN6OrSmMEOUMiokkE0f2 X-Proofpoint-ORIG-GUID: 8YpVaAxiz3kljY3j3GdnUTvuJ6m4uzTi X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-06_07,2022-06-03_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 mlxscore=0 suspectscore=0 phishscore=0 clxscore=1015 adultscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 bulkscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2204290000 definitions=main-2206060087 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UPPERCASE_50_75 autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: will schmidt via Gcc-patches From: will schmidt Reply-To: will schmidt Cc: David Edelsohn , Segher Boessenkool Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" [PATCH,RS6000 5/5] Replace MASK_ usage with OPTION_MASK_ This continues the changes of replacing the MASK_ defines with their OPTION_MASK_ equivalents. This patch removes the defines for MASK_P8_VECTOR, MASK_P9_VECTOR, MASK_P9_MISC, MASK_POPCNTB, MASK_POPCNTD, MASK_PPC_GFXOPT, MASK_PPC_GPOPT, MASK_RECIP_PRECISION, MASK_SOFT_FLOAT, MASK_VSX, MASK_POWER10, MASK_P10_FUSION. gcc/ * config/rs6000/aix71.h (MASK_PPC_GPOPT, MASK_PPC_GFXOPT): Replace with OPTION_MASK_PPC_GPOPT, OPTION_MASK_PPC_GFXOPT. * config/rs6000/darwin.h (MASK_PPC_GFXOPT): Replace with OPTION_MASK_PPC_GFXOPT. * config/rs6000/darwin64-biarch.h (MASK_PPC_GFXOPT): Same. * config/rs6000/default64.h (MASK_PPC_GPOPT, MASK_PPC_GFXOPT): Replace with OPTION_MASK_PPC_GPOPT, OPTION_MASK_PPC_GFXOPT. * config/rs6000/rs6000-c.cc: Update comment. * config/rs6000/rs6000-cpus.def: Update RS6000_CPU macro calls. * config/rs6000/rs6000.cc (rs6000_darwin_file_start): Replace MASK_PPC_GPOPT with OPTION_MASK_PPC_GPOPT. (rs6000_builtin_mask_names): Replace MASK_PPC_GFXOPT, MASK_POPCNTB with OPTION_MASK_PPC_GFXOPT, OPTION_MASK_POPCNTB. * config/rs6000/rs6000.h: (MASK_P8_VECTOR, MASK_P9_VECTOR, MASK_P9_MISC, MASK_POPCNTB, MASK_POPCNTD, MASK_PPC_GFXOPT, MASK_PPC_GPOPT, MASK_RECIP_PRECISION, MASK_SOFT_FLOAT, MASK_VSX, MASK_POWER10, MASK_P10_FUSION): Delete. diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h index 3f7e6e380ca8..323d7c884d18 100644 --- a/gcc/config/rs6000/aix71.h +++ b/gcc/config/rs6000/aix71.h @@ -135,14 +135,15 @@ do { \ #include "rs6000-cpus.def" #undef RS6000_CPU #undef TARGET_DEFAULT #ifdef RS6000_BI_ARCH -#define TARGET_DEFAULT (MASK_PPC_GPOPT | MASK_PPC_GFXOPT \ +#define TARGET_DEFAULT (OPTION_MASK_PPC_GPOPT | OPTION_MASK_PPC_GFXOPT \ | OPTION_MASK_MFCRF | MASK_POWERPC64 | MASK_64BIT) #else -#define TARGET_DEFAULT (MASK_PPC_GPOPT | MASK_PPC_GFXOPT | OPTION_MASK_MFCRF) +#define TARGET_DEFAULT (OPTION_MASK_PPC_GPOPT | OPTION_MASK_PPC_GFXOPT \ + | OPTION_MASK_MFCRF) #endif #undef PROCESSOR_DEFAULT #define PROCESSOR_DEFAULT PROCESSOR_POWER7 #undef PROCESSOR_DEFAULT64 diff --git a/gcc/config/rs6000/darwin.h b/gcc/config/rs6000/darwin.h index ec02022c6a9f..6a8845eb3bb7 100644 --- a/gcc/config/rs6000/darwin.h +++ b/gcc/config/rs6000/darwin.h @@ -365,11 +365,11 @@ /* Default target flag settings. Despite the fact that STMW/LMW serializes, it's still a big code size win to use them. Use FSEL by default as well. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT (OPTION_MASK_MULTIPLE | MASK_PPC_GFXOPT) +#define TARGET_DEFAULT (OPTION_MASK_MULTIPLE | OPTION_MASK_PPC_GFXOPT) /* Darwin always uses IBM long double, never IEEE long double. */ #undef TARGET_IEEEQUAD #define TARGET_IEEEQUAD 0 diff --git a/gcc/config/rs6000/darwin64-biarch.h b/gcc/config/rs6000/darwin64-biarch.h index a53e567f8b73..6515bcc8bf5a 100644 --- a/gcc/config/rs6000/darwin64-biarch.h +++ b/gcc/config/rs6000/darwin64-biarch.h @@ -19,11 +19,11 @@ along with GCC; see the file COPYING3. If not see . */ #undef TARGET_DEFAULT #define TARGET_DEFAULT (MASK_POWERPC64 | MASK_64BIT \ - | OPTION_MASK_MULTIPLE | MASK_PPC_GFXOPT) + | OPTION_MASK_MULTIPLE | OPTION_MASK_PPC_GFXOPT) #undef DARWIN_ARCH_SPEC #define DARWIN_ARCH_SPEC "%{m32:ppc;:ppc64}" /* Actually, there's really only 970 as an active option. */ diff --git a/gcc/config/rs6000/default64.h b/gcc/config/rs6000/default64.h index f3a81404eff3..0bec94935e2b 100644 --- a/gcc/config/rs6000/default64.h +++ b/gcc/config/rs6000/default64.h @@ -28,10 +28,10 @@ along with GCC; see the file COPYING3. If not see | MASK_LITTLE_ENDIAN) #undef ASM_DEFAULT_SPEC #define ASM_DEFAULT_SPEC "-mpower8" #else #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_PPC_GFXOPT | MASK_PPC_GPOPT \ +#define TARGET_DEFAULT (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT \ | OPTION_MASK_MFCRF | MASK_POWERPC64 | MASK_64BIT) #undef ASM_DEFAULT_SPEC #define ASM_DEFAULT_SPEC "-mpower4" #endif diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc index 4c99afc761ae..0d13645040ff 100644 --- a/gcc/config/rs6000/rs6000-c.cc +++ b/gcc/config/rs6000/rs6000-c.cc @@ -382,11 +382,11 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags, 3. If either of the above two conditions apply except that the TARGET_DEFAULT macro is defined to equal zero, and TARGET_POWERPC64 and a) BYTES_BIG_ENDIAN and the flag to be enabled is either - MASK_PPC_GFXOPT or MASK_POWERPC64 (flags for "powerpc64" + OPTION_MASK_PPC_GFXOPT or MASK_POWERPC64 (flags for "powerpc64" target), or b) !BYTES_BIG_ENDIAN and the flag to be enabled is either MASK_POWERPC64 or it is one of the flags included in ISA_2_7_MASKS_SERVER (flags for "powerpc64le" target). diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 7d226493dc54..c3825bcccd84 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -174,92 +174,93 @@ RS6000_CPU (NAME, CPU, FLAGS) where the arguments are the fields of struct rs6000_ptt. */ -RS6000_CPU ("401", PROCESSOR_PPC403, MASK_SOFT_FLOAT) -RS6000_CPU ("403", PROCESSOR_PPC403, MASK_SOFT_FLOAT | MASK_STRICT_ALIGN) -RS6000_CPU ("405", PROCESSOR_PPC405, MASK_SOFT_FLOAT | OPTION_MASK_MULHW - | OPTION_MASK_DLMZB) +RS6000_CPU ("401", PROCESSOR_PPC403, OPTION_MASK_SOFT_FLOAT) +RS6000_CPU ("403", PROCESSOR_PPC403, OPTION_MASK_SOFT_FLOAT | MASK_STRICT_ALIGN) +RS6000_CPU ("405", PROCESSOR_PPC405, OPTION_MASK_SOFT_FLOAT + | OPTION_MASK_MULHW | OPTION_MASK_DLMZB) RS6000_CPU ("405fp", PROCESSOR_PPC405, OPTION_MASK_MULHW | OPTION_MASK_DLMZB) -RS6000_CPU ("440", PROCESSOR_PPC440, MASK_SOFT_FLOAT | OPTION_MASK_MULHW - | OPTION_MASK_DLMZB) +RS6000_CPU ("440", PROCESSOR_PPC440, OPTION_MASK_SOFT_FLOAT + | OPTION_MASK_MULHW | OPTION_MASK_DLMZB) RS6000_CPU ("440fp", PROCESSOR_PPC440, OPTION_MASK_MULHW | OPTION_MASK_DLMZB) -RS6000_CPU ("464", PROCESSOR_PPC440, MASK_SOFT_FLOAT | OPTION_MASK_MULHW - | OPTION_MASK_DLMZB) +RS6000_CPU ("464", PROCESSOR_PPC440, OPTION_MASK_SOFT_FLOAT + | OPTION_MASK_MULHW | OPTION_MASK_DLMZB) RS6000_CPU ("464fp", PROCESSOR_PPC440, OPTION_MASK_MULHW | OPTION_MASK_DLMZB) -RS6000_CPU ("476", PROCESSOR_PPC476, MASK_SOFT_FLOAT | MASK_PPC_GFXOPT - | OPTION_MASK_MFCRF | MASK_POPCNTB +RS6000_CPU ("476", PROCESSOR_PPC476, OPTION_MASK_SOFT_FLOAT + | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB | OPTION_MASK_FPRND | OPTION_MASK_CMPB | OPTION_MASK_MULHW | OPTION_MASK_DLMZB) -RS6000_CPU ("476fp", PROCESSOR_PPC476, - MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | MASK_POPCNTB - | OPTION_MASK_FPRND +RS6000_CPU ("476fp", PROCESSOR_PPC476, OPTION_MASK_PPC_GFXOPT + | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB | OPTION_MASK_FPRND | OPTION_MASK_CMPB | OPTION_MASK_MULHW | OPTION_MASK_DLMZB) RS6000_CPU ("505", PROCESSOR_MPCCORE, 0) RS6000_CPU ("601", PROCESSOR_PPC601, OPTION_MASK_MULTIPLE) -RS6000_CPU ("602", PROCESSOR_PPC603, MASK_PPC_GFXOPT) -RS6000_CPU ("603", PROCESSOR_PPC603, MASK_PPC_GFXOPT) -RS6000_CPU ("603e", PROCESSOR_PPC603, MASK_PPC_GFXOPT) -RS6000_CPU ("604", PROCESSOR_PPC604, MASK_PPC_GFXOPT) -RS6000_CPU ("604e", PROCESSOR_PPC604e, MASK_PPC_GFXOPT) -RS6000_CPU ("620", PROCESSOR_PPC620, MASK_PPC_GFXOPT | MASK_POWERPC64) -RS6000_CPU ("630", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64) -RS6000_CPU ("740", PROCESSOR_PPC750, MASK_PPC_GFXOPT) +RS6000_CPU ("602", PROCESSOR_PPC603, OPTION_MASK_PPC_GFXOPT) +RS6000_CPU ("603", PROCESSOR_PPC603, OPTION_MASK_PPC_GFXOPT) +RS6000_CPU ("603e", PROCESSOR_PPC603, OPTION_MASK_PPC_GFXOPT) +RS6000_CPU ("604", PROCESSOR_PPC604, OPTION_MASK_PPC_GFXOPT) +RS6000_CPU ("604e", PROCESSOR_PPC604e, OPTION_MASK_PPC_GFXOPT) +RS6000_CPU ("620", PROCESSOR_PPC620, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64) +RS6000_CPU ("630", PROCESSOR_PPC630, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64) +RS6000_CPU ("740", PROCESSOR_PPC750, OPTION_MASK_PPC_GFXOPT) RS6000_CPU ("7400", PROCESSOR_PPC7400, POWERPC_7400_MASK) RS6000_CPU ("7450", PROCESSOR_PPC7450, POWERPC_7400_MASK) -RS6000_CPU ("750", PROCESSOR_PPC750, MASK_PPC_GFXOPT) -RS6000_CPU ("801", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT) -RS6000_CPU ("821", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT) -RS6000_CPU ("823", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT) +RS6000_CPU ("750", PROCESSOR_PPC750, OPTION_MASK_PPC_GFXOPT) +RS6000_CPU ("801", PROCESSOR_MPCCORE, OPTION_MASK_SOFT_FLOAT) +RS6000_CPU ("821", PROCESSOR_MPCCORE, OPTION_MASK_SOFT_FLOAT) +RS6000_CPU ("823", PROCESSOR_MPCCORE, OPTION_MASK_SOFT_FLOAT) RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN | OPTION_MASK_ISEL) RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN | OPTION_MASK_ISEL) -RS6000_CPU ("a2", PROCESSOR_PPCA2, - MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_POPCNTB | OPTION_MASK_CMPB +RS6000_CPU ("a2", PROCESSOR_PPCA2, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64 + | OPTION_MASK_POPCNTB | OPTION_MASK_CMPB | OPTION_MASK_NO_UPDATE) -RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, MASK_SOFT_FLOAT) +RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, OPTION_MASK_SOFT_FLOAT) RS6000_CPU ("e300c3", PROCESSOR_PPCE300C3, 0) -RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, MASK_PPC_GFXOPT | OPTION_MASK_ISEL) +RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, OPTION_MASK_PPC_GFXOPT + | OPTION_MASK_ISEL) RS6000_CPU ("e500mc64", PROCESSOR_PPCE500MC64, - MASK_POWERPC64 | MASK_PPC_GFXOPT | OPTION_MASK_ISEL) + MASK_POWERPC64 | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ISEL) RS6000_CPU ("e5500", PROCESSOR_PPCE5500, - MASK_POWERPC64 | MASK_PPC_GFXOPT | OPTION_MASK_ISEL) + MASK_POWERPC64 | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ISEL) RS6000_CPU ("e6500", PROCESSOR_PPCE6500, POWERPC_7400_MASK | MASK_POWERPC64 | OPTION_MASK_MFCRF | OPTION_MASK_ISEL) -RS6000_CPU ("860", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT) -RS6000_CPU ("970", PROCESSOR_POWER4, POWERPC_7400_MASK | MASK_PPC_GPOPT +RS6000_CPU ("860", PROCESSOR_MPCCORE, OPTION_MASK_SOFT_FLOAT) +RS6000_CPU ("970", PROCESSOR_POWER4, POWERPC_7400_MASK | OPTION_MASK_PPC_GPOPT | OPTION_MASK_MFCRF | MASK_POWERPC64) -RS6000_CPU ("cell", PROCESSOR_CELL, POWERPC_7400_MASK | MASK_PPC_GPOPT +RS6000_CPU ("cell", PROCESSOR_CELL, POWERPC_7400_MASK | OPTION_MASK_PPC_GPOPT | OPTION_MASK_MFCRF | MASK_POWERPC64) -RS6000_CPU ("ec603e", PROCESSOR_PPC603, MASK_SOFT_FLOAT) -RS6000_CPU ("G3", PROCESSOR_PPC750, MASK_PPC_GFXOPT) +RS6000_CPU ("ec603e", PROCESSOR_PPC603, OPTION_MASK_SOFT_FLOAT) +RS6000_CPU ("G3", PROCESSOR_PPC750, OPTION_MASK_PPC_GFXOPT) RS6000_CPU ("G4", PROCESSOR_PPC7450, POWERPC_7400_MASK) -RS6000_CPU ("G5", PROCESSOR_POWER4, POWERPC_7400_MASK | MASK_PPC_GPOPT +RS6000_CPU ("G5", PROCESSOR_POWER4, POWERPC_7400_MASK | OPTION_MASK_PPC_GPOPT | OPTION_MASK_MFCRF | MASK_POWERPC64) RS6000_CPU ("titan", PROCESSOR_TITAN, OPTION_MASK_MULHW | OPTION_MASK_DLMZB) -RS6000_CPU ("power3", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64) -RS6000_CPU ("power4", PROCESSOR_POWER4, MASK_POWERPC64 | MASK_PPC_GPOPT - | MASK_PPC_GFXOPT | OPTION_MASK_MFCRF) -RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT - | MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | MASK_POPCNTB) -RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT - | MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | MASK_POPCNTB +RS6000_CPU ("power3", PROCESSOR_PPC630, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64) +RS6000_CPU ("power4", PROCESSOR_POWER4, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT + | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF) +RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT + | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB) +RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT + | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB | OPTION_MASK_FPRND) -RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT - | MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | MASK_POPCNTB +RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT + | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB | OPTION_MASK_FPRND | OPTION_MASK_CMPB | OPTION_MASK_DFP - | MASK_RECIP_PRECISION) -RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT - | MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | MASK_POPCNTB + | OPTION_MASK_RECIP_PRECISION) +RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT + | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB | OPTION_MASK_FPRND | OPTION_MASK_CMPB | OPTION_MASK_DFP - | MASK_RECIP_PRECISION) + | OPTION_MASK_RECIP_PRECISION) RS6000_CPU ("power7", PROCESSOR_POWER7, MASK_POWERPC64 | ISA_2_6_MASKS_SERVER) RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER | OPTION_MASK_HTM) RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER | OPTION_MASK_HTM) RS6000_CPU ("power10", PROCESSOR_POWER10, MASK_POWERPC64 | ISA_3_1_MASKS_SERVER) RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0) -RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64) -RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER - | OPTION_MASK_HTM) -RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64) +RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, OPTION_MASK_PPC_GFXOPT + | MASK_POWERPC64) +RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 + | ISA_2_7_MASKS_SERVER | OPTION_MASK_HTM) +RS6000_CPU ("rs64", PROCESSOR_RS64A, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 2faac05b5045..5fd30203daac 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -20727,11 +20727,12 @@ rs6000_darwin_file_start (void) const char *arg; const char *name; HOST_WIDE_INT if_set; } mapping[] = { { "ppc64", "ppc64", MASK_64BIT }, - { "970", "ppc970", MASK_PPC_GPOPT | OPTION_MASK_MFCRF | MASK_POWERPC64 }, + { "970", "ppc970", OPTION_MASK_PPC_GPOPT | OPTION_MASK_MFCRF \ + | MASK_POWERPC64 }, { "power4", "ppc970", 0 }, { "G5", "ppc970", 0 }, { "7450", "ppc7450", 0 }, { "7400", "ppc7400", OPTION_MASK_ALTIVEC }, { "G4", "ppc7400", 0 }, @@ -24060,12 +24061,12 @@ static struct rs6000_opt_mask const rs6000_builtin_mask_names[] = { "crypto", OPTION_MASK_CRYPTO, false, false }, { "htm", OPTION_MASK_HTM, false, false }, { "hard-dfp", OPTION_MASK_DFP, false, false }, { "hard-float", OPTION_MASK_SOFT_FLOAT, false, false }, { "long-double-128", OPTION_MASK_MULTIPLE, false, false }, - { "powerpc64", MASK_POWERPC64, false, false }, - { "float128", OPTION_MASK_FLOAT128_KEYWORD, false, false }, + { "powerpc64", MASK_POWERPC64, false, false }, + { "float128", OPTION_MASK_FLOAT128_KEYWORD, false, false }, { "float128-hw", OPTION_MASK_FLOAT128_HW,false, false }, { "mma", OPTION_MASK_MMA, false, false }, { "power10", OPTION_MASK_POWER10, false, false }, }; diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 4d180bd95e59..7d04556304a0 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -506,23 +506,12 @@ extern int rs6000_vector_align[]; /* In switching from using target_flags to using rs6000_isa_flags, the options machinery creates OPTION_MASK_ instead of MASK_. The MASK_ options that have not yet been replaced by their OPTION_MASK_ equivalents are defined here. */ -#define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR -#define MASK_P9_VECTOR OPTION_MASK_P9_VECTOR -#define MASK_P9_MISC OPTION_MASK_P9_MISC -#define MASK_POPCNTB OPTION_MASK_POPCNTB -#define MASK_POPCNTD OPTION_MASK_POPCNTD -#define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT -#define MASK_PPC_GPOPT OPTION_MASK_PPC_GPOPT -#define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION -#define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT + #define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN -#define MASK_VSX OPTION_MASK_VSX -#define MASK_POWER10 OPTION_MASK_POWER10 -#define MASK_P10_FUSION OPTION_MASK_P10_FUSION #ifndef IN_LIBGCC2 #define MASK_POWERPC64 OPTION_MASK_POWERPC64 #endif