From patchwork Wed Jun 1 12:42:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 1637959 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=l6S1JRZP; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4LCpjy5XGSz9s09 for ; Wed, 1 Jun 2022 22:44:06 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352993AbiFAMoE (ORCPT ); Wed, 1 Jun 2022 08:44:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55870 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353009AbiFAMoA (ORCPT ); Wed, 1 Jun 2022 08:44:00 -0400 Received: from mail-ed1-x52d.google.com (mail-ed1-x52d.google.com [IPv6:2a00:1450:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0FA4C488AA for ; Wed, 1 Jun 2022 05:43:59 -0700 (PDT) Received: by mail-ed1-x52d.google.com with SMTP id er5so1980990edb.12 for ; Wed, 01 Jun 2022 05:43:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BJBEZRlCtPIDFnVc3ujH68azfQRAs2ANl4wIkw87NgU=; b=l6S1JRZPQZFbHBkTaJh2eaATKruEQNYCb4KYgn2XH5WEGH+3lfGfmu3n/43NsCxkyT eODSQ0VHHRFsBrh6R6ffGHQzV8BAwYAySMYzVOVC7JIoDG2KoBGsw71TsMGg89P9lbtQ X9JfPhz7JTiY/1AWjDt0j8GrtTsm6lAwFPWfX4Ib++bht3IcRPhEF9nQs+aRRhNhQ7Wc FjYJaidcoG/yE1vDjBnrR7B6hgQfmiZh2oyhE4aDXQtPIyoZ1TLm1wtnu3n0O+vqf/yt l4DI4rghRvLX8pyor8eD7t1C6zD6pvU943Nlj+p5tFHquvEa/0mCrY1C54wY1fA/YC0J uc/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BJBEZRlCtPIDFnVc3ujH68azfQRAs2ANl4wIkw87NgU=; b=DvqOEm8gEsUnkmoBZltz97eTf61JvHUvT8oYiXMqt7My2aMtCx24KmMlPp+6dSpYl/ pWiUYZSysm36jI0sg09I6TQX7/U7XaL0n6lmn5Cn3VO9lwqYlW1PLfEZbKgZ4fdFOdaF pcnwYlb4KWcLJLECQbcQhLDb9L5QANfzmH3ODuwmqOhwV3jYaXGYg7nwkyPwk4AD375q F8wr6p5eikrd2wPT3OpttjT+p8S7C2Fl1ygxJ5TzniD7qw5F39aX3rRR93/435g9Px/m gEQ+598vLbRcgYrJApl5rsMU7pxguiO3MNsjX5n0WB0jbVEMEi7YqWTPIFmhCCoZqpsA IfMA== X-Gm-Message-State: AOAM531rPRZqqCdHsypoL7U1bokfHHl1x3B7TrME9mqtEJlUvMbkfvQR f3+wsj9ezR/tuMSPavd2bXmAfw== X-Google-Smtp-Source: ABdhPJwLDOPjvWMN+yEowqbZw2aBGbXb8VFgCsDAV8Sbl2c4ebkftZJqngZtf/pifKNStHJ/K5jdAA== X-Received: by 2002:a05:6402:516e:b0:42d:c48b:b724 with SMTP id d14-20020a056402516e00b0042dc48bb724mr21404495ede.93.1654087437606; Wed, 01 Jun 2022 05:43:57 -0700 (PDT) Received: from prec5560.. ([176.74.57.19]) by smtp.gmail.com with ESMTPSA id j10-20020a170906830a00b006f3ef214dc0sm682055ejx.38.2022.06.01.05.43.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Jun 2022 05:43:56 -0700 (PDT) From: Robert Foss To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzk+dt@kernel.org, robert.foss@linaro.org, jonathan@marek.ca, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Konrad Dybcio Cc: Dmitry Baryshkov Subject: [PATCH v4 3/6] dt-bindings: clock: Add Qcom SM8350 GPUCC bindings Date: Wed, 1 Jun 2022 14:42:47 +0200 Message-Id: <20220601124250.60968-4-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220601124250.60968-1-robert.foss@linaro.org> References: <20220601124250.60968-1-robert.foss@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM8350 SoCs. Signed-off-by: Robert Foss Reviewed-by: Dmitry Baryshkov --- Changes since v3 - Separate from qcom,gpucc - Remove clock-names - Make example sm8350 based - Changed author to me due to size of changes .../bindings/clock/qcom,gpucc-sm8350.yaml | 72 +++++++++++++++++++ include/dt-bindings/clock/qcom,gpucc-sm8350.h | 52 ++++++++++++++ 2 files changed, 124 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml create mode 100644 include/dt-bindings/clock/qcom,gpucc-sm8350.h diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml new file mode 100644 index 000000000000..0a0546c079a9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gpucc-sm8350.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller Binding + +maintainers: + - Robert Foss + +description: | + Qualcomm graphics clock control module which supports the clocks, resets and + power domains on Qualcomm SoCs. + + See also: + dt-bindings/clock/qcom,gpucc-sm8350.h + +properties: + compatible: + enum: + - qcom,sm8350-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 div branch source + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@3d90000 { + compatible = "qcom,sm8350-gpucc"; + reg = <0 0x03d90000 0 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/include/dt-bindings/clock/qcom,gpucc-sm8350.h b/include/dt-bindings/clock/qcom,gpucc-sm8350.h new file mode 100644 index 000000000000..d2294e0d527e --- /dev/null +++ b/include/dt-bindings/clock/qcom,gpucc-sm8350.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CB_CLK 1 +#define GPU_CC_CRC_AHB_CLK 2 +#define GPU_CC_CX_APB_CLK 3 +#define GPU_CC_CX_GMU_CLK 4 +#define GPU_CC_CX_QDSS_AT_CLK 5 +#define GPU_CC_CX_QDSS_TRIG_CLK 6 +#define GPU_CC_CX_QDSS_TSCTR_CLK 7 +#define GPU_CC_CX_SNOC_DVM_CLK 8 +#define GPU_CC_CXO_AON_CLK 9 +#define GPU_CC_CXO_CLK 10 +#define GPU_CC_FREQ_MEASURE_CLK 11 +#define GPU_CC_GMU_CLK_SRC 12 +#define GPU_CC_GX_GMU_CLK 13 +#define GPU_CC_GX_QDSS_TSCTR_CLK 14 +#define GPU_CC_GX_VSENSE_CLK 15 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 16 +#define GPU_CC_HUB_AHB_DIV_CLK_SRC 17 +#define GPU_CC_HUB_AON_CLK 18 +#define GPU_CC_HUB_CLK_SRC 19 +#define GPU_CC_HUB_CX_INT_CLK 20 +#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 21 +#define GPU_CC_MND1X_0_GFX3D_CLK 22 +#define GPU_CC_MND1X_1_GFX3D_CLK 23 +#define GPU_CC_PLL0 24 +#define GPU_CC_PLL1 25 +#define GPU_CC_SLEEP_CLK 26 + +/* GPU_CC resets */ +#define GPUCC_GPU_CC_ACD_BCR 0 +#define GPUCC_GPU_CC_CB_BCR 1 +#define GPUCC_GPU_CC_CX_BCR 2 +#define GPUCC_GPU_CC_FAST_HUB_BCR 3 +#define GPUCC_GPU_CC_GFX3D_AON_BCR 4 +#define GPUCC_GPU_CC_GMU_BCR 5 +#define GPUCC_GPU_CC_GX_BCR 6 +#define GPUCC_GPU_CC_XO_BCR 7 + +/* GPU_CC GDSCRs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif From patchwork Wed Jun 1 12:42:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 1637960 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=EO+94TNU; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4LCpkG5nM8z9s09 for ; Wed, 1 Jun 2022 22:44:22 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353056AbiFAMoU (ORCPT ); Wed, 1 Jun 2022 08:44:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56370 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352976AbiFAMoT (ORCPT ); Wed, 1 Jun 2022 08:44:19 -0400 Received: from mail-ed1-x535.google.com (mail-ed1-x535.google.com [IPv6:2a00:1450:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F0CA25003E for ; Wed, 1 Jun 2022 05:44:17 -0700 (PDT) Received: by mail-ed1-x535.google.com with SMTP id w27so2006869edl.7 for ; Wed, 01 Jun 2022 05:44:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=NmrsNTC7U91tg8YsVhHhgXCDiOGXL6aN8PsJdwtecxo=; b=EO+94TNUS90lHTob+AzkHTeeAsGZcsN5zZMorptL8RgqLoUVkAARnBcEgpU5FXMfCI /3ZqUv7sxt5TCdOAkUmEuwqK4LiKNCTx0W47t8qnkvKD/iDfxxKtUZYdOpszMOKE87x9 2HgO8anSDPEOODFfDzyzuxjcqPeUvJ5JwVd/OtHBNPMYbI4YkrIzU4LIGfZpBxhu8U0P MjWUoKsj0wYGy84XUZu/yhqeIPMzYOO60FIqRfcBoJ1Vjm/dpDOtxDsalqWJE+E1IXJ5 w8cLtNKTUbekC1VrPDmaRfCu41kXEwVR7SBhcF+7spT9zpUwH5j1STrp1kHNnxWcyDIS ZQXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NmrsNTC7U91tg8YsVhHhgXCDiOGXL6aN8PsJdwtecxo=; b=COOu8RN0zxBZWf/ycmRFhq6V/qSzoP0b/k8cNFp7nLyqr8JKc+/1Ds8uq5+Mz4dy9n QyPRRwkR4tmxBTSLXG8t7XtiFVQowCZSpKrcY0vMZTP1CopFTSv3MnJ2TBhg+XQMuaO6 nBpEPOuZzHYJZYyNw91nON5nr7/EtFoZcF9xHWR/4fkigbr3ciqLVK8G6u/uX6y4hHnY guyM8IMiALThfZtHryLFkTh7ZnKtpKoQTcyZbOHqTJ/8kJZdQjlNrbtwsm92hFwdKcvo sY2V0IKugBtgq0E8SE85ASansHaE4yaceKzfQ7xnsy0vL09LNqR+qaIissm8UzJ2+Lch RFkA== X-Gm-Message-State: AOAM5311AsTbSiU9LqKEuJrgFh6+eO4Lao9DjH8e6711ccKaNtBNJ8jU sE24Oh9+NSGphY3cVxC/Hb9zeA== X-Google-Smtp-Source: ABdhPJwaCweUu5jrm6eOCYIhs9upUUwSOtGI5bUWI4ShD8mRi06VAfR10j1ntSKF5a1Tv4fdJr5mqg== X-Received: by 2002:a05:6402:3812:b0:42a:a0dc:562c with SMTP id es18-20020a056402381200b0042aa0dc562cmr70062602edb.205.1654087456525; Wed, 01 Jun 2022 05:44:16 -0700 (PDT) Received: from prec5560.. ([176.74.57.19]) by smtp.gmail.com with ESMTPSA id j10-20020a170906830a00b006f3ef214dc0sm682055ejx.38.2022.06.01.05.44.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Jun 2022 05:44:16 -0700 (PDT) From: Robert Foss To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzk+dt@kernel.org, robert.foss@linaro.org, jonathan@marek.ca, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Konrad Dybcio Subject: [PATCH v4 5/6] dt-bindings: clock: Add Qcom SM8350 DISPCC bindings Date: Wed, 1 Jun 2022 14:42:49 +0200 Message-Id: <20220601124250.60968-6-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220601124250.60968-1-robert.foss@linaro.org> References: <20220601124250.60968-1-robert.foss@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add sm8350 DISPCC bindings, while these bindings are similar to the sm8x50 bindings, the way clocks are represented has changed in ABI incompatible ways. Signed-off-by: Robert Foss Reviewed-by: Rob Herring --- hanges since v2 - Add my SoB - Bjorn Changes since v3 - Separate from qcom,dispcc-sm8x50 - Remove clock-names - Make example sm8350 based - Changed author to me due to size of changes .../bindings/clock/qcom,dispcc-sm8350.yaml | 104 ++++++++++++++++++ .../bindings/clock/qcom,dispcc-sm8x50.yaml | 4 +- .../dt-bindings/clock/qcom,dispcc-sm8350.h | 1 + 3 files changed, 107 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/qcom,dispcc-sm8350.yaml create mode 120000 include/dt-bindings/clock/qcom,dispcc-sm8350.h diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8350.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8350.yaml new file mode 100644 index 000000000000..d7e8739cab32 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8350.yaml @@ -0,0 +1,104 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8350.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display Clock & Reset Controller Binding for SM8350 + +maintainers: + - Robert Foss + +description: | + Qualcomm display clock control module which supports the clocks, resets and + power domains on SM8350. + + See also: + dt-bindings/clock/qcom,dispcc-sm8350.h + +properties: + compatible: + enum: + - qcom,sm8350-dispcc + + clocks: + items: + - description: Board XO source + - description: Link clock from DP PHY + - description: VCO DIV clock from DP PHY + - description: Link clock from DPTX1 PHY + - description: VCO DIV clock from DPTX1 PHY + - description: Link clock from DPTX2 PHY + - description: VCO DIV clock from DPTX2 PHY + - description: Byte clock from DSI PHY0 + - description: Pixel clock from DSI PHY0 + - description: Byte clock from DSI PHY1 + - description: Pixel clock from DSI PHY1 + - description: Link clock from EDP PHY + - description: VCO DIV clock from EDP PHY + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + + power-domains: + description: + A phandle and PM domain specifier for the MMCX power domain. + maxItems: 1 + + required-opps: + description: + A phandle to an OPP node describing required MMCX performance point. + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + #include + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@af00000 { + compatible = "qcom,sm8350-dispcc"; + reg = <0 0x0af00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&dp_phy 0>, + <&dp_phy 1>, + <&dptx1_phy 0>, + <&dptx1_phy 1>, + <&dptx2_phy 0>, + <&dptx2_phy 1>, + <&dsi0_phy 0>, + <&dsi0_phy 1>, + <&dsi1_phy 0>, + <&dsi1_phy 1>, + <&edp_phy 0>, + <&edp_phy 1>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + power-domains = <&rpmhpd SM8350_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml index 31497677e8de..951fe2ecb7a6 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml @@ -4,14 +4,14 @@ $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250 +title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250/SM8350 maintainers: - Jonathan Marek description: | Qualcomm display clock control module which supports the clocks, resets and - power domains on SM8150 and SM8250. + power domains on SM8150/SM8250. See also: dt-bindings/clock/qcom,dispcc-sm8150.h diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8350.h b/include/dt-bindings/clock/qcom,dispcc-sm8350.h new file mode 120000 index 000000000000..0312b4544acb --- /dev/null +++ b/include/dt-bindings/clock/qcom,dispcc-sm8350.h @@ -0,0 +1 @@ +qcom,dispcc-sm8250.h \ No newline at end of file