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[125.228.123.29]) by smtp.gmail.com with ESMTPSA id u11-20020a63d34b000000b003c14af505f6sm290749pgi.14.2022.05.31.21.17.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 May 2022 21:17:45 -0700 (PDT) From: Potin Lai To: Brendan Higgins , Benjamin Herrenschmidt , Joel Stanley , Andrew Jeffery , Rob Herring , Rayn Chen Subject: [PATCH v2 1/2] aspeed: i2c: add manual clock setting feature Date: Wed, 1 Jun 2022 12:15:11 +0800 Message-Id: <20220601041512.21484-2-potin.lai.pt@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220601041512.21484-1-potin.lai.pt@gmail.com> References: <20220601041512.21484-1-potin.lai.pt@gmail.com> X-BeenThere: linux-aspeed@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux ASPEED SoC development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-aspeed@lists.ozlabs.org, Potin Lai , linux-kernel@vger.kernel.org, Potin Lai , Patrick Williams , linux-i2c@vger.kernel.org, linux-arm-kernel@lists.infradead.org Errors-To: linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linux-aspeed" Add manual tuning i2c clock timing register support by reading following properties. * aspeed,i2c-manual-clk: Enable aspeed i2c clock manual setting * aspeed,i2c-base-clk-div: Base Clock divisor (tBaseClk) * aspeed,i2c-clk-high-cycle: Cycles of clock-high pulse (tClkHigh) * aspeed,i2c-clk-low-cycle: Cycles of clock-low pulse (tClkLow) Signed-off-by: Potin Lai --- drivers/i2c/busses/i2c-aspeed.c | 57 ++++++++++++++++++++++++++++++++- 1 file changed, 56 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-aspeed.c b/drivers/i2c/busses/i2c-aspeed.c index 67e8b97c0c95..64424f377f27 100644 --- a/drivers/i2c/busses/i2c-aspeed.c +++ b/drivers/i2c/busses/i2c-aspeed.c @@ -60,6 +60,7 @@ #define ASPEED_I2CD_TIME_SCL_LOW_MASK GENMASK(15, 12) #define ASPEED_I2CD_TIME_BASE_DIVISOR_MASK GENMASK(3, 0) #define ASPEED_I2CD_TIME_SCL_REG_MAX GENMASK(3, 0) +#define ASPEED_I2CD_TIME_BASE_DIVISOR_MAX 32768 /* 0x08 : I2CD Clock and AC Timing Control Register #2 */ #define ASPEED_NO_TIMEOUT_CTRL 0 @@ -898,6 +899,57 @@ static int aspeed_i2c_init_clk(struct aspeed_i2c_bus *bus) return 0; } +/* precondition: bus.lock has been acquired. */ +static int aspeed_i2c_manual_clk_setup(struct aspeed_i2c_bus *bus) +{ + u32 divisor, clk_high, clk_low, clk_reg_val; + + if (device_property_read_u32(bus->dev, "aspeed,i2c-base-clk-div", + &divisor) != 0) { + dev_err(bus->dev, "Could not read aspeed,i2c-base-clk-div\n"); + return -EINVAL; + } else if (!divisor || divisor > ASPEED_I2CD_TIME_BASE_DIVISOR_MAX || + BIT(__fls(divisor)) != divisor) { + dev_err(bus->dev, "Invalid aspeed,i2c-base-clk-div: %u\n", + divisor); + return -EINVAL; + } + + if (device_property_read_u32(bus->dev, "aspeed,i2c-clk-high-cycle", + &clk_high) != 0) { + dev_err(bus->dev, "Could not read aspeed,i2c-clk-high-cycle\n"); + return -EINVAL; + } else if ((clk_high-1) > ASPEED_I2CD_TIME_SCL_REG_MAX) { + dev_err(bus->dev, "Invalid aspeed,i2c-clk-high-cycle: %u\n", + clk_high); + return -EINVAL; + } + + if (device_property_read_u32(bus->dev, "aspeed,i2c-clk-low-cycle", + &clk_low) != 0) { + dev_err(bus->dev, "Could not read aspeed,i2c-clk-low-cycle\n"); + return -EINVAL; + } else if ((clk_low-1) > ASPEED_I2CD_TIME_SCL_REG_MAX) { + dev_err(bus->dev, "Invalid aspeed,i2c-clk-low-cycle: %u\n", + clk_low); + return -EINVAL; + } + + clk_reg_val = readl(bus->base + ASPEED_I2C_AC_TIMING_REG1); + clk_reg_val &= (ASPEED_I2CD_TIME_TBUF_MASK | + ASPEED_I2CD_TIME_THDSTA_MASK | + ASPEED_I2CD_TIME_TACST_MASK); + clk_reg_val |= (ilog2(divisor) & ASPEED_I2CD_TIME_BASE_DIVISOR_MASK) + | (((clk_high-1) << ASPEED_I2CD_TIME_SCL_HIGH_SHIFT) + & ASPEED_I2CD_TIME_SCL_HIGH_MASK) + | (((clk_low-1) << ASPEED_I2CD_TIME_SCL_LOW_SHIFT) + & ASPEED_I2CD_TIME_SCL_LOW_MASK); + writel(clk_reg_val, bus->base + ASPEED_I2C_AC_TIMING_REG1); + writel(ASPEED_NO_TIMEOUT_CTRL, bus->base + ASPEED_I2C_AC_TIMING_REG2); + + return 0; +} + /* precondition: bus.lock has been acquired. */ static int aspeed_i2c_init(struct aspeed_i2c_bus *bus, struct platform_device *pdev) @@ -908,7 +960,10 @@ static int aspeed_i2c_init(struct aspeed_i2c_bus *bus, /* Disable everything. */ writel(0, bus->base + ASPEED_I2C_FUN_CTRL_REG); - ret = aspeed_i2c_init_clk(bus); + if (of_property_read_bool(pdev->dev.of_node, "aspeed,i2c-manual-clk")) + ret = aspeed_i2c_manual_clk_setup(bus); + else + ret = aspeed_i2c_init_clk(bus); if (ret < 0) return ret; From patchwork Wed Jun 1 04:15:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Potin Lai X-Patchwork-Id: 1637735 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=cz3+YUGh; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LCbTx2mkrz9s5V for ; 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[125.228.123.29]) by smtp.gmail.com with ESMTPSA id u11-20020a63d34b000000b003c14af505f6sm290749pgi.14.2022.05.31.21.17.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 May 2022 21:17:47 -0700 (PDT) From: Potin Lai To: Brendan Higgins , Benjamin Herrenschmidt , Joel Stanley , Andrew Jeffery , Rob Herring , Rayn Chen Subject: [PATCH v2 2/2] dt-bindings: aspeed-i2c: add properties for manual clock setting Date: Wed, 1 Jun 2022 12:15:12 +0800 Message-Id: <20220601041512.21484-3-potin.lai.pt@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220601041512.21484-1-potin.lai.pt@gmail.com> References: <20220601041512.21484-1-potin.lai.pt@gmail.com> X-BeenThere: linux-aspeed@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux ASPEED SoC development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-aspeed@lists.ozlabs.org, Potin Lai , linux-kernel@vger.kernel.org, Potin Lai , Patrick Williams , linux-i2c@vger.kernel.org, linux-arm-kernel@lists.infradead.org Errors-To: linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linux-aspeed" Add following properties for manual tuning clock divisor and cycle of hign/low pulse witdh. * aspeed,i2c-manual-clk: Enable aspeed i2c clock manual setting * aspeed,i2c-base-clk-div: Base Clock divisor (tBaseClk) * aspeed,i2c-clk-high-cycle: Cycles of clock-high pulse (tClkHigh) * aspeed,i2c-clk-low-cycle: Cycles of clock-low pulse (tClkLow) Signed-off-by: Potin Lai --- .../devicetree/bindings/i2c/aspeed,i2c.yaml | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml b/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml index ea643e6c3ef5..e2f67fe2aa0c 100644 --- a/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml @@ -12,6 +12,28 @@ maintainers: allOf: - $ref: /schemas/i2c/i2c-controller.yaml# + - if: + properties: + compatible: + const: st,stm32-uart + + then: + properties: + aspeed,i2c-clk-high-cycle: + maximum: 8 + aspeed,i2c-clk-low-cycle: + maximum: 8 + + - if: + required: + - aspeed,i2c-manual-clk + + then: + required: + - aspeed,i2c-base-clk-div + - aspeed,i2c-clk-high-cycle + - aspeed,i2c-clk-low-cycle + properties: compatible: enum: @@ -49,6 +71,28 @@ properties: description: states that there is another master active on this bus + aspeed,i2c-manual-clk: + type: boolean + description: enable manual clock setting + + aspeed,i2c-base-clk-div: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, + 16384, 32768] + description: base clock divisor + + aspeed,i2c-clk-high-cycle: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 16 + description: cycles of master clock-high pulse width + + aspeed,i2c-clk-low-cycle: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 16 + description: cycles of master clock-low pulse width + required: - reg - compatible