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[220.133.130.217]) by smtp.gmail.com with ESMTPSA id q14-20020a17090a178e00b001df3a251cc2sm322188pja.4.2022.05.24.20.24.17 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 24 May 2022 20:24:17 -0700 (PDT) From: Tyrone Ting To: avifishman70@gmail.com, tmaimon77@gmail.com, tali.perry1@gmail.com, venture@google.com, yuenn@google.com, benjaminfair@google.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, wsa@kernel.org, andriy.shevchenko@linux.intel.com, jarkko.nikula@linux.intel.com, semen.protsenko@linaro.org, jie.deng@intel.com, jsd@semihalf.com, sven@svenpeter.dev, lukas.bulwahn@gmail.com, olof@lixom.net, arnd@arndb.de, warp5tw@gmail.com, tali.perry@nuvoton.com, Avi.Fishman@nuvoton.com, tomer.maimon@nuvoton.com, KWLIU@nuvoton.com, JJLIU0@nuvoton.com, kfting@nuvoton.com Subject: [PATCH v6 1/5] dt-bindings: i2c: npcm: support NPCM845 Date: Wed, 25 May 2022 11:23:37 +0800 Message-Id: <20220525032341.3182-2-warp5tw@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220525032341.3182-1-warp5tw@gmail.com> References: <20220525032341.3182-1-warp5tw@gmail.com> X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, openbmc@lists.ozlabs.org, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" From: Tyrone Ting Add compatible and nuvoton,sys-mgr description for NPCM i2c module. Signed-off-by: Tyrone Ting Reviewed-by: Krzysztof Kozlowski Reviewed-by: Rob Herring --- .../bindings/i2c/nuvoton,npcm7xx-i2c.yaml | 25 +++++++++++++++---- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/i2c/nuvoton,npcm7xx-i2c.yaml b/Documentation/devicetree/bindings/i2c/nuvoton,npcm7xx-i2c.yaml index 128444942aec..09d2591e1fa3 100644 --- a/Documentation/devicetree/bindings/i2c/nuvoton,npcm7xx-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/nuvoton,npcm7xx-i2c.yaml @@ -7,17 +7,18 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: nuvoton NPCM7XX I2C Controller Device Tree Bindings description: | - The NPCM750x includes sixteen I2C bus controllers. All Controllers support - both master and slave mode. Each controller can switch between master and slave - at run time (i.e. IPMB mode). Each controller has two 16 byte HW FIFO for TX and - RX. + I2C bus controllers of the NPCM series support both master and + slave mode. Each controller can switch between master and slave at run time + (i.e. IPMB mode). HW FIFO for TX and RX are supported. maintainers: - Tali Perry properties: compatible: - const: nuvoton,npcm750-i2c + enum: + - nuvoton,npcm750-i2c + - nuvoton,npcm845-i2c reg: maxItems: 1 @@ -36,6 +37,10 @@ properties: default: 100000 enum: [100000, 400000, 1000000] + nuvoton,sys-mgr: + $ref: /schemas/types.yaml#/definitions/phandle + description: The phandle of system manager register node. + required: - compatible - reg @@ -44,6 +49,15 @@ required: allOf: - $ref: /schemas/i2c/i2c-controller.yaml# + - if: + properties: + compatible: + contains: + const: nuvoton,npcm845-i2c + + then: + required: + - nuvoton,sys-mgr unevaluatedProperties: false @@ -57,6 +71,7 @@ examples: clock-frequency = <100000>; interrupts = ; compatible = "nuvoton,npcm750-i2c"; + nuvoton,sys-mgr = <&gcr>; }; ... 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[220.133.130.217]) by smtp.gmail.com with ESMTPSA id gx3-20020a17090b124300b001df6ccdf3f6sm461772pjb.47.2022.05.24.20.24.19 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 24 May 2022 20:24:19 -0700 (PDT) From: Tyrone Ting To: avifishman70@gmail.com, tmaimon77@gmail.com, tali.perry1@gmail.com, venture@google.com, yuenn@google.com, benjaminfair@google.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, wsa@kernel.org, andriy.shevchenko@linux.intel.com, jarkko.nikula@linux.intel.com, semen.protsenko@linaro.org, jie.deng@intel.com, jsd@semihalf.com, sven@svenpeter.dev, lukas.bulwahn@gmail.com, olof@lixom.net, arnd@arndb.de, warp5tw@gmail.com, tali.perry@nuvoton.com, Avi.Fishman@nuvoton.com, tomer.maimon@nuvoton.com, KWLIU@nuvoton.com, JJLIU0@nuvoton.com, kfting@nuvoton.com Subject: [PATCH v6 2/5] i2c: npcm: Remove own slave addresses 2:10 Date: Wed, 25 May 2022 11:23:38 +0800 Message-Id: <20220525032341.3182-3-warp5tw@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220525032341.3182-1-warp5tw@gmail.com> References: <20220525032341.3182-1-warp5tw@gmail.com> X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, openbmc@lists.ozlabs.org, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" From: Tali Perry NPCM can support up to 10 own slave addresses. In practice, only one address is actually being used. In order to access addresses 2 and above, need to switch register banks. The switch needs spinlock. To avoid using spinlock for this useless feature removed support of SA >= 2. Also fix returned slave event enum. Remove some comment since the bank selection is not required. The bank selection is not required since the supported slave addresses are reduced. Fixes: 56a1485b102e ("i2c: npcm7xx: Add Nuvoton NPCM I2C controller driver") Signed-off-by: Tali Perry Signed-off-by: Tyrone Ting --- drivers/i2c/busses/i2c-npcm7xx.c | 41 +++++++++++++------------------- 1 file changed, 16 insertions(+), 25 deletions(-) diff --git a/drivers/i2c/busses/i2c-npcm7xx.c b/drivers/i2c/busses/i2c-npcm7xx.c index 5960ccde6574..b5cc83e51029 100644 --- a/drivers/i2c/busses/i2c-npcm7xx.c +++ b/drivers/i2c/busses/i2c-npcm7xx.c @@ -123,11 +123,11 @@ enum i2c_addr { * Since the addr regs are sprinkled all over the address space, * use this array to get the address or each register. */ -#define I2C_NUM_OWN_ADDR 10 +#define I2C_NUM_OWN_ADDR 2 +#define I2C_NUM_OWN_ADDR_SUPPORTED 2 + static const int npcm_i2caddr[I2C_NUM_OWN_ADDR] = { - NPCM_I2CADDR1, NPCM_I2CADDR2, NPCM_I2CADDR3, NPCM_I2CADDR4, - NPCM_I2CADDR5, NPCM_I2CADDR6, NPCM_I2CADDR7, NPCM_I2CADDR8, - NPCM_I2CADDR9, NPCM_I2CADDR10, + NPCM_I2CADDR1, NPCM_I2CADDR2, }; #endif @@ -392,14 +392,10 @@ static void npcm_i2c_disable(struct npcm_i2c *bus) #if IS_ENABLED(CONFIG_I2C_SLAVE) int i; - /* select bank 0 for I2C addresses */ - npcm_i2c_select_bank(bus, I2C_BANK_0); - /* Slave addresses removal */ - for (i = I2C_SLAVE_ADDR1; i < I2C_NUM_OWN_ADDR; i++) + for (i = I2C_SLAVE_ADDR1; i < I2C_NUM_OWN_ADDR_SUPPORTED; i++) iowrite8(0, bus->reg + npcm_i2caddr[i]); - npcm_i2c_select_bank(bus, I2C_BANK_1); #endif /* Disable module */ i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2); @@ -604,8 +600,7 @@ static int npcm_i2c_slave_enable(struct npcm_i2c *bus, enum i2c_addr addr_type, i2cctl1 &= ~NPCM_I2CCTL1_GCMEN; iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1); return 0; - } - if (addr_type == I2C_ARP_ADDR) { + } else if (addr_type == I2C_ARP_ADDR) { i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3); if (enable) i2cctl3 |= I2CCTL3_ARPMEN; @@ -614,16 +609,16 @@ static int npcm_i2c_slave_enable(struct npcm_i2c *bus, enum i2c_addr addr_type, iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3); return 0; } + if (addr_type > I2C_SLAVE_ADDR2 && addr_type <= I2C_SLAVE_ADDR10) + dev_err(bus->dev, "try to enable more than 2 SA not supported\n"); + if (addr_type >= I2C_ARP_ADDR) return -EFAULT; - /* select bank 0 for address 3 to 10 */ - if (addr_type > I2C_SLAVE_ADDR2) - npcm_i2c_select_bank(bus, I2C_BANK_0); + /* Set and enable the address */ iowrite8(sa_reg, bus->reg + npcm_i2caddr[addr_type]); npcm_i2c_slave_int_enable(bus, enable); - if (addr_type > I2C_SLAVE_ADDR2) - npcm_i2c_select_bank(bus, I2C_BANK_1); + return 0; } #endif @@ -846,15 +841,11 @@ static u8 npcm_i2c_get_slave_addr(struct npcm_i2c *bus, enum i2c_addr addr_type) { u8 slave_add; - /* select bank 0 for address 3 to 10 */ - if (addr_type > I2C_SLAVE_ADDR2) - npcm_i2c_select_bank(bus, I2C_BANK_0); + if (addr_type > I2C_SLAVE_ADDR2 && addr_type <= I2C_SLAVE_ADDR10) + dev_err(bus->dev, "get slave: try to use more than 2 SA not supported\n"); slave_add = ioread8(bus->reg + npcm_i2caddr[(int)addr_type]); - if (addr_type > I2C_SLAVE_ADDR2) - npcm_i2c_select_bank(bus, I2C_BANK_1); - return slave_add; } @@ -864,12 +855,12 @@ static int npcm_i2c_remove_slave_addr(struct npcm_i2c *bus, u8 slave_add) /* Set the enable bit */ slave_add |= 0x80; - npcm_i2c_select_bank(bus, I2C_BANK_0); - for (i = I2C_SLAVE_ADDR1; i < I2C_NUM_OWN_ADDR; i++) { + + for (i = I2C_SLAVE_ADDR1; i < I2C_NUM_OWN_ADDR_SUPPORTED; i++) { if (ioread8(bus->reg + npcm_i2caddr[i]) == slave_add) iowrite8(0, bus->reg + npcm_i2caddr[i]); } - npcm_i2c_select_bank(bus, I2C_BANK_1); + return 0; } From patchwork Wed May 25 03:23:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tyrone Ting X-Patchwork-Id: 1635269 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=jKuli6//; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; 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[220.133.130.217]) by smtp.gmail.com with ESMTPSA id c21-20020a62e815000000b00518e3256022sm711553pfi.104.2022.05.24.20.24.21 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 24 May 2022 20:24:21 -0700 (PDT) From: Tyrone Ting To: avifishman70@gmail.com, tmaimon77@gmail.com, tali.perry1@gmail.com, venture@google.com, yuenn@google.com, benjaminfair@google.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, wsa@kernel.org, andriy.shevchenko@linux.intel.com, jarkko.nikula@linux.intel.com, semen.protsenko@linaro.org, jie.deng@intel.com, jsd@semihalf.com, sven@svenpeter.dev, lukas.bulwahn@gmail.com, olof@lixom.net, arnd@arndb.de, warp5tw@gmail.com, tali.perry@nuvoton.com, Avi.Fishman@nuvoton.com, tomer.maimon@nuvoton.com, KWLIU@nuvoton.com, JJLIU0@nuvoton.com, kfting@nuvoton.com Subject: [PATCH v6 3/5] i2c: npcm: Correct slave role behavior Date: Wed, 25 May 2022 11:23:39 +0800 Message-Id: <20220525032341.3182-4-warp5tw@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220525032341.3182-1-warp5tw@gmail.com> References: <20220525032341.3182-1-warp5tw@gmail.com> X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, openbmc@lists.ozlabs.org, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" From: Tali Perry Correct the slave transaction logic to be compatible with the generic slave backend driver. Fixes: 56a1485b102e ("i2c: npcm7xx: Add Nuvoton NPCM I2C controller driver") Signed-off-by: Tali Perry Signed-off-by: Tyrone Ting --- drivers/i2c/busses/i2c-npcm7xx.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/i2c/busses/i2c-npcm7xx.c b/drivers/i2c/busses/i2c-npcm7xx.c index b5cc83e51029..b4d218c6c8fb 100644 --- a/drivers/i2c/busses/i2c-npcm7xx.c +++ b/drivers/i2c/busses/i2c-npcm7xx.c @@ -915,11 +915,15 @@ static int npcm_i2c_slave_get_wr_buf(struct npcm_i2c *bus) for (i = 0; i < I2C_HW_FIFO_SIZE; i++) { if (bus->slv_wr_size >= I2C_HW_FIFO_SIZE) break; - i2c_slave_event(bus->slave, I2C_SLAVE_READ_REQUESTED, &value); + if (bus->state == I2C_SLAVE_MATCH) { + i2c_slave_event(bus->slave, I2C_SLAVE_READ_REQUESTED, &value); + bus->state = I2C_OPER_STARTED; + } else { + i2c_slave_event(bus->slave, I2C_SLAVE_READ_PROCESSED, &value); + } ind = (bus->slv_wr_ind + bus->slv_wr_size) % I2C_HW_FIFO_SIZE; bus->slv_wr_buf[ind] = value; bus->slv_wr_size++; - i2c_slave_event(bus->slave, I2C_SLAVE_READ_PROCESSED, &value); } return I2C_HW_FIFO_SIZE - ret; } @@ -967,7 +971,6 @@ static void npcm_i2c_slave_xmit(struct npcm_i2c *bus, u16 nwrite, if (nwrite == 0) return; - bus->state = I2C_OPER_STARTED; bus->operation = I2C_WRITE_OPER; /* get the next buffer */ From patchwork Wed May 25 03:23:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tyrone Ting X-Patchwork-Id: 1635270 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=j8wx++BG; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4L7GhJ5rTQz9sGl for ; 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[220.133.130.217]) by smtp.gmail.com with ESMTPSA id br19-20020a17090b0f1300b001d954837197sm306541pjb.22.2022.05.24.20.24.23 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 24 May 2022 20:24:23 -0700 (PDT) From: Tyrone Ting To: avifishman70@gmail.com, tmaimon77@gmail.com, tali.perry1@gmail.com, venture@google.com, yuenn@google.com, benjaminfair@google.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, wsa@kernel.org, andriy.shevchenko@linux.intel.com, jarkko.nikula@linux.intel.com, semen.protsenko@linaro.org, jie.deng@intel.com, jsd@semihalf.com, sven@svenpeter.dev, lukas.bulwahn@gmail.com, olof@lixom.net, arnd@arndb.de, warp5tw@gmail.com, tali.perry@nuvoton.com, Avi.Fishman@nuvoton.com, tomer.maimon@nuvoton.com, KWLIU@nuvoton.com, JJLIU0@nuvoton.com, kfting@nuvoton.com Subject: [PATCH v6 4/5] i2c: npcm: Support NPCM845 Date: Wed, 25 May 2022 11:23:40 +0800 Message-Id: <20220525032341.3182-5-warp5tw@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220525032341.3182-1-warp5tw@gmail.com> References: <20220525032341.3182-1-warp5tw@gmail.com> X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, openbmc@lists.ozlabs.org, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" From: Tyrone Ting Add NPCM8XX I2C support. The NPCM8XX uses a similar i2c module as NPCM7XX. The internal HW FIFO is larger in NPCM8XX. Signed-off-by: Tyrone Ting Acked-by: Tomer Maimon --- drivers/i2c/busses/Kconfig | 8 +-- drivers/i2c/busses/Makefile | 2 +- drivers/i2c/busses/i2c-npcm7xx.c | 114 +++++++++++++++++++------------ 3 files changed, 76 insertions(+), 48 deletions(-) diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index a1bae59208e3..b1d7069dd377 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -838,13 +838,13 @@ config I2C_NOMADIK I2C interface from ST-Ericsson's Nomadik and Ux500 architectures, as well as the STA2X11 PCIe I/O HUB. -config I2C_NPCM7XX +config I2C_NPCM tristate "Nuvoton I2C Controller" - depends on ARCH_NPCM7XX || COMPILE_TEST + depends on ARCH_NPCM || COMPILE_TEST help If you say yes to this option, support will be included for the - Nuvoton I2C controller, which is available on the NPCM7xx BMC - controller. + Nuvoton I2C controller, which is available on the NPCM BMC + controllers. Driver can also support slave mode (select I2C_SLAVE). config I2C_OCORES diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index 479f60e4ee3d..b0a10e5d9ee9 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -84,7 +84,7 @@ obj-$(CONFIG_I2C_MT7621) += i2c-mt7621.o obj-$(CONFIG_I2C_MV64XXX) += i2c-mv64xxx.o obj-$(CONFIG_I2C_MXS) += i2c-mxs.o obj-$(CONFIG_I2C_NOMADIK) += i2c-nomadik.o -obj-$(CONFIG_I2C_NPCM7XX) += i2c-npcm7xx.o +obj-$(CONFIG_I2C_NPCM) += i2c-npcm7xx.o obj-$(CONFIG_I2C_OCORES) += i2c-ocores.o obj-$(CONFIG_I2C_OMAP) += i2c-omap.o obj-$(CONFIG_I2C_OWL) += i2c-owl.o diff --git a/drivers/i2c/busses/i2c-npcm7xx.c b/drivers/i2c/busses/i2c-npcm7xx.c index b4d218c6c8fb..86fd942ea648 100644 --- a/drivers/i2c/busses/i2c-npcm7xx.c +++ b/drivers/i2c/busses/i2c-npcm7xx.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -91,7 +92,6 @@ enum i2c_addr { /* init register and default value required to enable module */ #define NPCM_I2CSEGCTL 0xE4 -#define NPCM_I2CSEGCTL_INIT_VAL 0x0333F000 /* Common regs */ #define NPCM_I2CSDA 0x00 @@ -226,8 +226,7 @@ static const int npcm_i2caddr[I2C_NUM_OWN_ADDR] = { #define NPCM_I2CFIF_CTS_CLR_FIFO BIT(6) #define NPCM_I2CFIF_CTS_SLVRSTR BIT(7) -/* NPCM_I2CTXF_CTL reg fields */ -#define NPCM_I2CTXF_CTL_TX_THR GENMASK(4, 0) +/* NPCM_I2CTXF_CTL reg field */ #define NPCM_I2CTXF_CTL_THR_TXIE BIT(6) /* NPCM_I2CT_OUT reg fields */ @@ -236,22 +235,18 @@ static const int npcm_i2caddr[I2C_NUM_OWN_ADDR] = { #define NPCM_I2CT_OUT_T_OUTST BIT(7) /* NPCM_I2CTXF_STS reg fields */ -#define NPCM_I2CTXF_STS_TX_BYTES GENMASK(4, 0) #define NPCM_I2CTXF_STS_TX_THST BIT(6) /* NPCM_I2CRXF_STS reg fields */ -#define NPCM_I2CRXF_STS_RX_BYTES GENMASK(4, 0) #define NPCM_I2CRXF_STS_RX_THST BIT(6) /* NPCM_I2CFIF_CTL reg fields */ #define NPCM_I2CFIF_CTL_FIFO_EN BIT(4) /* NPCM_I2CRXF_CTL reg fields */ -#define NPCM_I2CRXF_CTL_RX_THR GENMASK(4, 0) -#define NPCM_I2CRXF_CTL_LAST_PEC BIT(5) #define NPCM_I2CRXF_CTL_THR_RXIE BIT(6) -#define I2C_HW_FIFO_SIZE 16 +#define MAX_I2C_HW_FIFO_SIZE 32 /* I2C_VER reg fields */ #define I2C_VER_VERSION GENMASK(6, 0) @@ -268,11 +263,36 @@ static const int npcm_i2caddr[I2C_NUM_OWN_ADDR] = { #define I2C_FREQ_MIN_HZ 10000 #define I2C_FREQ_MAX_HZ I2C_MAX_FAST_MODE_PLUS_FREQ +struct npcm_i2c_data { + u8 fifo_size; + u32 segctl_init_val; + u8 txf_sts_tx_bytes; + u8 rxf_sts_rx_bytes; + u8 rxf_ctl_last_pec; +}; + +static const struct npcm_i2c_data npxm7xx_i2c_data = { + .fifo_size = 16, + .segctl_init_val = 0x0333F000, + .txf_sts_tx_bytes = GENMASK(4, 0), + .rxf_sts_rx_bytes = GENMASK(4, 0), + .rxf_ctl_last_pec = BIT(5), +}; + +static const struct npcm_i2c_data npxm8xx_i2c_data = { + .fifo_size = 32, + .segctl_init_val = 0x9333F000, + .txf_sts_tx_bytes = GENMASK(5, 0), + .rxf_sts_rx_bytes = GENMASK(5, 0), + .rxf_ctl_last_pec = BIT(7), +}; + /* Status of one I2C module */ struct npcm_i2c { struct i2c_adapter adap; struct device *dev; unsigned char __iomem *reg; + const struct npcm_i2c_data *data; spinlock_t lock; /* IRQ synchronization */ struct completion cmd_complete; int cmd_err; @@ -305,8 +325,8 @@ struct npcm_i2c { int slv_rd_ind; int slv_wr_size; int slv_wr_ind; - u8 slv_rd_buf[I2C_HW_FIFO_SIZE]; - u8 slv_wr_buf[I2C_HW_FIFO_SIZE]; + u8 slv_rd_buf[MAX_I2C_HW_FIFO_SIZE]; + u8 slv_wr_buf[MAX_I2C_HW_FIFO_SIZE]; #endif struct dentry *debugfs; /* debugfs device directory */ u64 ber_cnt; @@ -439,7 +459,7 @@ static inline bool npcm_i2c_tx_fifo_empty(struct npcm_i2c *bus) tx_fifo_sts = ioread8(bus->reg + NPCM_I2CTXF_STS); /* check if TX FIFO is not empty */ - if ((tx_fifo_sts & NPCM_I2CTXF_STS_TX_BYTES) == 0) + if ((tx_fifo_sts & bus->data->txf_sts_tx_bytes) == 0) return false; /* check if TX FIFO status bit is set: */ @@ -452,7 +472,7 @@ static inline bool npcm_i2c_rx_fifo_full(struct npcm_i2c *bus) rx_fifo_sts = ioread8(bus->reg + NPCM_I2CRXF_STS); /* check if RX FIFO is not empty: */ - if ((rx_fifo_sts & NPCM_I2CRXF_STS_RX_BYTES) == 0) + if ((rx_fifo_sts & bus->data->rxf_sts_rx_bytes) == 0) return false; /* check if rx fifo full status is set: */ @@ -739,11 +759,11 @@ static void npcm_i2c_callback(struct npcm_i2c *bus, static u8 npcm_i2c_fifo_usage(struct npcm_i2c *bus) { if (bus->operation == I2C_WRITE_OPER) - return FIELD_GET(NPCM_I2CTXF_STS_TX_BYTES, - ioread8(bus->reg + NPCM_I2CTXF_STS)); + return (bus->data->txf_sts_tx_bytes & + ioread8(bus->reg + NPCM_I2CTXF_STS)); if (bus->operation == I2C_READ_OPER) - return FIELD_GET(NPCM_I2CRXF_STS_RX_BYTES, - ioread8(bus->reg + NPCM_I2CRXF_STS)); + return (bus->data->rxf_sts_rx_bytes & + ioread8(bus->reg + NPCM_I2CRXF_STS)); return 0; } @@ -755,13 +775,13 @@ static void npcm_i2c_write_to_fifo_master(struct npcm_i2c *bus, u16 max_bytes) * Fill the FIFO, while the FIFO is not full and there are more bytes * to write */ - size_free_fifo = I2C_HW_FIFO_SIZE - npcm_i2c_fifo_usage(bus); + size_free_fifo = bus->data->fifo_size - npcm_i2c_fifo_usage(bus); while (max_bytes-- && size_free_fifo) { if (bus->wr_ind < bus->wr_size) npcm_i2c_wr_byte(bus, bus->wr_buf[bus->wr_ind++]); else npcm_i2c_wr_byte(bus, 0xFF); - size_free_fifo = I2C_HW_FIFO_SIZE - npcm_i2c_fifo_usage(bus); + size_free_fifo = bus->data->fifo_size - npcm_i2c_fifo_usage(bus); } } @@ -782,11 +802,11 @@ static void npcm_i2c_set_fifo(struct npcm_i2c *bus, int nread, int nwrite) /* configure RX FIFO */ if (nread > 0) { - rxf_ctl = min_t(int, nread, I2C_HW_FIFO_SIZE); + rxf_ctl = min_t(int, nread, bus->data->fifo_size); /* set LAST bit. if LAST is set next FIFO packet is nacked */ - if (nread <= I2C_HW_FIFO_SIZE) - rxf_ctl |= NPCM_I2CRXF_CTL_LAST_PEC; + if (nread <= bus->data->fifo_size) + rxf_ctl |= bus->data->rxf_ctl_last_pec; /* * if we are about to read the first byte in blk rd mode, @@ -804,9 +824,9 @@ static void npcm_i2c_set_fifo(struct npcm_i2c *bus, int nread, int nwrite) /* configure TX FIFO */ if (nwrite > 0) { - if (nwrite > I2C_HW_FIFO_SIZE) + if (nwrite > bus->data->fifo_size) /* data to send is more then FIFO size. */ - iowrite8(I2C_HW_FIFO_SIZE, bus->reg + NPCM_I2CTXF_CTL); + iowrite8(bus->data->fifo_size, bus->reg + NPCM_I2CTXF_CTL); else iowrite8(nwrite, bus->reg + NPCM_I2CTXF_CTL); @@ -873,13 +893,13 @@ static void npcm_i2c_write_fifo_slave(struct npcm_i2c *bus, u16 max_bytes) npcm_i2c_clear_fifo_int(bus); npcm_i2c_clear_tx_fifo(bus); iowrite8(0, bus->reg + NPCM_I2CTXF_CTL); - while (max_bytes-- && I2C_HW_FIFO_SIZE != npcm_i2c_fifo_usage(bus)) { + while (max_bytes-- && bus->data->fifo_size != npcm_i2c_fifo_usage(bus)) { if (bus->slv_wr_size <= 0) break; - bus->slv_wr_ind = bus->slv_wr_ind % I2C_HW_FIFO_SIZE; + bus->slv_wr_ind = bus->slv_wr_ind & (bus->data->fifo_size - 1); npcm_i2c_wr_byte(bus, bus->slv_wr_buf[bus->slv_wr_ind]); bus->slv_wr_ind++; - bus->slv_wr_ind = bus->slv_wr_ind % I2C_HW_FIFO_SIZE; + bus->slv_wr_ind = bus->slv_wr_ind & (bus->data->fifo_size - 1); bus->slv_wr_size--; } } @@ -894,7 +914,7 @@ static void npcm_i2c_read_fifo_slave(struct npcm_i2c *bus, u8 bytes_in_fifo) while (bytes_in_fifo--) { data = npcm_i2c_rd_byte(bus); - bus->slv_rd_ind = bus->slv_rd_ind % I2C_HW_FIFO_SIZE; + bus->slv_rd_ind = bus->slv_rd_ind & (bus->data->fifo_size - 1); bus->slv_rd_buf[bus->slv_rd_ind] = data; bus->slv_rd_ind++; @@ -912,8 +932,8 @@ static int npcm_i2c_slave_get_wr_buf(struct npcm_i2c *bus) int ret = bus->slv_wr_ind; /* fill a cyclic buffer */ - for (i = 0; i < I2C_HW_FIFO_SIZE; i++) { - if (bus->slv_wr_size >= I2C_HW_FIFO_SIZE) + for (i = 0; i < bus->data->fifo_size; i++) { + if (bus->slv_wr_size >= bus->data->fifo_size) break; if (bus->state == I2C_SLAVE_MATCH) { i2c_slave_event(bus->slave, I2C_SLAVE_READ_REQUESTED, &value); @@ -921,11 +941,11 @@ static int npcm_i2c_slave_get_wr_buf(struct npcm_i2c *bus) } else { i2c_slave_event(bus->slave, I2C_SLAVE_READ_PROCESSED, &value); } - ind = (bus->slv_wr_ind + bus->slv_wr_size) % I2C_HW_FIFO_SIZE; + ind = (bus->slv_wr_ind + bus->slv_wr_size) & (bus->data->fifo_size - 1); bus->slv_wr_buf[ind] = value; bus->slv_wr_size++; } - return I2C_HW_FIFO_SIZE - ret; + return bus->data->fifo_size - ret; } static void npcm_i2c_slave_send_rd_buf(struct npcm_i2c *bus) @@ -960,7 +980,7 @@ static void npcm_i2c_slave_receive(struct npcm_i2c *bus, u16 nread, bus->slv_rd_ind = 0; iowrite8(0, bus->reg + NPCM_I2CTXF_CTL); - iowrite8(I2C_HW_FIFO_SIZE, bus->reg + NPCM_I2CRXF_CTL); + iowrite8(bus->data->fifo_size, bus->reg + NPCM_I2CRXF_CTL); npcm_i2c_clear_tx_fifo(bus); npcm_i2c_clear_rx_fifo(bus); } @@ -993,12 +1013,12 @@ static void npcm_i2c_slave_wr_buf_sync(struct npcm_i2c *bus) { int left_in_fifo; - left_in_fifo = FIELD_GET(NPCM_I2CTXF_STS_TX_BYTES, - ioread8(bus->reg + NPCM_I2CTXF_STS)); + left_in_fifo = bus->data->txf_sts_tx_bytes & + ioread8(bus->reg + NPCM_I2CTXF_STS); /* fifo already full: */ - if (left_in_fifo >= I2C_HW_FIFO_SIZE || - bus->slv_wr_size >= I2C_HW_FIFO_SIZE) + if (left_in_fifo >= bus->data->fifo_size || + bus->slv_wr_size >= bus->data->fifo_size) return; /* update the wr fifo index back to the untransmitted bytes: */ @@ -1006,7 +1026,7 @@ static void npcm_i2c_slave_wr_buf_sync(struct npcm_i2c *bus) bus->slv_wr_size = bus->slv_wr_size + left_in_fifo; if (bus->slv_wr_ind < 0) - bus->slv_wr_ind += I2C_HW_FIFO_SIZE; + bus->slv_wr_ind += bus->data->fifo_size; } static void npcm_i2c_slave_rd_wr(struct npcm_i2c *bus) @@ -1152,7 +1172,7 @@ static irqreturn_t npcm_i2c_int_slave_handler(struct npcm_i2c *bus) npcm_i2c_clear_rx_fifo(bus); npcm_i2c_clear_tx_fifo(bus); iowrite8(0, bus->reg + NPCM_I2CTXF_CTL); - iowrite8(I2C_HW_FIFO_SIZE, bus->reg + NPCM_I2CRXF_CTL); + iowrite8(bus->data->fifo_size, bus->reg + NPCM_I2CRXF_CTL); if (NPCM_I2CST_XMIT & i2cst) { bus->operation = I2C_WRITE_OPER; } else { @@ -1313,8 +1333,8 @@ static void npcm_i2c_master_fifo_read(struct npcm_i2c *bus) * read == FIFO Size + C (where C < FIFO Size)then first read C bytes * and in the next int we read rest of the data. */ - if (rcount < (2 * I2C_HW_FIFO_SIZE) && rcount > I2C_HW_FIFO_SIZE) - fifo_bytes = rcount - I2C_HW_FIFO_SIZE; + if (rcount < (2 * bus->data->fifo_size) && rcount > bus->data->fifo_size) + fifo_bytes = rcount - bus->data->fifo_size; if (rcount <= fifo_bytes) { /* last bytes are about to be read - end of tx */ @@ -2193,7 +2213,7 @@ static int npcm_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, * It cannot be cleared without resetting the module. */ else if (bus->cmd_err && - (NPCM_I2CRXF_CTL_LAST_PEC & ioread8(bus->reg + NPCM_I2CRXF_CTL))) + (bus->data->rxf_ctl_last_pec & ioread8(bus->reg + NPCM_I2CRXF_CTL))) npcm_i2c_reset(bus); /* after any xfer, successful or not, stall and EOB must be disabled */ @@ -2262,6 +2282,7 @@ static int npcm_i2c_probe_bus(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; static struct regmap *gcr_regmap; + struct device *dev = &pdev->dev; struct i2c_adapter *adap; struct npcm_i2c *bus; struct clk *i2c_clk; @@ -2274,6 +2295,12 @@ static int npcm_i2c_probe_bus(struct platform_device *pdev) bus->dev = &pdev->dev; + bus->data = of_device_get_match_data(dev); + if (!bus->data) { + dev_err(dev, "OF data missing\n"); + return -EINVAL; + } + bus->num = of_alias_get_id(pdev->dev.of_node, "i2c"); /* core clk must be acquired to calculate module timing settings */ i2c_clk = devm_clk_get(&pdev->dev, NULL); @@ -2287,7 +2314,7 @@ static int npcm_i2c_probe_bus(struct platform_device *pdev) if (IS_ERR(gcr_regmap)) return PTR_ERR(gcr_regmap); - regmap_write(gcr_regmap, NPCM_I2CSEGCTL, NPCM_I2CSEGCTL_INIT_VAL); + regmap_write(gcr_regmap, NPCM_I2CSEGCTL, bus->data->segctl_init_val); bus->reg = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(bus->reg)) @@ -2349,7 +2376,8 @@ static int npcm_i2c_remove_bus(struct platform_device *pdev) } static const struct of_device_id npcm_i2c_bus_of_table[] = { - { .compatible = "nuvoton,npcm750-i2c", }, + { .compatible = "nuvoton,npcm750-i2c", .data = &npxm7xx_i2c_data }, + { .compatible = "nuvoton,npcm845-i2c", .data = &npxm8xx_i2c_data }, {} }; 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[220.133.130.217]) by smtp.gmail.com with ESMTPSA id c2-20020a170902848200b00161996b9a66sm7969391plo.233.2022.05.24.20.24.25 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 24 May 2022 20:24:25 -0700 (PDT) From: Tyrone Ting To: avifishman70@gmail.com, tmaimon77@gmail.com, tali.perry1@gmail.com, venture@google.com, yuenn@google.com, benjaminfair@google.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, wsa@kernel.org, andriy.shevchenko@linux.intel.com, jarkko.nikula@linux.intel.com, semen.protsenko@linaro.org, jie.deng@intel.com, jsd@semihalf.com, sven@svenpeter.dev, lukas.bulwahn@gmail.com, olof@lixom.net, arnd@arndb.de, warp5tw@gmail.com, tali.perry@nuvoton.com, Avi.Fishman@nuvoton.com, tomer.maimon@nuvoton.com, KWLIU@nuvoton.com, JJLIU0@nuvoton.com, kfting@nuvoton.com Subject: [PATCH v6 5/5] i2c: npcm: Capitalize the one-line comment Date: Wed, 25 May 2022 11:23:41 +0800 Message-Id: <20220525032341.3182-6-warp5tw@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220525032341.3182-1-warp5tw@gmail.com> References: <20220525032341.3182-1-warp5tw@gmail.com> X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, openbmc@lists.ozlabs.org, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" From: Tyrone Ting Make the one-line comments capital in the driver to get the comment style consistent. Fixes: 56a1485b102e ("i2c: npcm7xx: Add Nuvoton NPCM I2C controller driver") Signed-off-by: Tyrone Ting --- drivers/i2c/busses/i2c-npcm7xx.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/i2c/busses/i2c-npcm7xx.c b/drivers/i2c/busses/i2c-npcm7xx.c index 86fd942ea648..7d863edc14e4 100644 --- a/drivers/i2c/busses/i2c-npcm7xx.c +++ b/drivers/i2c/busses/i2c-npcm7xx.c @@ -680,7 +680,7 @@ static void npcm_i2c_reset(struct npcm_i2c *bus) } #endif - /* clear status bits for spurious interrupts */ + /* Clear status bits for spurious interrupts */ npcm_i2c_clear_master_status(bus); bus->state = I2C_IDLE; @@ -1252,7 +1252,7 @@ static irqreturn_t npcm_i2c_int_slave_handler(struct npcm_i2c *bus) } /* SDAST */ /* - * if irq is not one of the above, make sure EOB is disabled and all + * If irq is not one of the above, make sure EOB is disabled and all * status bits are cleared. */ if (ret == IRQ_NONE) { @@ -1506,7 +1506,7 @@ static void npcm_i2c_irq_handle_nack(struct npcm_i2c *bus) npcm_i2c_clear_master_status(bus); readx_poll_timeout_atomic(ioread8, bus->reg + NPCM_I2CCST, val, !(val & NPCM_I2CCST_BUSY), 10, 200); - /* verify no status bits are still set after bus is released */ + /* Verify no status bits are still set after bus is released */ npcm_i2c_clear_master_status(bus); } bus->state = I2C_IDLE; @@ -1974,7 +1974,7 @@ static int npcm_i2c_init_module(struct npcm_i2c *bus, enum i2c_mode mode, npcm_i2c_reset(bus); - /* check HW is OK: SDA and SCL should be high at this point. */ + /* Check HW is OK: SDA and SCL should be high at this point. */ if ((npcm_i2c_get_SDA(&bus->adap) == 0) || (npcm_i2c_get_SCL(&bus->adap) == 0)) { dev_err(bus->dev, "I2C%d init fail: lines are low\n", bus->num); dev_err(bus->dev, "SDA=%d SCL=%d\n", npcm_i2c_get_SDA(&bus->adap), @@ -2034,7 +2034,7 @@ static irqreturn_t npcm_i2c_bus_irq(int irq, void *dev_id) return IRQ_HANDLED; } #endif - /* clear status bits for spurious interrupts */ + /* Clear status bits for spurious interrupts */ npcm_i2c_clear_master_status(bus); return IRQ_HANDLED; @@ -2216,7 +2216,7 @@ static int npcm_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, (bus->data->rxf_ctl_last_pec & ioread8(bus->reg + NPCM_I2CRXF_CTL))) npcm_i2c_reset(bus); - /* after any xfer, successful or not, stall and EOB must be disabled */ + /* After any xfer, successful or not, stall and EOB must be disabled */ npcm_i2c_stall_after_start(bus, false); npcm_i2c_eob_int(bus, false);