From patchwork Thu May 19 08:43:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Liang X-Patchwork-Id: 1633128 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4L3k1M3qrFz9t5H for ; Thu, 19 May 2022 18:44:23 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 3406A83919; Thu, 19 May 2022 10:44:17 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 8623583ABF; Thu, 19 May 2022 10:44:15 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from Atcsqr.andestech.com (exmail.andestech.com [60.248.187.195]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 566AA837EF for ; Thu, 19 May 2022 10:44:05 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ycliang@andestech.com Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 24J8hdhG092255; Thu, 19 May 2022 16:43:39 +0800 (+08) (envelope-from ycliang@andestech.com) Received: from atcfdc88.andestech.com (10.0.15.120) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Thu, 19 May 2022 16:43:36 +0800 From: Leo Yu-Chi Liang To: CC: , , , , Subject: [PATCH v2, 1/1] riscv: Clean up asm/io.h Date: Thu, 19 May 2022 16:43:31 +0800 Message-ID: <20220519084331.12536-1-ycliang@andestech.com> X-Mailer: git-send-email 2.34.1.390.g2ae0a9cb82 MIME-Version: 1.0 X-Originating-IP: [10.0.15.120] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 24J8hdhG092255 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Clean up asm/io.h by - removing commented code - removing outdated comments - removing unused definitions (for mem_isa, mem_pci) This massively improves the readability of the file. Suggested by commits: 7ab2e47d27c9 ("arm: Clean up asm/io.h") 909d0399a519 ("ARM: asm/io.h: kill off confusing #ifdef __mem_pci block") Signed-off-by: Leo Yu-Chi Liang Reviewed-by: Bin Meng --- arch/riscv/include/asm/io.h | 117 +----------------------------------- 1 file changed, 1 insertion(+), 116 deletions(-) diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index fc39bb2c70..49bffac03c 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -7,8 +7,6 @@ #ifndef __ASM_RISCV_IO_H #define __ASM_RISCV_IO_H -#ifdef __KERNEL__ - #include #include #include @@ -39,11 +37,7 @@ static inline phys_addr_t map_to_sysmem(const void *ptr) } #endif -/* - * Generic virtual read/write. Note that we don't support half-word - * read/writes. We define __arch_*[bl] here, and leave __arch_*w - * to the architecture specific code. - */ +/* Generic virtual read/write. */ #define __arch_getb(a) (*(volatile unsigned char *)(a)) #define __arch_getw(a) (*(volatile unsigned short *)(a)) #define __arch_getl(a) (*(volatile unsigned int *)(a)) @@ -352,115 +346,6 @@ static inline void writesl(unsigned int *addr, const void *data, int longlen) #define insw_p(port, to, len) insw(port, to, len) #define insl_p(port, to, len) insl(port, to, len) -/* - * DMA-consistent mapping functions. These allocate/free a region of - * uncached, unwrite-buffered mapped memory space for use with DMA - * devices. This is the "generic" version. The PCI specific version - * is in pci.h - */ - -/* - * String version of IO memory access ops: - */ - -/* - * If this architecture has PCI memory IO, then define the read/write - * macros. These should only be used with the cookie passed from - * ioremap. - */ -#ifdef __mem_pci - -#define readb(c) ({ unsigned int __v = \ - __raw_readb(__mem_pci(c)); __v; }) -#define readw(c) ({ unsigned int __v = \ - le16_to_cpu(__raw_readw(__mem_pci(c))); __v; }) -#define readl(c) ({ unsigned int __v = \ - le32_to_cpu(__raw_readl(__mem_pci(c))); __v; }) - -#define writeb(v, c) __raw_writeb(v, __mem_pci(c)) -#define writew(v, c) __raw_writew(cpu_to_le16(v), __mem_pci(c)) -#define writel(v, c) __raw_writel(cpu_to_le32(v), __mem_pci(c)) - -#define memset_io(c, v, l) _memset_io(__mem_pci(c), (v), (l)) -#define memcpy_fromio(a, c, l) _memcpy_fromio((a), __mem_pci(c), (l)) -#define memcpy_toio(c, a, l) _memcpy_toio(__mem_pci(c), (a), (l)) - -#define eth_io_copy_and_sum(s, c, l, b) \ - eth_copy_and_sum((s), __mem_pci(c), (l), (b)) - -static inline int check_signature(ulong io_addr, const uchar *s, int len) -{ - int retval = 0; - - do { - if (readb(io_addr) != *s) - goto out; - io_addr++; - s++; - len--; - } while (len); - retval = 1; -out: - return retval; -} -#endif /* __mem_pci */ - -/* - * If this architecture has ISA IO, then define the isa_read/isa_write - * macros. - */ -#ifdef __mem_isa - -#define isa_readb(addr) __raw_readb(__mem_isa(addr)) -#define isa_readw(addr) __raw_readw(__mem_isa(addr)) -#define isa_readl(addr) __raw_readl(__mem_isa(addr)) -#define isa_writeb(val, addr) __raw_writeb(val, __mem_isa(addr)) -#define isa_writew(val, addr) __raw_writew(val, __mem_isa(addr)) -#define isa_writel(val, addr) __raw_writel(val, __mem_isa(addr)) -#define isa_memset_io(a, b, c) _memset_io(__mem_isa(a), (b), (c)) -#define isa_memcpy_fromio(a, b, c) _memcpy_fromio((a), __mem_isa(b), (c)) -#define isa_memcpy_toio(a, b, c) _memcpy_toio(__mem_isa((a)), (b), (c)) - -#define isa_eth_io_copy_and_sum(a, b, c, d) \ - eth_copy_and_sum((a), __mem_isa(b), (c), (d)) - -static inline int -isa_check_signature(ulong io_addr, const uchar *s, int len) -{ - int retval = 0; - - do { - if (isa_readb(io_addr) != *s) - goto out; - io_addr++; - s++; - len--; - } while (len); - retval = 1; -out: - return retval; -} - -#else /* __mem_isa */ - -#define isa_readb(addr) (__readwrite_bug("isa_readb"), 0) -#define isa_readw(addr) (__readwrite_bug("isa_readw"), 0) -#define isa_readl(addr) (__readwrite_bug("isa_readl"), 0) -#define isa_writeb(val, addr) __readwrite_bug("isa_writeb") -#define isa_writew(val, addr) __readwrite_bug("isa_writew") -#define isa_writel(val, addr) __readwrite_bug("isa_writel") -#define isa_memset_io(a, b, c) __readwrite_bug("isa_memset_io") -#define isa_memcpy_fromio(a, b, c) __readwrite_bug("isa_memcpy_fromio") -#define isa_memcpy_toio(a, b, c) __readwrite_bug("isa_memcpy_toio") - -#define isa_eth_io_copy_and_sum(a, b, c, d) \ - __readwrite_bug("isa_eth_io_copy_and_sum") - -#define isa_check_signature(io, sig, len) (0) - -#endif /* __mem_isa */ -#endif /* __KERNEL__ */ - #include #endif /* __ASM_RISCV_IO_H */