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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230001)(4636009)(46966006)(40470700004)(36840700001)(70206006)(8676002)(235185007)(2616005)(70586007)(4326008)(6916009)(82310400005)(6506007)(186003)(47076005)(5660300002)(336012)(6486002)(44144004)(33964004)(26005)(4743002)(81166007)(6512007)(356005)(36860700001)(86362001)(36756003)(2906002)(8936002)(316002)(40460700003)(508600001)(44832011)(4216001)(2700100001); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 May 2022 17:11:26.7073 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bfd45da8-c5d8-4de8-d54f-08da35039d69 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VE1EUR03FT035.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR08MB7044 X-Spam-Status: No, score=-13.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_LOTSOFHASH, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, THIS_AD, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tamar Christina via Gcc-patches From: Tamar Christina Reply-To: Tamar Christina Cc: richard.sandiford@arm.com, nd@arm.com, rguenther@suse.de Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Hi All, Some targets require function parameters to be promoted to a different type on expand time because the target may not have native instructions to work on such types. As an example the AArch64 port does not have native instructions working on integer 8- or 16-bit values. As such it promotes every parameter of these types to 32-bits. This promotion could be done by a target for two reasons: 1. For correctness. This may be an APCS requirement for instance. 2. For efficiency. By promoting the argument at expansion time we don't have to keep promoting the type back and forth after each operation on it. i.e. the promotion simplies the RTL. This patch adds the ability for a target to decide whether during the expansion to use an extend to handle promotion or to use a paradoxical subreg. A pradoxical subreg can be used when there's no correctness issues and when you still want the RTL efficiency of not doing the promotion constantly. This also allows the target to not need to generate any code when the top bits are not significant. An example is in AArch64 the following extend is unneeded: uint8_t fd2 (uint8_t xr){ return xr + 1; } currently generates: fd2: and w0, w0, 255 add w0, w0, 1 ret instead of fd2: add w0, w0, #1 ret Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Bootstrapped on x86_64-pc-linux-gnu and no issues Ok for master? Thanks, Tamar gcc/ChangeLog: * cfgexpand.cc (set_rtl): Check for function promotion. * tree-outof-ssa.cc (insert_value_copy_on_edge): Likewise. * function.cc (assign_parm_setup_reg): Likewise. * hooks.cc (hook_bool_mode_mode_int_tree_false, hook_bool_mode_mode_int_tree_true): New. * hooks.h (hook_bool_mode_mode_int_tree_false, hook_bool_mode_mode_int_tree_true): New. * target.def (promote_function_args_subreg_p): New. * doc/tm.texi: Document it. * doc/tm.texi.in: Likewise. --- inline copy of patch -- diff --git a/gcc/cfgexpand.cc b/gcc/cfgexpand.cc index d3cc77d2ca98f620b29623fc5696410bad9bc184..df95184cfa185312c2a46cb92daa051718d9f4f3 100644 --- diff --git a/gcc/cfgexpand.cc b/gcc/cfgexpand.cc index d3cc77d2ca98f620b29623fc5696410bad9bc184..df95184cfa185312c2a46cb92daa051718d9f4f3 100644 --- a/gcc/cfgexpand.cc +++ b/gcc/cfgexpand.cc @@ -206,14 +206,20 @@ set_rtl (tree t, rtx x) have to compute it ourselves. For RESULT_DECLs, we accept mode mismatches too, as long as we have BLKmode or are not coalescing across variables, so that we don't reject BLKmode PARALLELs or - unpromoted REGs. */ + unpromoted REGs. For any promoted types that result in a + paradoxical subreg also accept the argument. */ gcc_checking_assert (!x || x == pc_rtx || TREE_CODE (t) != SSA_NAME || (SSAVAR (t) && TREE_CODE (SSAVAR (t)) == RESULT_DECL && (promote_ssa_mode (t, NULL) == BLKmode || !flag_tree_coalesce_vars)) || !use_register_for_decl (t) - || GET_MODE (x) == promote_ssa_mode (t, NULL)); + || GET_MODE (x) == promote_ssa_mode (t, NULL) + || targetm.calls.promote_function_args_subreg_p ( + GET_MODE (x), + promote_ssa_mode (t, NULL), + TYPE_UNSIGNED (TREE_TYPE (t)), + SSAVAR (t))); if (x) { diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi index 2f92d37da8c0091e9879a493cfe8a361eb1d9299..6314cd83a2488dc225d4a1a15599e8e51e639f7f 100644 --- a/gcc/doc/tm.texi +++ b/gcc/doc/tm.texi @@ -3906,6 +3906,15 @@ cases of mismatch, it also makes for better code on certain machines. The default is to not promote prototypes. @end deftypefn +@deftypefn {Target Hook} bool TARGET_PROMOTE_FUNCTION_ARGS_SUBREG_P (machine_mode @var{mode}, machine_mode @var{promoted_mode}, int @var{unsignedp}, tree @var{v}) +When a function argument is promoted with @code{PROMOTE_MODE} then this +hook is used to determine whether the bits of the promoted type are all +significant in the expression pointed to by V. If they are an extend is +generated, if they are not a paradoxical subreg is created for the argument +from @code{mode} to @code{promoted_mode}. +The default is to promote using an extend. +@end deftypefn + @deftypefn {Target Hook} bool TARGET_PUSH_ARGUMENT (unsigned int @var{npush}) This target hook returns @code{true} if push instructions will be used to pass outgoing arguments. When the push instruction usage is diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in index f869ddd5e5b8b7acbd8e9765fb103af24a1085b6..35f955803ec0a5a93be18a028fa1043f90858982 100644 --- a/gcc/doc/tm.texi.in +++ b/gcc/doc/tm.texi.in @@ -3103,6 +3103,8 @@ control passing certain arguments in registers. @hook TARGET_PROMOTE_PROTOTYPES +@hook TARGET_PROMOTE_FUNCTION_ARGS_SUBREG_P + @hook TARGET_PUSH_ARGUMENT @defmac PUSH_ARGS_REVERSED diff --git a/gcc/function.cc b/gcc/function.cc index d5ed51a6a663a1ef472f5b1c090543f359c18f42..92f469bfd5d1ebfb09cc94d9be854715cd2f90f8 100644 --- a/gcc/function.cc +++ b/gcc/function.cc @@ -3161,7 +3161,7 @@ assign_parm_setup_reg (struct assign_parm_data_all *all, tree parm, machine_mode promoted_nominal_mode; int unsignedp = TYPE_UNSIGNED (TREE_TYPE (parm)); bool did_conversion = false; - bool need_conversion, moved; + bool need_conversion, moved, use_subregs; enum insn_code icode; rtx rtl; @@ -3172,7 +3172,20 @@ assign_parm_setup_reg (struct assign_parm_data_all *all, tree parm, = promote_function_mode (data->nominal_type, data->nominal_mode, &unsignedp, TREE_TYPE (current_function_decl), 2); - parmreg = gen_reg_rtx (promoted_nominal_mode); + /* Check to see how the target wants the promotion of function arguments to + be handled. */ + use_subregs + = targetm.calls.promote_function_args_subreg_p (data->nominal_mode, + promoted_nominal_mode, + unsignedp, parm); + + /* If we're promoting using a paradoxical subreg then we need to keep using + the unpromoted type because that's the only fully defined value. */ + if (use_subregs) + parmreg = gen_reg_rtx (data->nominal_mode); + else + parmreg = gen_reg_rtx (promoted_nominal_mode); + if (!DECL_ARTIFICIAL (parm)) mark_user_reg (parmreg); @@ -3256,9 +3269,19 @@ assign_parm_setup_reg (struct assign_parm_data_all *all, tree parm, } else t = op1; - rtx_insn *pat = gen_extend_insn (op0, t, promoted_nominal_mode, - data->passed_mode, unsignedp); - emit_insn (pat); + + /* Promote the argument itself now if a target wants it. This + prevents unneeded back and forth convertions in RTL between + the original and promoted type. */ + if (use_subregs) + emit_move_insn (op0, lowpart_subreg (promoted_nominal_mode, t, + data->nominal_mode)); + else + { + rtx_insn *pat = gen_extend_insn (op0, t, promoted_nominal_mode, + data->passed_mode, unsignedp); + emit_insn (pat); + } insns = get_insns (); moved = true; diff --git a/gcc/hooks.h b/gcc/hooks.h index 1056e1e9e4dc3e6ce298557351047caa2f84227f..8d68de5cdb9adaea0a79ebf6de599f66b40aa67a 100644 --- a/gcc/hooks.h +++ b/gcc/hooks.h @@ -31,6 +31,8 @@ extern bool hook_bool_const_int_const_int_true (const int, const int); extern bool hook_bool_mode_false (machine_mode); extern bool hook_bool_mode_true (machine_mode); extern bool hook_bool_mode_mode_true (machine_mode, machine_mode); +extern bool hook_bool_mode_mode_int_tree_false (machine_mode, machine_mode, int, tree); +extern bool hook_bool_mode_mode_int_tree_true (machine_mode, machine_mode, int, tree); extern bool hook_bool_mode_const_rtx_false (machine_mode, const_rtx); extern bool hook_bool_mode_const_rtx_true (machine_mode, const_rtx); extern bool hook_bool_mode_rtx_false (machine_mode, rtx); diff --git a/gcc/hooks.cc b/gcc/hooks.cc index b29233f4f852fb81ede75a5065d743cd16cc9219..7647774f9e8efbbe13d5607e4a4b2f1c9d22f045 100644 --- a/gcc/hooks.cc +++ b/gcc/hooks.cc @@ -89,6 +89,22 @@ hook_bool_mode_mode_true (machine_mode, machine_mode) return true; } +/* Generic hook that takes (machine_mode, machine_mode, int, tree) and + returns false. */ +bool +hook_bool_mode_mode_int_tree_false (machine_mode, machine_mode, int, tree) +{ + return false; +} + +/* Generic hook that takes (machine_mode, machine_mode, int, tree) and + returns true. */ +bool +hook_bool_mode_mode_int_tree_true (machine_mode, machine_mode, int, tree) +{ + return true; +} + /* Generic hook that takes (machine_mode, const_rtx) and returns false. */ bool hook_bool_mode_const_rtx_false (machine_mode, const_rtx) diff --git a/gcc/target.def b/gcc/target.def index 72c2e1ef756cf70a1c92abe81f8a6577eaaa2501..bdbacf8c5fd7b0626a37951f6f6ec649f3194977 100644 --- a/gcc/target.def +++ b/gcc/target.def @@ -4561,6 +4561,17 @@ The default is to not promote prototypes.", bool, (const_tree fntype), hook_bool_const_tree_false) +DEFHOOK +(promote_function_args_subreg_p, + "When a function argument is promoted with @code{PROMOTE_MODE} then this\n\ +hook is used to determine whether the bits of the promoted type are all\n\ +significant in the expression pointed to by V. If they are an extend is\n\ +generated, if they are not a paradoxical subreg is created for the argument\n\ +from @code{mode} to @code{promoted_mode}.\n\ +The default is to promote using an extend.", + bool, (machine_mode mode, machine_mode promoted_mode, int unsignedp, tree v), + hook_bool_mode_mode_int_tree_false) + DEFHOOK (struct_value_rtx, "This target hook should return the location of the structure value\n\ diff --git a/gcc/tree-outof-ssa.cc b/gcc/tree-outof-ssa.cc index ec883126ad86d86a2c2dafee4592b8d83e2ed917..0f437023983baa0f23da25221f7bce8fc559a8b8 100644 --- a/gcc/tree-outof-ssa.cc +++ b/gcc/tree-outof-ssa.cc @@ -45,6 +45,7 @@ along with GCC; see the file COPYING3. If not see #include "tree-ssa-coalesce.h" #include "tree-outof-ssa.h" #include "dojump.h" +#include "target.h" /* FIXME: A lot of code here deals with expanding to RTL. All that code should be in cfgexpand.cc. */ @@ -333,7 +334,10 @@ insert_value_copy_on_edge (edge e, int dest, tree src, location_t locus) dest_mode = GET_MODE (dest_rtx); gcc_assert (src_mode == TYPE_MODE (TREE_TYPE (name))); gcc_assert (!REG_P (dest_rtx) - || dest_mode == promote_ssa_mode (name, &unsignedp)); + || dest_mode == promote_ssa_mode (name, &unsignedp) + || targetm.calls.promote_function_args_subreg_p ( + dest_mode, promote_ssa_mode (name, NULL), unsignedp, + name)); if (src_mode != dest_mode) { --- a/gcc/cfgexpand.cc +++ b/gcc/cfgexpand.cc @@ -206,14 +206,20 @@ set_rtl (tree t, rtx x) have to compute it ourselves. For RESULT_DECLs, we accept mode mismatches too, as long as we have BLKmode or are not coalescing across variables, so that we don't reject BLKmode PARALLELs or - unpromoted REGs. */ + unpromoted REGs. For any promoted types that result in a + paradoxical subreg also accept the argument. */ gcc_checking_assert (!x || x == pc_rtx || TREE_CODE (t) != SSA_NAME || (SSAVAR (t) && TREE_CODE (SSAVAR (t)) == RESULT_DECL && (promote_ssa_mode (t, NULL) == BLKmode || !flag_tree_coalesce_vars)) || !use_register_for_decl (t) - || GET_MODE (x) == promote_ssa_mode (t, NULL)); + || GET_MODE (x) == promote_ssa_mode (t, NULL) + || targetm.calls.promote_function_args_subreg_p ( + GET_MODE (x), + promote_ssa_mode (t, NULL), + TYPE_UNSIGNED (TREE_TYPE (t)), + SSAVAR (t))); if (x) { diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi index 2f92d37da8c0091e9879a493cfe8a361eb1d9299..6314cd83a2488dc225d4a1a15599e8e51e639f7f 100644 --- a/gcc/doc/tm.texi +++ b/gcc/doc/tm.texi @@ -3906,6 +3906,15 @@ cases of mismatch, it also makes for better code on certain machines. The default is to not promote prototypes. @end deftypefn +@deftypefn {Target Hook} bool TARGET_PROMOTE_FUNCTION_ARGS_SUBREG_P (machine_mode @var{mode}, machine_mode @var{promoted_mode}, int @var{unsignedp}, tree @var{v}) +When a function argument is promoted with @code{PROMOTE_MODE} then this +hook is used to determine whether the bits of the promoted type are all +significant in the expression pointed to by V. If they are an extend is +generated, if they are not a paradoxical subreg is created for the argument +from @code{mode} to @code{promoted_mode}. +The default is to promote using an extend. +@end deftypefn + @deftypefn {Target Hook} bool TARGET_PUSH_ARGUMENT (unsigned int @var{npush}) This target hook returns @code{true} if push instructions will be used to pass outgoing arguments. When the push instruction usage is diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in index f869ddd5e5b8b7acbd8e9765fb103af24a1085b6..35f955803ec0a5a93be18a028fa1043f90858982 100644 --- a/gcc/doc/tm.texi.in +++ b/gcc/doc/tm.texi.in @@ -3103,6 +3103,8 @@ control passing certain arguments in registers. @hook TARGET_PROMOTE_PROTOTYPES +@hook TARGET_PROMOTE_FUNCTION_ARGS_SUBREG_P + @hook TARGET_PUSH_ARGUMENT @defmac PUSH_ARGS_REVERSED diff --git a/gcc/function.cc b/gcc/function.cc index d5ed51a6a663a1ef472f5b1c090543f359c18f42..92f469bfd5d1ebfb09cc94d9be854715cd2f90f8 100644 --- a/gcc/function.cc +++ b/gcc/function.cc @@ -3161,7 +3161,7 @@ assign_parm_setup_reg (struct assign_parm_data_all *all, tree parm, machine_mode promoted_nominal_mode; int unsignedp = TYPE_UNSIGNED (TREE_TYPE (parm)); bool did_conversion = false; - bool need_conversion, moved; + bool need_conversion, moved, use_subregs; enum insn_code icode; rtx rtl; @@ -3172,7 +3172,20 @@ assign_parm_setup_reg (struct assign_parm_data_all *all, tree parm, = promote_function_mode (data->nominal_type, data->nominal_mode, &unsignedp, TREE_TYPE (current_function_decl), 2); - parmreg = gen_reg_rtx (promoted_nominal_mode); + /* Check to see how the target wants the promotion of function arguments to + be handled. */ + use_subregs + = targetm.calls.promote_function_args_subreg_p (data->nominal_mode, + promoted_nominal_mode, + unsignedp, parm); + + /* If we're promoting using a paradoxical subreg then we need to keep using + the unpromoted type because that's the only fully defined value. */ + if (use_subregs) + parmreg = gen_reg_rtx (data->nominal_mode); + else + parmreg = gen_reg_rtx (promoted_nominal_mode); + if (!DECL_ARTIFICIAL (parm)) mark_user_reg (parmreg); @@ -3256,9 +3269,19 @@ assign_parm_setup_reg (struct assign_parm_data_all *all, tree parm, } else t = op1; - rtx_insn *pat = gen_extend_insn (op0, t, promoted_nominal_mode, - data->passed_mode, unsignedp); - emit_insn (pat); + + /* Promote the argument itself now if a target wants it. This + prevents unneeded back and forth convertions in RTL between + the original and promoted type. */ + if (use_subregs) + emit_move_insn (op0, lowpart_subreg (promoted_nominal_mode, t, + data->nominal_mode)); + else + { + rtx_insn *pat = gen_extend_insn (op0, t, promoted_nominal_mode, + data->passed_mode, unsignedp); + emit_insn (pat); + } insns = get_insns (); moved = true; diff --git a/gcc/hooks.h b/gcc/hooks.h index 1056e1e9e4dc3e6ce298557351047caa2f84227f..8d68de5cdb9adaea0a79ebf6de599f66b40aa67a 100644 --- a/gcc/hooks.h +++ b/gcc/hooks.h @@ -31,6 +31,8 @@ extern bool hook_bool_const_int_const_int_true (const int, const int); extern bool hook_bool_mode_false (machine_mode); extern bool hook_bool_mode_true (machine_mode); extern bool hook_bool_mode_mode_true (machine_mode, machine_mode); +extern bool hook_bool_mode_mode_int_tree_false (machine_mode, machine_mode, int, tree); +extern bool hook_bool_mode_mode_int_tree_true (machine_mode, machine_mode, int, tree); extern bool hook_bool_mode_const_rtx_false (machine_mode, const_rtx); extern bool hook_bool_mode_const_rtx_true (machine_mode, const_rtx); extern bool hook_bool_mode_rtx_false (machine_mode, rtx); diff --git a/gcc/hooks.cc b/gcc/hooks.cc index b29233f4f852fb81ede75a5065d743cd16cc9219..7647774f9e8efbbe13d5607e4a4b2f1c9d22f045 100644 --- a/gcc/hooks.cc +++ b/gcc/hooks.cc @@ -89,6 +89,22 @@ hook_bool_mode_mode_true (machine_mode, machine_mode) return true; } +/* Generic hook that takes (machine_mode, machine_mode, int, tree) and + returns false. */ +bool +hook_bool_mode_mode_int_tree_false (machine_mode, machine_mode, int, tree) +{ + return false; +} + +/* Generic hook that takes (machine_mode, machine_mode, int, tree) and + returns true. */ +bool +hook_bool_mode_mode_int_tree_true (machine_mode, machine_mode, int, tree) +{ + return true; +} + /* Generic hook that takes (machine_mode, const_rtx) and returns false. */ bool hook_bool_mode_const_rtx_false (machine_mode, const_rtx) diff --git a/gcc/target.def b/gcc/target.def index 72c2e1ef756cf70a1c92abe81f8a6577eaaa2501..bdbacf8c5fd7b0626a37951f6f6ec649f3194977 100644 --- a/gcc/target.def +++ b/gcc/target.def @@ -4561,6 +4561,17 @@ The default is to not promote prototypes.", bool, (const_tree fntype), hook_bool_const_tree_false) +DEFHOOK +(promote_function_args_subreg_p, + "When a function argument is promoted with @code{PROMOTE_MODE} then this\n\ +hook is used to determine whether the bits of the promoted type are all\n\ +significant in the expression pointed to by V. If they are an extend is\n\ +generated, if they are not a paradoxical subreg is created for the argument\n\ +from @code{mode} to @code{promoted_mode}.\n\ +The default is to promote using an extend.", + bool, (machine_mode mode, machine_mode promoted_mode, int unsignedp, tree v), + hook_bool_mode_mode_int_tree_false) + DEFHOOK (struct_value_rtx, "This target hook should return the location of the structure value\n\ diff --git a/gcc/tree-outof-ssa.cc b/gcc/tree-outof-ssa.cc index ec883126ad86d86a2c2dafee4592b8d83e2ed917..0f437023983baa0f23da25221f7bce8fc559a8b8 100644 --- a/gcc/tree-outof-ssa.cc +++ b/gcc/tree-outof-ssa.cc @@ -45,6 +45,7 @@ along with GCC; see the file COPYING3. If not see #include "tree-ssa-coalesce.h" #include "tree-outof-ssa.h" #include "dojump.h" +#include "target.h" /* FIXME: A lot of code here deals with expanding to RTL. All that code should be in cfgexpand.cc. */ @@ -333,7 +334,10 @@ insert_value_copy_on_edge (edge e, int dest, tree src, location_t locus) dest_mode = GET_MODE (dest_rtx); gcc_assert (src_mode == TYPE_MODE (TREE_TYPE (name))); gcc_assert (!REG_P (dest_rtx) - || dest_mode == promote_ssa_mode (name, &unsignedp)); + || dest_mode == promote_ssa_mode (name, &unsignedp) + || targetm.calls.promote_function_args_subreg_p ( + dest_mode, promote_ssa_mode (name, NULL), unsignedp, + name)); if (src_mode != dest_mode) { From patchwork Fri May 13 17:11:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tamar Christina X-Patchwork-Id: 1630861 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=nH9z43L3; dkim-atps=neutral Authentication-Results: ozlabs.org; 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This promotion is not required for the ABI which states: ``` C.9 If the argument is an Integral or Pointer Type, the size of the argument is less than or equal to 8 bytes and the NGRN is less than 8, the argument is copied to the least significant bits in x[NGRN]. The NGRN is incremented by one. The argument has now been allocated. C.16 If the size of the argument is less than 8 bytes then the size of the argument is set to 8 bytes. The effect is as if the argument was copied to the least significant bits of a 64-bit register and the remaining bits filled with unspecified values ``` That is, the bits in the registers are unspecified and callees cannot assume any particular status. This means that we can avoid the promotion and still get correct code as the language level promotion rules require values to be extended when the bits are significant. So if we are .e.g OR-ing two 8-bit values no extend is needed as the top bits are irrelevant. If we are doing e.g. addition, then the top bits *might* be relevant depending on the result type. But the middle end will always contain the appropriate extend in those cases. The mid-end also has optimizations around this assumption and the AArch64 port actively undoes them. So for instance uint16_t fd (uint8_t xr){ return xr + 1; } uint8_t fd2 (uint8_t xr){ return xr + 1; } should produce fd: // @fd and w8, w0, #0xff add w0, w8, #1 ret fd2: // @fd2 add w0, w0, #1 ret like clang does instead of fd: and w0, w0, 255 add w0, w0, 1 ret fd2: and w0, w0, 255 add w0, w0, 1 ret like we do now. Removing this forced expansion maintains correctness but fixes issues with various codegen defects. It also brings us inline with clang. Note that C, C++ and Fortran etc all correctly specify what should happen w.r.t extends and e.g. array indexing, pointer arith etc so we never get incorrect code. There is however a second reason for doing this promotion: RTL efficiency. The promotion stops us from having to promote the values to SI to be able to use them in instructions and then truncating again afterwards. To get both the efficiency and the simpler RTL we can instead promote to a paradoxical subreg. This patch implements the hook for AArch64 and adds an explicit opt-out for values that feed into comparisons. This is done because: 1. our comparisons patterns already allow us to absorb the zero extend 2. The extension allows us to use cbz/cbnz/tbz etc. In some cases such as int foo (char a, char b) { if (a) if (b) bar1 (); else ... else if (b) bar2 (); else ... } by zero extending the value we can avoid having to repeatedly test the value before a branch. Allowing the zero extend also allows our existing `ands` patterns to work as expected. Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. I have to commit this and the last patch together but ease of review I have split them up here. However 209 missed optimization xfails are fixed. No performance difference on SPECCPU 2017 but no failures. Ok for master? Thanks, Tamar gcc/ChangeLog: * config/aarch64/aarch64.cc (aarch64_promote_function_args_subreg_p): (TARGET_PROMOTE_FUNCTION_ARGS_SUBREG_P): New. * config/aarch64/aarch64.h (PROMOTE_MODE): Expand doc. gcc/testsuite/ChangeLog: * gcc.target/aarch64/apc-subreg.c: New test. --- inline copy of patch -- diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index efa46ac0b8799b5849b609d591186e26e5cb37ff..cc74a816fcc6458aa065246a30a4d2184692ad74 100644 --- diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index efa46ac0b8799b5849b609d591186e26e5cb37ff..cc74a816fcc6458aa065246a30a4d2184692ad74 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -34,7 +34,8 @@ #define REGISTER_TARGET_PRAGMAS() aarch64_register_pragmas () -/* Target machine storage layout. */ +/* Target machine storage layout. See also + TARGET_PROMOTE_FUNCTION_ARGS_SUBREG_P. */ #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ if (GET_MODE_CLASS (MODE) == MODE_INT \ diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 2f559600cff55af9d468e8d0810545583cc986f5..252d6c2af72afc1dfee1a86644a5753784b41f59 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -3736,6 +3736,57 @@ aarch64_array_mode_supported_p (machine_mode mode, return false; } +/* Implement target hook TARGET_PROMOTE_FUNCTION_ARGS_SUBREG_P to complement + PROMOTE_MODE. If any argument promotion was done, do them as subregs. */ +static bool +aarch64_promote_function_args_subreg_p (machine_mode mode, + machine_mode promoted_mode, + int /* unsignedp */, tree parm) +{ + bool candidate_p = GET_MODE_CLASS (mode) == MODE_INT + && GET_MODE_CLASS (promoted_mode) == MODE_INT + && known_lt (GET_MODE_SIZE (mode), 4) + && promoted_mode == SImode; + + if (!candidate_p) + return false; + + if (!parm || !is_gimple_reg (parm)) + return true; + + tree var = parm; + if (!VAR_P (var)) + { + if (TREE_CODE (parm) == SSA_NAME + && !(var = SSA_NAME_VAR (var))) + return true; + else if (TREE_CODE (parm) != PARM_DECL) + return true; + } + + /* If the variable is used inside a comparison which sets CC then we should + still promote using an extend. By doing this we make it easier to use + cbz/cbnz but also repeatedly having to test the value in certain + circumstances like nested if values that test the same value with calls + in between. */ + tree ssa_var = ssa_default_def (cfun, var); + if (!ssa_var) + return true; + + const ssa_use_operand_t *const head = &(SSA_NAME_IMM_USE_NODE (ssa_var)); + const ssa_use_operand_t *ptr; + + for (ptr = head->next; ptr != head; ptr = ptr->next) + if (USE_STMT(ptr) && is_gimple_assign (USE_STMT (ptr))) + { + tree_code code = gimple_assign_rhs_code (USE_STMT(ptr)); + if (TREE_CODE_CLASS (code) == tcc_comparison) + return false; + } + + return true; +} + /* MODE is some form of SVE vector mode. For data modes, return the number of vector register bits that each element of MODE occupies, such as 64 for both VNx2DImode and VNx2SImode (where each 32-bit value is stored @@ -27490,6 +27541,10 @@ aarch64_libgcc_floating_mode_supported_p #undef TARGET_ARRAY_MODE_SUPPORTED_P #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p +#undef TARGET_PROMOTE_FUNCTION_ARGS_SUBREG_P +#define TARGET_PROMOTE_FUNCTION_ARGS_SUBREG_P \ + aarch64_promote_function_args_subreg_p + #undef TARGET_VECTORIZE_CREATE_COSTS #define TARGET_VECTORIZE_CREATE_COSTS aarch64_vectorize_create_costs diff --git a/gcc/testsuite/gcc.target/aarch64/apc-subreg.c b/gcc/testsuite/gcc.target/aarch64/apc-subreg.c new file mode 100644 index 0000000000000000000000000000000000000000..2d7563a11ce11fa677f7ad4bf2a090e6a136e4d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/apc-subreg.c @@ -0,0 +1,103 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +#include + +/* +** f0: +** mvn w0, w0 +** ret +*/ +uint8_t f0 (uint8_t xr){ + return (uint8_t) (0xff - xr); +} + +/* +** f1: +** mvn w0, w0 +** ret +*/ +int8_t f1 (int8_t xr){ + return (int8_t) (0xff - xr); +} + +/* +** f2: +** mvn w0, w0 +** ret +*/ +uint16_t f2 (uint16_t xr){ + return (uint16_t) (0xffFF - xr); +} + +/* +** f3: +** mvn w0, w0 +** ret +*/ +uint32_t f3 (uint32_t xr){ + return (uint32_t) (0xffFFffff - xr); +} + +/* +** f4: +** mvn x0, x0 +** ret +*/ +uint64_t f4 (uint64_t xr){ + return (uint64_t) (0xffFFffffffffffff - xr); +} + +/* +** f5: +** mvn w0, w0 +** sub w0, w0, w1 +** ret +*/ +uint8_t f5 (uint8_t xr, uint8_t xc){ + return (uint8_t) (0xff - xr - xc); +} + +/* +** f6: +** mvn w0, w0 +** and w0, w0, 255 +** and w1, w1, 255 +** mul w0, w0, w1 +** ret +*/ +uint16_t f6 (uint8_t xr, uint8_t xc){ + return ((uint8_t) (0xff - xr)) * xc; +} + +/* +** f7: +** and w0, w0, 255 +** and w1, w1, 255 +** mul w0, w0, w1 +** ret +*/ +uint16_t f7 (uint8_t xr, uint8_t xc){ + return xr * xc; +} + +/* +** f8: +** mul w0, w0, w1 +** and w0, w0, 255 +** ret +*/ +uint16_t f8 (uint8_t xr, uint8_t xc){ + return (uint8_t)(xr * xc); +} + +/* +** f9: +** and w0, w0, 255 +** add w0, w0, w1 +** ret +*/ +uint16_t f9 (uint8_t xr, uint16_t xc){ + return xr + xc; +} --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -34,7 +34,8 @@ #define REGISTER_TARGET_PRAGMAS() aarch64_register_pragmas () -/* Target machine storage layout. */ +/* Target machine storage layout. See also + TARGET_PROMOTE_FUNCTION_ARGS_SUBREG_P. */ #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ if (GET_MODE_CLASS (MODE) == MODE_INT \ diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 2f559600cff55af9d468e8d0810545583cc986f5..252d6c2af72afc1dfee1a86644a5753784b41f59 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -3736,6 +3736,57 @@ aarch64_array_mode_supported_p (machine_mode mode, return false; } +/* Implement target hook TARGET_PROMOTE_FUNCTION_ARGS_SUBREG_P to complement + PROMOTE_MODE. If any argument promotion was done, do them as subregs. */ +static bool +aarch64_promote_function_args_subreg_p (machine_mode mode, + machine_mode promoted_mode, + int /* unsignedp */, tree parm) +{ + bool candidate_p = GET_MODE_CLASS (mode) == MODE_INT + && GET_MODE_CLASS (promoted_mode) == MODE_INT + && known_lt (GET_MODE_SIZE (mode), 4) + && promoted_mode == SImode; + + if (!candidate_p) + return false; + + if (!parm || !is_gimple_reg (parm)) + return true; + + tree var = parm; + if (!VAR_P (var)) + { + if (TREE_CODE (parm) == SSA_NAME + && !(var = SSA_NAME_VAR (var))) + return true; + else if (TREE_CODE (parm) != PARM_DECL) + return true; + } + + /* If the variable is used inside a comparison which sets CC then we should + still promote using an extend. By doing this we make it easier to use + cbz/cbnz but also repeatedly having to test the value in certain + circumstances like nested if values that test the same value with calls + in between. */ + tree ssa_var = ssa_default_def (cfun, var); + if (!ssa_var) + return true; + + const ssa_use_operand_t *const head = &(SSA_NAME_IMM_USE_NODE (ssa_var)); + const ssa_use_operand_t *ptr; + + for (ptr = head->next; ptr != head; ptr = ptr->next) + if (USE_STMT(ptr) && is_gimple_assign (USE_STMT (ptr))) + { + tree_code code = gimple_assign_rhs_code (USE_STMT(ptr)); + if (TREE_CODE_CLASS (code) == tcc_comparison) + return false; + } + + return true; +} + /* MODE is some form of SVE vector mode. For data modes, return the number of vector register bits that each element of MODE occupies, such as 64 for both VNx2DImode and VNx2SImode (where each 32-bit value is stored @@ -27490,6 +27541,10 @@ aarch64_libgcc_floating_mode_supported_p #undef TARGET_ARRAY_MODE_SUPPORTED_P #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p +#undef TARGET_PROMOTE_FUNCTION_ARGS_SUBREG_P +#define TARGET_PROMOTE_FUNCTION_ARGS_SUBREG_P \ + aarch64_promote_function_args_subreg_p + #undef TARGET_VECTORIZE_CREATE_COSTS #define TARGET_VECTORIZE_CREATE_COSTS aarch64_vectorize_create_costs diff --git a/gcc/testsuite/gcc.target/aarch64/apc-subreg.c b/gcc/testsuite/gcc.target/aarch64/apc-subreg.c new file mode 100644 index 0000000000000000000000000000000000000000..2d7563a11ce11fa677f7ad4bf2a090e6a136e4d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/apc-subreg.c @@ -0,0 +1,103 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +#include + +/* +** f0: +** mvn w0, w0 +** ret +*/ +uint8_t f0 (uint8_t xr){ + return (uint8_t) (0xff - xr); +} + +/* +** f1: +** mvn w0, w0 +** ret +*/ +int8_t f1 (int8_t xr){ + return (int8_t) (0xff - xr); +} + +/* +** f2: +** mvn w0, w0 +** ret +*/ +uint16_t f2 (uint16_t xr){ + return (uint16_t) (0xffFF - xr); +} + +/* +** f3: +** mvn w0, w0 +** ret +*/ +uint32_t f3 (uint32_t xr){ + return (uint32_t) (0xffFFffff - xr); +} + +/* +** f4: +** mvn x0, x0 +** ret +*/ +uint64_t f4 (uint64_t xr){ + return (uint64_t) (0xffFFffffffffffff - xr); +} + +/* +** f5: +** mvn w0, w0 +** sub w0, w0, w1 +** ret +*/ +uint8_t f5 (uint8_t xr, uint8_t xc){ + return (uint8_t) (0xff - xr - xc); +} + +/* +** f6: +** mvn w0, w0 +** and w0, w0, 255 +** and w1, w1, 255 +** mul w0, w0, w1 +** ret +*/ +uint16_t f6 (uint8_t xr, uint8_t xc){ + return ((uint8_t) (0xff - xr)) * xc; +} + +/* +** f7: +** and w0, w0, 255 +** and w1, w1, 255 +** mul w0, w0, w1 +** ret +*/ +uint16_t f7 (uint8_t xr, uint8_t xc){ + return xr * xc; +} + +/* +** f8: +** mul w0, w0, w1 +** and w0, w0, 255 +** ret +*/ +uint16_t f8 (uint8_t xr, uint8_t xc){ + return (uint8_t)(xr * xc); +} + +/* +** f9: +** and w0, w0, 255 +** add w0, w0, w1 +** ret +*/ +uint16_t f9 (uint8_t xr, uint16_t xc){ + return xr + xc; +} From patchwork Fri May 13 17:12:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tamar Christina X-Patchwork-Id: 1630862 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=Af3a6NYH; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4L0FdB11Ltz9sFk for ; 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Bootstrapped Regtested on aarch64-none-linux-gnu and no issues and fixes 209 SVE xfails. Ok for master? Thanks, Tamar gcc/testsuite/ChangeLog: * gcc.target/aarch64/sve/acle/asm/abd_s16.c: Remove xfail. * gcc.target/aarch64/sve/acle/asm/abd_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/abd_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/abd_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/add_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/add_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/add_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/add_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/and_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/and_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/and_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/and_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/asr_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/asr_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/bic_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/bic_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/bic_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/bic_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/dot_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/dot_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/dot_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/dot_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/eor_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/eor_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/eor_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/eor_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsr_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsr_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mad_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mad_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mad_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mad_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/max_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/max_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/max_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/max_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/min_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/min_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/min_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/min_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mla_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mla_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mla_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mla_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mls_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mls_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mls_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mls_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/msb_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/msb_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/msb_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/msb_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mul_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mul_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mul_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mul_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mulh_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mulh_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mulh_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/mulh_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/orr_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/orr_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/orr_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/orr_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/scale_f16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/sub_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/sub_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/sub_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/sub_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/subr_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/subr_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/subr_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/subr_u8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/bcax_s16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/bcax_s8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/bcax_u16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/bcax_u8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qadd_s16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qadd_s8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qadd_u16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qadd_u8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qdmlalb_s16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qdmlalb_s32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qdmlalbt_s16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qdmlalbt_s32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qsub_s16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qsub_s8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qsub_u16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qsub_u8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qsubr_s16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qsubr_s8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qsubr_u16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/qsubr_u8.c: Likewise. --- inline copy of patch -- diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_s16.c index e2d0c0fb7ef3f9cd6f232bb5da7f5a46205a093f..030d952ecda6da44b2351d48daa850fc7b5033b7 100644 --- diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_s16.c index e2d0c0fb7ef3f9cd6f232bb5da7f5a46205a093f..030d952ecda6da44b2351d48daa850fc7b5033b7 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_s16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (abd_w0_s16_m_tied1, svint16_t, int16_t, z0 = svabd_m (p0, z0, x0)) /* -** abd_w0_s16_m_untied: { xfail *-*-* } +** abd_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** sabd z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_s8.c index 49a2cc388f960848e15680219c098fdd0ab21671..e1a74a16f6f745966889f90e82e4da473bd1e706 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_s8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (abd_w0_s8_m_tied1, svint8_t, int8_t, z0 = svabd_m (p0, z0, x0)) /* -** abd_w0_s8_m_untied: { xfail *-*-* } +** abd_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** sabd z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_u16.c index 60aa9429ea62b41c2ae098b4f2cf6c5357fdf9af..f763da3ec941d334009c1cfe6c80861e4d15cd33 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_u16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (abd_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = svabd_m (p0, z0, x0)) /* -** abd_w0_u16_m_untied: { xfail *-*-* } +** abd_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** uabd z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_u8.c index 454ef153cc3c51b3595525e76ea0a0d7ca70805b..f46f1943484f001a5e9babdba8cb8b9160fef314 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_u8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (abd_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = svabd_m (p0, z0, x0)) /* -** abd_w0_u8_m_untied: { xfail *-*-* } +** abd_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** uabd z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_s16.c index c0883edf9ab4eedf5dca5104e1443b614397cad5..7dd48c778634bd958445cf9bfa29e54fa38b3921 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_s16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (add_w0_s16_m_tied1, svint16_t, int16_t, z0 = svadd_m (p0, z0, x0)) /* -** add_w0_s16_m_untied: { xfail *-*-* } +** add_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** add z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_s8.c index 0889c189d59699e6fdbc1c91f8a36ab0f9296f52..6775f26cfb24dfaa1c5d60302ae5eb1766102def 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_s8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (add_w0_s8_m_tied1, svint8_t, int8_t, z0 = svadd_m (p0, z0, x0)) /* -** add_w0_s8_m_untied: { xfail *-*-* } +** add_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** add z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_u16.c index 25cb90353d3b852334885c6eb306bb2e97452c2e..f0fafdb1c2dc526f2b9199a451a62975111e53a8 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_u16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (add_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = svadd_m (p0, z0, x0)) /* -** add_w0_u16_m_untied: { xfail *-*-* } +** add_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** add z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_u8.c index 06b68c97ce8c84494c960f28b2ae4c5dcafd0d03..2bdb7a85f56a8c1969e9390b6ba7c0eb10336c97 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_u8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (add_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = svadd_m (p0, z0, x0)) /* -** add_w0_u8_m_untied: { xfail *-*-* } +** add_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** add z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_s16.c index d54613e915d221b02d957cf57c44d690328cb430..15e5d58334455a75a42eee29e2aaf1eb89e75acd 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_s16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (and_w0_s16_m_tied1, svint16_t, int16_t, z0 = svand_m (p0, z0, x0)) /* -** and_w0_s16_m_untied: { xfail *-*-* } +** and_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** and z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_s8.c index 61d168d3fdf8968295724cdb0e63fcb087d30d27..197c3011cee8d17725ed0e42557745325b4cfa2d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_s8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (and_w0_s8_m_tied1, svint8_t, int8_t, z0 = svand_m (p0, z0, x0)) /* -** and_w0_s8_m_untied: { xfail *-*-* } +** and_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** and z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_u16.c index 875a08d71d1822c54b3d549ce46e6c951ef38bc6..8210fba2f6382e493fba46f7b087b6de860f7f66 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_u16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (and_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = svand_m (p0, z0, x0)) /* -** and_w0_u16_m_untied: { xfail *-*-* } +** and_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** and z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_u8.c index b0f1c9529f05d614a1b37bdba68caf843ae12f65..5d3fd60382ffe4016f4539f347a1e34045a4e827 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_u8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (and_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = svand_m (p0, z0, x0)) /* -** and_w0_u8_m_untied: { xfail *-*-* } +** and_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** and z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asr_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asr_s16.c index 877bf10685a4b29cc0c6e067ce0cec61530df59f..f9ce790da95e655ac73389ccdc36b9e16cdfebb9 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asr_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asr_s16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (asr_w0_s16_m_tied1, svint16_t, uint16_t, z0 = svasr_m (p0, z0, x0)) /* -** asr_w0_s16_m_untied: { xfail *-*-* } +** asr_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** asr z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asr_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asr_s8.c index 992e93fdef7a6a425d247229ebc14801caf02ef0..5cf3a712c282534031e1dbf301f82058467da4ec 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asr_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asr_s8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (asr_w0_s8_m_tied1, svint8_t, uint8_t, z0 = svasr_m (p0, z0, x0)) /* -** asr_w0_s8_m_untied: { xfail *-*-* } +** asr_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** asr z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_s16.c index c80f5697f5f475cb052527b2a0af5c37b794ba3b..9cf22ebe7fc37a12f9ef3d0a5c76b9c7db82d0ae 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_s16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (bic_w0_s16_m_tied1, svint16_t, int16_t, z0 = svbic_m (p0, z0, x0)) /* -** bic_w0_s16_m_untied: { xfail *-*-* } +** bic_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** bic z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_s8.c index 0958a34039394d79ecd00ac3c855c01cecbce86a..6795716810c8ba79da1c4e96d8eeef1cfdd1dc40 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_s8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (bic_w0_s8_m_tied1, svint8_t, int8_t, z0 = svbic_m (p0, z0, x0)) /* -** bic_w0_s8_m_untied: { xfail *-*-* } +** bic_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** bic z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_u16.c index 30209ffb418f410094afd9df594dad98aa380a5d..5409954caff45d6c12bd13c4e090712f72e8da0e 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_u16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (bic_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = svbic_m (p0, z0, x0)) /* -** bic_w0_u16_m_untied: { xfail *-*-* } +** bic_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** bic z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_u8.c index 80c489b9cdb2b6c6dfd3ab5377bc902f8ef86f6d..a0fbae4796259694b6918a88d9743c4edb9f390d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_u8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (bic_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = svbic_m (p0, z0, x0)) /* -** bic_w0_u8_m_untied: { xfail *-*-* } +** bic_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** bic z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_s32.c index 605bd1b30f25f4b2b2bb9e923a9e7dfee8784b07..e9603adf20b79bb96cb1f8ea7e804c308212b319 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_s32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_s32.c @@ -54,7 +54,7 @@ TEST_DUAL_ZX (dot_w0_s32_tied1, svint32_t, svint8_t, int8_t, z0 = svdot (z0, z4, x0)) /* -** dot_w0_s32_untied: { xfail *-*-* } +** dot_w0_s32_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** sdot z0\.s, z4\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_s64.c index b6574740b7e7a9a9ff5f79568d8590d2744ad7a4..7a13c62c535150d827e4247de3151588e61d9e68 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_s64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_s64.c @@ -54,7 +54,7 @@ TEST_DUAL_ZX (dot_w0_s64_tied1, svint64_t, svint16_t, int16_t, z0 = svdot (z0, z4, x0)) /* -** dot_w0_s64_untied: { xfail *-*-* } +** dot_w0_s64_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** sdot z0\.d, z4\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_u32.c index 541e71cc212e7ce0d96a550c373c4c30a0db58ea..e46cac469d98fc59408296676566c61f88fc1c77 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_u32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_u32.c @@ -54,7 +54,7 @@ TEST_DUAL_ZX (dot_w0_u32_tied1, svuint32_t, svuint8_t, uint8_t, z0 = svdot (z0, z4, x0)) /* -** dot_w0_u32_untied: { xfail *-*-* } +** dot_w0_u32_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** udot z0\.s, z4\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_u64.c index cc0e853737df001f4d46c0a12edad45dd568f745..67576c8da171ff61bb32db4f89b2dd3074be48e0 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_u64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_u64.c @@ -54,7 +54,7 @@ TEST_DUAL_ZX (dot_w0_u64_tied1, svuint64_t, svuint16_t, uint16_t, z0 = svdot (z0, z4, x0)) /* -** dot_w0_u64_untied: { xfail *-*-* } +** dot_w0_u64_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** udot z0\.d, z4\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_s16.c index 7cf73609a1aa188e0385838803fe75f45014a1bc..123cdfb0a7a74be73be8bea5b21ec2593a21f96a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_s16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (eor_w0_s16_m_tied1, svint16_t, int16_t, z0 = sveor_m (p0, z0, x0)) /* -** eor_w0_s16_m_untied: { xfail *-*-* } +** eor_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** eor z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_s8.c index 083ac2dde06e43dbdcdcf441c7d50ea77ac5c9cd..5da5908ac36bb729564e2e810a43965bd0913be3 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_s8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (eor_w0_s8_m_tied1, svint8_t, int8_t, z0 = sveor_m (p0, z0, x0)) /* -** eor_w0_s8_m_untied: { xfail *-*-* } +** eor_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** eor z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_u16.c index 40b43a5f89b480a6286c1fcc0746375eb8031914..b3c2e0c4e0b4320653b663f55246e9aa59afa722 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_u16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (eor_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = sveor_m (p0, z0, x0)) /* -** eor_w0_u16_m_untied: { xfail *-*-* } +** eor_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** eor z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_u8.c index 006637699e8b199aad22112b72d748c04f8f5257..021af308174b1d5e0003e7a2960cc821739c4aab 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_u8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (eor_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = sveor_m (p0, z0, x0)) /* -** eor_w0_u8_m_untied: { xfail *-*-* } +** eor_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** eor z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s16.c index edaaca5f155b9af6cd7dd1d15ff94e86c82c486f..67db99697ee88367f8393f9580b4cc11655c2327 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (lsl_w0_s16_m_tied1, svint16_t, uint16_t, z0 = svlsl_m (p0, z0, x0)) /* -** lsl_w0_s16_m_untied: { xfail *-*-* } +** lsl_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** lsl z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s8.c index 9a9cc959c33da729324920a6946c15cb6ba099bd..67a09a745e24e08c29bdbadde1b2f9640683a1d0 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (lsl_w0_s8_m_tied1, svint8_t, uint8_t, z0 = svlsl_m (p0, z0, x0)) /* -** lsl_w0_s8_m_untied: { xfail *-*-* } +** lsl_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** lsl z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u16.c index 57db0fda66af3d642eeacd22ec3bd48c94b34048..b5e7386ce632a672b49b4bc05d8380fbc62bc0bb 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (lsl_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = svlsl_m (p0, z0, x0)) /* -** lsl_w0_u16_m_untied: { xfail *-*-* } +** lsl_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** lsl z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u8.c index 894b5513857b5949a6942156148778a9ae9cadbe..905bf9ed1692ab596af0237a7b33fa40bca24ddd 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (lsl_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = svlsl_m (p0, z0, x0)) /* -** lsl_w0_u8_m_untied: { xfail *-*-* } +** lsl_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** lsl z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsr_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsr_u16.c index 61575645fad086970193875926d051ecc6482ef6..a41411986f798e251e73915542f999f8468fd2eb 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsr_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsr_u16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (lsr_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = svlsr_m (p0, z0, x0)) /* -** lsr_w0_u16_m_untied: { xfail *-*-* } +** lsr_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** lsr z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsr_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsr_u8.c index a049ca90556e5daa42a928a82a1a704803194cd6..b773eedba7fe5b4e390170076a32d9281527d690 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsr_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsr_u8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (lsr_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = svlsr_m (p0, z0, x0)) /* -** lsr_w0_u8_m_untied: { xfail *-*-* } +** lsr_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** lsr z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_s16.c index 02a6d4588b85f315e8e695b196db8bbf5c214454..bb6e0ea31c521dfb8199aff6409b56335d492320 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_s16.c @@ -54,7 +54,7 @@ TEST_UNIFORM_ZX (mad_w0_s16_m_tied1, svint16_t, int16_t, z0 = svmad_m (p0, z0, z1, x0)) /* -** mad_w0_s16_m_untied: { xfail *-*-* } +** mad_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** mad z0\.h, p0/m, z2\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_s8.c index 90d712686ca5ab9752c245dcf2ae4230546fd9fc..adc6972a7dca903a148e83b649140f8b97f10eee 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_s8.c @@ -54,7 +54,7 @@ TEST_UNIFORM_ZX (mad_w0_s8_m_tied1, svint8_t, int8_t, z0 = svmad_m (p0, z0, z1, x0)) /* -** mad_w0_s8_m_untied: { xfail *-*-* } +** mad_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** mad z0\.b, p0/m, z2\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_u16.c index 1d2ad9c5fc9d972c08bbf690b1fb4fb4d26c6f29..5b3c390b14c8b26b268cad5b364ac32a13a502b5 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_u16.c @@ -54,7 +54,7 @@ TEST_UNIFORM_ZX (mad_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = svmad_m (p0, z0, z1, x0)) /* -** mad_w0_u16_m_untied: { xfail *-*-* } +** mad_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** mad z0\.h, p0/m, z2\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_u8.c index 0b4b1b8cfe6e3b00eb4b1fe0516ca84fd2418aa0..a23c813f18f1a82b9dca777a84d44c2d2993c6ce 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_u8.c @@ -54,7 +54,7 @@ TEST_UNIFORM_ZX (mad_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = svmad_m (p0, z0, z1, x0)) /* -** mad_w0_u8_m_untied: { xfail *-*-* } +** mad_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** mad z0\.b, p0/m, z2\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_s16.c index 6a21675228274043ec4ed46405964015a9f34744..d5f5e6e629dcadf40618dd7156a39fda36b3896a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_s16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (max_w0_s16_m_tied1, svint16_t, int16_t, z0 = svmax_m (p0, z0, x0)) /* -** max_w0_s16_m_untied: { xfail *-*-* } +** max_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** smax z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_s8.c index c651a26f0d1a92bdaca0ea7260421a6e251e2622..e23dbeeec6b33ef8f28ddde8a52af1e1cbb3e815 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_s8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (max_w0_s8_m_tied1, svint8_t, int8_t, z0 = svmax_m (p0, z0, x0)) /* -** max_w0_s8_m_untied: { xfail *-*-* } +** max_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** smax z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_u16.c index 9a0b9543169d9a626e20009a8a838ba16fd6c48c..9ad6705ab703b204a78b07174590cbaa8813731d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_u16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (max_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = svmax_m (p0, z0, x0)) /* -** max_w0_u16_m_untied: { xfail *-*-* } +** max_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** umax z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_u8.c index 04c9ddb36a23c13e345781c04c3ef566e9c0f2af..6326891f68005c6223afe0c1f24ffa1b81d059e3 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_u8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (max_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = svmax_m (p0, z0, x0)) /* -** max_w0_u8_m_untied: { xfail *-*-* } +** max_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** umax z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_s16.c index 14dfcc4c333b69fe24a4a9f978c02999f8abffce..1cf12277add40827921a4a1004d59e6706977acf 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_s16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (min_w0_s16_m_tied1, svint16_t, int16_t, z0 = svmin_m (p0, z0, x0)) /* -** min_w0_s16_m_untied: { xfail *-*-* } +** min_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** smin z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_s8.c index 714b1576d5c6fa27d2648c2db0e38076aeb266c0..4edc0b72fadbbe508d7b9666f6d438163eb8c2cb 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_s8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (min_w0_s8_m_tied1, svint8_t, int8_t, z0 = svmin_m (p0, z0, x0)) /* -** min_w0_s8_m_untied: { xfail *-*-* } +** min_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** smin z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_u16.c index df35cf1135ec0fcf7a6528f78657271b95b8defc..2147f96d09f251703845745f2fbe505793bf51cd 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_u16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (min_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = svmin_m (p0, z0, x0)) /* -** min_w0_u16_m_untied: { xfail *-*-* } +** min_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** umin z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_u8.c index 2ca274278a29a0e16e0756a5015f438bfa90f839..734925e6ea348316ee8cf6a3b9356f38c2f819ea 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_u8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (min_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = svmin_m (p0, z0, x0)) /* -** min_w0_u8_m_untied: { xfail *-*-* } +** min_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** umin z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_s16.c index f3ed191db6abe5947313cf9cc9259735f39aa789..c016acd816290082b4dde6b83ca4f7c74f975ae0 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_s16.c @@ -54,7 +54,7 @@ TEST_UNIFORM_ZX (mla_w0_s16_m_tied1, svint16_t, int16_t, z0 = svmla_m (p0, z0, z1, x0)) /* -** mla_w0_s16_m_untied: { xfail *-*-* } +** mla_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** mla z0\.h, p0/m, z2\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_s8.c index 47468947d78b686ee83a309ad7ff2f31deed5872..ccbf145850acf927ebdc02ad950bd518606eb79d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_s8.c @@ -54,7 +54,7 @@ TEST_UNIFORM_ZX (mla_w0_s8_m_tied1, svint8_t, int8_t, z0 = svmla_m (p0, z0, z1, x0)) /* -** mla_w0_s8_m_untied: { xfail *-*-* } +** mla_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** mla z0\.b, p0/m, z2\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_u16.c index 7238e428f68668c23ef46d62a6bfb036bc669641..c3121bb761261c1acf632709ff4836b2fd4e5692 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_u16.c @@ -54,7 +54,7 @@ TEST_UNIFORM_ZX (mla_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = svmla_m (p0, z0, z1, x0)) /* -** mla_w0_u16_m_untied: { xfail *-*-* } +** mla_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** mla z0\.h, p0/m, z2\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_u8.c index 832ed41410e39b1c0e554799d9d881357939ab1c..ecc70274cb6e452b1576d02968b8afe5a7dc7fac 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_u8.c @@ -54,7 +54,7 @@ TEST_UNIFORM_ZX (mla_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = svmla_m (p0, z0, z1, x0)) /* -** mla_w0_u8_m_untied: { xfail *-*-* } +** mla_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** mla z0\.b, p0/m, z2\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_s16.c index e199829c4adc8da64824e5523e77a02b1dc0acf4..7be0a4128f6165a65ef2a2f2defb659c50d64b45 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_s16.c @@ -54,7 +54,7 @@ TEST_UNIFORM_ZX (mls_w0_s16_m_tied1, svint16_t, int16_t, z0 = svmls_m (p0, z0, z1, x0)) /* -** mls_w0_s16_m_untied: { xfail *-*-* } +** mls_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** mls z0\.h, p0/m, z2\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_s8.c index c60c431455f099fc45e5ad2a026a72a6f7ae3eb9..fc3a65c7a0944e5c6865a2ddb899a06d15b21976 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_s8.c @@ -54,7 +54,7 @@ TEST_UNIFORM_ZX (mls_w0_s8_m_tied1, svint8_t, int8_t, z0 = svmls_m (p0, z0, z1, x0)) /* -** mls_w0_s8_m_untied: { xfail *-*-* } +** mls_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** mls z0\.b, p0/m, z2\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_u16.c index e8a9f5cd94c6d823f988915373bfa5eebbc44c45..10779fb6674aefef7bcbd209dbc94ec3badb4801 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_u16.c @@ -54,7 +54,7 @@ TEST_UNIFORM_ZX (mls_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = svmls_m (p0, z0, z1, x0)) /* -** mls_w0_u16_m_untied: { xfail *-*-* } +** mls_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** mls z0\.h, p0/m, z2\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_u8.c index 0489aaa7cf96af5d0d02233f813b0b95119b1169..c9277e11cb5cefbe43511da5e01a74aa5f7eac6c 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_u8.c @@ -54,7 +54,7 @@ TEST_UNIFORM_ZX (mls_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = svmls_m (p0, z0, z1, x0)) /* -** mls_w0_u8_m_untied: { xfail *-*-* } +** mls_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** mls z0\.b, p0/m, z2\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_s16.c index 56347cfb91828d45f5609c030e0869c650c5fd2f..52f3721c93633568f390cc6b7196af38a715b844 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_s16.c @@ -54,7 +54,7 @@ TEST_UNIFORM_ZX (msb_w0_s16_m_tied1, svint16_t, int16_t, z0 = svmsb_m (p0, z0, z1, x0)) /* -** msb_w0_s16_m_untied: { xfail *-*-* } +** msb_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** msb z0\.h, p0/m, z2\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_s8.c index d7fcafdd0dfab6f4b1f7da8551570ab898ca2eab..381773c4a2b43538a336a63a36f4d3307e0e405f 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_s8.c @@ -54,7 +54,7 @@ TEST_UNIFORM_ZX (msb_w0_s8_m_tied1, svint8_t, int8_t, z0 = svmsb_m (p0, z0, z1, x0)) /* -** msb_w0_s8_m_untied: { xfail *-*-* } +** msb_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** msb z0\.b, p0/m, z2\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_u16.c index 437a96040e12ca2dc83d8dc56ff2dbf14d3728ba..3b710f72c2dcce03df64634b35a5838330eda410 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_u16.c @@ -54,7 +54,7 @@ TEST_UNIFORM_ZX (msb_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = svmsb_m (p0, z0, z1, x0)) /* -** msb_w0_u16_m_untied: { xfail *-*-* } +** msb_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** msb z0\.h, p0/m, z2\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_u8.c index 5665ec9e32075c0d8a9665ab624c4dfde2042d5a..a0e86c799183d758a5be4a5116c592aba9d50021 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_u8.c @@ -54,7 +54,7 @@ TEST_UNIFORM_ZX (msb_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = svmsb_m (p0, z0, z1, x0)) /* -** msb_w0_u8_m_untied: { xfail *-*-* } +** msb_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** msb z0\.b, p0/m, z2\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s16.c index aa08bc2740507c7df20a31acea455b61e937ae4e..52c6767ede0df73ac5b5a7c32c283c13f46d1c85 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (mul_w0_s16_m_tied1, svint16_t, int16_t, z0 = svmul_m (p0, z0, x0)) /* -** mul_w0_s16_m_untied: { xfail *-*-* } +** mul_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** mul z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s8.c index 012e6f250989dd0965b72bbec26d05facf0d6bda..5fc9d93b2b4567f381521c63d9b174cdd4dea1e0 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (mul_w0_s8_m_tied1, svint8_t, int8_t, z0 = svmul_m (p0, z0, x0)) /* -** mul_w0_s8_m_untied: { xfail *-*-* } +** mul_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** mul z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u16.c index 300987eb6e63677a0fa5e0f2b99f39700f9520bb..b081d230be3ed49044c506da156bc00bbaeb28a6 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (mul_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = svmul_m (p0, z0, x0)) /* -** mul_w0_u16_m_untied: { xfail *-*-* } +** mul_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** mul z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u8.c index b2745a48f506cabee8fe9d952c7d89fa8eabdd45..e02be8b343e4e02d765bfea3a55e5f2f43345867 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (mul_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = svmul_m (p0, z0, x0)) /* -** mul_w0_u8_m_untied: { xfail *-*-* } +** mul_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** mul z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_s16.c index a81532f5d8987dc2405cf0a51ca476052f5b984e..3cd3a2477052ad17c435a9bcb0db92789a2b8611 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_s16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (mulh_w0_s16_m_tied1, svint16_t, int16_t, z0 = svmulh_m (p0, z0, x0)) /* -** mulh_w0_s16_m_untied: { xfail *-*-* } +** mulh_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** smulh z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_s8.c index f9cd01afdc964f89e6fd24a057aa17f69bb3172c..08ead93a80da38a9df5dc770141f84a23e5ac1a6 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_s8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (mulh_w0_s8_m_tied1, svint8_t, int8_t, z0 = svmulh_m (p0, z0, x0)) /* -** mulh_w0_s8_m_untied: { xfail *-*-* } +** mulh_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** smulh z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_u16.c index e9173eb243ec9c2514809fd0bdf208a7811377a8..01a0de738bb980adfcd0394ca221fe765fb8207c 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_u16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (mulh_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = svmulh_m (p0, z0, x0)) /* -** mulh_w0_u16_m_untied: { xfail *-*-* } +** mulh_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** umulh z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_u8.c index db7b1be1bdf92ec534ae8d467cb44d0df380423a..ce547ffbe2b6ced08ad52f366800f68c7bda9dfb 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_u8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (mulh_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = svmulh_m (p0, z0, x0)) /* -** mulh_w0_u8_m_untied: { xfail *-*-* } +** mulh_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** umulh z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_s16.c index 62b707a9c696164ec1da32daac76182f3dbcf1fa..c0a3aaf3dfe6b7bf29dfdf91a16b16e64d4b966a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_s16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (orr_w0_s16_m_tied1, svint16_t, int16_t, z0 = svorr_m (p0, z0, x0)) /* -** orr_w0_s16_m_untied: { xfail *-*-* } +** orr_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** orr z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_s8.c index b6483b6e76ec82e0e6e99e701271fb2fe3d507b5..96c265d856ab5aba848a04c44c1ebc2db790e21d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_s8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (orr_w0_s8_m_tied1, svint8_t, int8_t, z0 = svorr_m (p0, z0, x0)) /* -** orr_w0_s8_m_untied: { xfail *-*-* } +** orr_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** orr z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_u16.c index 000a0444c9b08f8c17bc44183381f57c5136081a..8757ff18499b28fd4e3156abfa9e331058b895a8 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_u16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (orr_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = svorr_m (p0, z0, x0)) /* -** orr_w0_u16_m_untied: { xfail *-*-* } +** orr_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** orr z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_u8.c index efe5591b47287412ec558ece8a9449302b9df31d..c9701f2c3492520f15c369ca74b60a2c370b78f2 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_u8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (orr_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = svorr_m (p0, z0, x0)) /* -** orr_w0_u8_m_untied: { xfail *-*-* } +** orr_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** orr z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/scale_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/scale_f16.c index 9c554255b443844d04427ce5777264921a3c5f61..50a718d46cf772ec12697d14bee61a3dfb59f6ec 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/scale_f16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/scale_f16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (scale_w0_f16_m_tied1, svfloat16_t, int16_t, z0 = svscale_m (p0, z0, x0)) /* -** scale_w0_f16_m_untied: { xfail *-*-* } +** scale_w0_f16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** fscale z0\.h, p0/m, z0\.h, \1 @@ -211,7 +211,7 @@ TEST_UNIFORM_ZX (scale_w0_f16_x_tied1, svfloat16_t, int16_t, z0 = svscale_x (p0, z0, x0)) /* -** scale_w0_f16_x_untied: { xfail *-*-* } +** scale_w0_f16_x_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** fscale z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_s16.c index aea8ea2b4aa545b5e1dc0416f972a2dfec512ba4..fcab3a87162d5df76371166951efb18fde493e55 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_s16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (sub_w0_s16_m_tied1, svint16_t, int16_t, z0 = svsub_m (p0, z0, x0)) /* -** sub_w0_s16_m_untied: { xfail *-*-* } +** sub_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** sub z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_s8.c index 0d7ba99aa5695c97e74ffc729dc01a96d2fbeec5..4de12f0b387d9d595c5bc4043018aaabdd643425 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_s8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (sub_w0_s8_m_tied1, svint8_t, int8_t, z0 = svsub_m (p0, z0, x0)) /* -** sub_w0_s8_m_untied: { xfail *-*-* } +** sub_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** sub z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_u16.c index 89620e159bf3b55a88c00900c901cafb547510b1..d682efa93eac4c97984e75d302268c2b478e07b9 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_u16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (sub_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = svsub_m (p0, z0, x0)) /* -** sub_w0_u16_m_untied: { xfail *-*-* } +** sub_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** sub z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_u8.c index 4552041910f7e86cbe896c04971da1b974a5eda0..39bc519c642585eba13fda8edd8060dff5627371 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_u8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (sub_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = svsub_m (p0, z0, x0)) /* -** sub_w0_u8_m_untied: { xfail *-*-* } +** sub_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** sub z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_s16.c index d3dad62dafeb93db1f2a309e4f4caab967a6dedd..ad6f4519e536adab2c45ad015b922d4c96714ab7 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_s16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (subr_w0_s16_m_tied1, svint16_t, int16_t, z0 = svsubr_m (p0, z0, x0)) /* -** subr_w0_s16_m_untied: { xfail *-*-* } +** subr_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** subr z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_s8.c index 90d2a6de9a5fc935fd134c459b89829a933f116d..c31948202e2405990d0c6c99bd11fcb564983cc9 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_s8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (subr_w0_s8_m_tied1, svint8_t, int8_t, z0 = svsubr_m (p0, z0, x0)) /* -** subr_w0_s8_m_untied: { xfail *-*-* } +** subr_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** subr z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_u16.c index 379a80fb189796f747c92948d33ff3bf8cf6d0a7..631593aad78af792659842fd635b3335ea439366 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_u16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (subr_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = svsubr_m (p0, z0, x0)) /* -** subr_w0_u16_m_untied: { xfail *-*-* } +** subr_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** subr z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_u8.c index fe5f96da833565d6013383281e14005f380410ba..b9ab757ca81b75d1d76fc969982e078db76b8a28 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_u8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (subr_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = svsubr_m (p0, z0, x0)) /* -** subr_w0_u8_m_untied: { xfail *-*-* } +** subr_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** subr z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bcax_s16.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bcax_s16.c index acad87d963540c6cbf3df1a929ac368c754007a7..2fb2bdff574222033b090498b93b99efae68073e 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bcax_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bcax_s16.c @@ -66,7 +66,7 @@ TEST_UNIFORM_ZX (bcax_w0_s16_tied2, svint16_t, int16_t, z0 = svbcax (z1, z0, x0)) /* -** bcax_w0_s16_untied: { xfail *-*-*} +** bcax_w0_s16_untied: ** mov (z[0-9]+)\.h, w0 ** movprfx z0, z1 ** bcax z0\.d, z0\.d, (z2\.d, \1\.d|\1\.d, z2\.d) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bcax_s8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bcax_s8.c index 548aafad85739d8420bd2c14bb877f14d8e755bc..3925f56ff20ca9db559a338587e1f19db8e9a0a6 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bcax_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bcax_s8.c @@ -66,7 +66,7 @@ TEST_UNIFORM_ZX (bcax_w0_s8_tied2, svint8_t, int8_t, z0 = svbcax (z1, z0, x0)) /* -** bcax_w0_s8_untied: { xfail *-*-*} +** bcax_w0_s8_untied: ** mov (z[0-9]+)\.b, w0 ** movprfx z0, z1 ** bcax z0\.d, z0\.d, (z2\.d, \1\.d|\1\.d, z2\.d) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bcax_u16.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bcax_u16.c index b63a4774ba73e5df19fcc5190483a3fda4092598..589e868b205c492b510aafd21d77bb187d35429d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bcax_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bcax_u16.c @@ -66,7 +66,7 @@ TEST_UNIFORM_ZX (bcax_w0_u16_tied2, svuint16_t, uint16_t, z0 = svbcax (z1, z0, x0)) /* -** bcax_w0_u16_untied: { xfail *-*-*} +** bcax_w0_u16_untied: ** mov (z[0-9]+)\.h, w0 ** movprfx z0, z1 ** bcax z0\.d, z0\.d, (z2\.d, \1\.d|\1\.d, z2\.d) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bcax_u8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bcax_u8.c index 0957d58bd0ecd348ea4148ce84e05ffcb2848bcd..ee0b603830b702fd7e99723d129e5369ded0ab9a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bcax_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bcax_u8.c @@ -66,7 +66,7 @@ TEST_UNIFORM_ZX (bcax_w0_u8_tied2, svuint8_t, uint8_t, z0 = svbcax (z1, z0, x0)) /* -** bcax_w0_u8_untied: { xfail *-*-*} +** bcax_w0_u8_untied: ** mov (z[0-9]+)\.b, w0 ** movprfx z0, z1 ** bcax z0\.d, z0\.d, (z2\.d, \1\.d|\1\.d, z2\.d) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qadd_s16.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qadd_s16.c index 6330c4265bb17b80f12a884e663db342b9c346b2..286f2e2b969139106f8a38b41b42097c9a79c276 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qadd_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qadd_s16.c @@ -163,7 +163,7 @@ TEST_UNIFORM_ZX (qadd_w0_s16_m_tied1, svint16_t, int16_t, z0 = svqadd_m (p0, z0, x0)) /* -** qadd_w0_s16_m_untied: { xfail *-*-* } +** qadd_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** sqadd z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qadd_s8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qadd_s8.c index 61343beacb899b843c2358b609cc26a1ca1110a3..ad439892a6749aa3d346424f8b2aebcd4bd4762c 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qadd_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qadd_s8.c @@ -163,7 +163,7 @@ TEST_UNIFORM_ZX (qadd_w0_s8_m_tied1, svint8_t, int8_t, z0 = svqadd_m (p0, z0, x0)) /* -** qadd_w0_s8_m_untied: { xfail *-*-* } +** qadd_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** sqadd z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qadd_u16.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qadd_u16.c index f6c7ca9e075b7106209b858763a0cec160210ddf..9dafc3617ef84cf5a6ac13ad532a0e63065c7409 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qadd_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qadd_u16.c @@ -166,7 +166,7 @@ TEST_UNIFORM_ZX (qadd_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = svqadd_m (p0, z0, x0)) /* -** qadd_w0_u16_m_untied: { xfail *-*-* } +** qadd_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** uqadd z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qadd_u8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qadd_u8.c index 6c856e2871c26e1fbfa32c4e37df60c8884e76dd..a485cf3eeb656dded02c7eba8944757d164fbf6c 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qadd_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qadd_u8.c @@ -163,7 +163,7 @@ TEST_UNIFORM_ZX (qadd_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = svqadd_m (p0, z0, x0)) /* -** qadd_w0_u8_m_untied: { xfail *-*-* } +** qadd_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** uqadd z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qdmlalb_s16.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qdmlalb_s16.c index 4d1e90395e212b323f304f837504f2d8b158afc8..4880a6940d2981dd37b049431a68c326264c9503 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qdmlalb_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qdmlalb_s16.c @@ -54,7 +54,7 @@ TEST_DUAL_ZX (qdmlalb_w0_s16_tied1, svint16_t, svint8_t, int8_t, z0 = svqdmlalb (z0, z4, x0)) /* -** qdmlalb_w0_s16_untied: { xfail *-*-* } +** qdmlalb_w0_s16_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** sqdmlalb z0\.h, z4\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qdmlalb_s32.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qdmlalb_s32.c index 94373773e61e3ad6ce0ff5c2a7fda38f8e2086cb..03eebba5997c583768253586c252ec13c939b890 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qdmlalb_s32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qdmlalb_s32.c @@ -54,7 +54,7 @@ TEST_DUAL_ZX (qdmlalb_w0_s32_tied1, svint32_t, svint16_t, int16_t, z0 = svqdmlalb (z0, z4, x0)) /* -** qdmlalb_w0_s32_untied: { xfail *-*-* } +** qdmlalb_w0_s32_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** sqdmlalb z0\.s, z4\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qdmlalbt_s16.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qdmlalbt_s16.c index d591db3cfb8da203395b3b5e2955805381a3e4f3..0b3d5279db96bd7a39f286c6c5b37d9e1dea7d5a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qdmlalbt_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qdmlalbt_s16.c @@ -54,7 +54,7 @@ TEST_DUAL_ZX (qdmlalbt_w0_s16_tied1, svint16_t, svint8_t, int8_t, z0 = svqdmlalbt (z0, z4, x0)) /* -** qdmlalbt_w0_s16_untied: { xfail *-*-*} +** qdmlalbt_w0_s16_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** sqdmlalbt z0\.h, z4\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qdmlalbt_s32.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qdmlalbt_s32.c index e8326fed6171531cad3dd1c8c921d89bc1f29ce9..9f2dd464e638d8dbe7d15b1fa1c1538aef18169a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qdmlalbt_s32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qdmlalbt_s32.c @@ -54,7 +54,7 @@ TEST_DUAL_ZX (qdmlalbt_w0_s32_tied1, svint32_t, svint16_t, int16_t, z0 = svqdmlalbt (z0, z4, x0)) /* -** qdmlalbt_w0_s32_untied: { xfail *-*-*} +** qdmlalbt_w0_s32_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** sqdmlalbt z0\.s, z4\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsub_s16.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsub_s16.c index c102e58ed910c07aef6bee739f45fb96dd5aed80..618a61bf48fd912014b59874372e8d22eb7ee325 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsub_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsub_s16.c @@ -163,7 +163,7 @@ TEST_UNIFORM_ZX (qsub_w0_s16_m_tied1, svint16_t, int16_t, z0 = svqsub_m (p0, z0, x0)) /* -** qsub_w0_s16_m_untied: { xfail *-*-* } +** qsub_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** sqsub z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsub_s8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsub_s8.c index 067ee6e6cb1026fc7691268c47d318f4e67aa66c..f0d6b97bf97cb511e3e3a8c1d01948bbe28e393d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsub_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsub_s8.c @@ -163,7 +163,7 @@ TEST_UNIFORM_ZX (qsub_w0_s8_m_tied1, svint8_t, int8_t, z0 = svqsub_m (p0, z0, x0)) /* -** qsub_w0_s8_m_untied: { xfail *-*-* } +** qsub_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** sqsub z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsub_u16.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsub_u16.c index 61be74634723fe1cac7a5c2e38b5d5e72d73dd84..3e87dd162bfe0494d060098c0640094591ef6072 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsub_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsub_u16.c @@ -166,7 +166,7 @@ TEST_UNIFORM_ZX (qsub_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = svqsub_m (p0, z0, x0)) /* -** qsub_w0_u16_m_untied: { xfail *-*-* } +** qsub_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** uqsub z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsub_u8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsub_u8.c index 686b2b425fb5f0ff9439571f7c518aa4b2e43167..92bf92909a7874a8bb4e073250b9f71e1bc82ebe 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsub_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsub_u8.c @@ -163,7 +163,7 @@ TEST_UNIFORM_ZX (qsub_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = svqsub_m (p0, z0, x0)) /* -** qsub_w0_u8_m_untied: { xfail *-*-* } +** qsub_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** uqsub z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsubr_s16.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsubr_s16.c index 577310d9614be6f063e473eb2d1b6be7aebf4cc2..e42821849b266391555d39773efa6f072bfa810c 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsubr_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsubr_s16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (qsubr_w0_s16_m_tied1, svint16_t, int16_t, z0 = svqsubr_m (p0, z0, x0)) /* -** qsubr_w0_s16_m_untied: { xfail *-*-* } +** qsubr_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** sqsubr z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsubr_s8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsubr_s8.c index ce814a8393e94f50ecff8869649bf0acbb8eeb7e..92e66f70cbfdb066be1e2b5a745f57dff0b85c43 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsubr_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsubr_s8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (qsubr_w0_s8_m_tied1, svint8_t, int8_t, z0 = svqsubr_m (p0, z0, x0)) /* -** qsubr_w0_s8_m_untied: { xfail *-*-* } +** qsubr_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** sqsubr z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsubr_u16.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsubr_u16.c index f406bf2ed86c606bd984671b30c925b1c1233fd4..8018fdaef9e3d2a99a916aeae114ad273ea8ee92 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsubr_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsubr_u16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (qsubr_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = svqsubr_m (p0, z0, x0)) /* -** qsubr_w0_u16_m_untied: { xfail *-*-* } +** qsubr_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** uqsubr z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsubr_u8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsubr_u8.c index 7b487fd93b19d4ad620541069759fd0b05564b1c..bb29faa83504c4d1d0df942dfba2ed936c3986a1 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsubr_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsubr_u8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (qsubr_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = svqsubr_m (p0, z0, x0)) /* -** qsubr_w0_u8_m_untied: { xfail *-*-* } +** qsubr_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** uqsubr z0\.b, p0/m, z0\.b, \1 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_s16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (abd_w0_s16_m_tied1, svint16_t, int16_t, z0 = svabd_m (p0, z0, x0)) /* -** abd_w0_s16_m_untied: { xfail *-*-* } +** abd_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** sabd z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_s8.c index 49a2cc388f960848e15680219c098fdd0ab21671..e1a74a16f6f745966889f90e82e4da473bd1e706 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_s8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (abd_w0_s8_m_tied1, svint8_t, int8_t, z0 = svabd_m (p0, z0, x0)) /* -** abd_w0_s8_m_untied: { xfail *-*-* } +** abd_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** sabd z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_u16.c index 60aa9429ea62b41c2ae098b4f2cf6c5357fdf9af..f763da3ec941d334009c1cfe6c80861e4d15cd33 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_u16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (abd_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = svabd_m (p0, z0, x0)) /* -** abd_w0_u16_m_untied: { xfail *-*-* } +** abd_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** uabd z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_u8.c index 454ef153cc3c51b3595525e76ea0a0d7ca70805b..f46f1943484f001a5e9babdba8cb8b9160fef314 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abd_u8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (abd_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = svabd_m (p0, z0, x0)) /* -** abd_w0_u8_m_untied: { xfail *-*-* } +** abd_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** uabd z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_s16.c index c0883edf9ab4eedf5dca5104e1443b614397cad5..7dd48c778634bd958445cf9bfa29e54fa38b3921 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_s16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (add_w0_s16_m_tied1, svint16_t, int16_t, z0 = svadd_m (p0, z0, x0)) /* -** add_w0_s16_m_untied: { xfail *-*-* } +** add_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** add z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_s8.c index 0889c189d59699e6fdbc1c91f8a36ab0f9296f52..6775f26cfb24dfaa1c5d60302ae5eb1766102def 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_s8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (add_w0_s8_m_tied1, svint8_t, int8_t, z0 = svadd_m (p0, z0, x0)) /* -** add_w0_s8_m_untied: { xfail *-*-* } +** add_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** add z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_u16.c index 25cb90353d3b852334885c6eb306bb2e97452c2e..f0fafdb1c2dc526f2b9199a451a62975111e53a8 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_u16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (add_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = svadd_m (p0, z0, x0)) /* -** add_w0_u16_m_untied: { xfail *-*-* } +** add_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** add z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_u8.c index 06b68c97ce8c84494c960f28b2ae4c5dcafd0d03..2bdb7a85f56a8c1969e9390b6ba7c0eb10336c97 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/add_u8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (add_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = svadd_m (p0, z0, x0)) /* -** add_w0_u8_m_untied: { xfail *-*-* } +** add_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** add z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_s16.c index d54613e915d221b02d957cf57c44d690328cb430..15e5d58334455a75a42eee29e2aaf1eb89e75acd 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_s16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (and_w0_s16_m_tied1, svint16_t, int16_t, z0 = svand_m (p0, z0, x0)) /* -** and_w0_s16_m_untied: { xfail *-*-* } +** and_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** and z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_s8.c index 61d168d3fdf8968295724cdb0e63fcb087d30d27..197c3011cee8d17725ed0e42557745325b4cfa2d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_s8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (and_w0_s8_m_tied1, svint8_t, int8_t, z0 = svand_m (p0, z0, x0)) /* -** and_w0_s8_m_untied: { xfail *-*-* } +** and_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** and z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_u16.c index 875a08d71d1822c54b3d549ce46e6c951ef38bc6..8210fba2f6382e493fba46f7b087b6de860f7f66 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_u16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (and_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = svand_m (p0, z0, x0)) /* -** and_w0_u16_m_untied: { xfail *-*-* } +** and_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** and z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_u8.c index b0f1c9529f05d614a1b37bdba68caf843ae12f65..5d3fd60382ffe4016f4539f347a1e34045a4e827 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/and_u8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (and_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = svand_m (p0, z0, x0)) /* -** and_w0_u8_m_untied: { xfail *-*-* } +** and_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** and z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asr_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asr_s16.c index 877bf10685a4b29cc0c6e067ce0cec61530df59f..f9ce790da95e655ac73389ccdc36b9e16cdfebb9 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asr_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asr_s16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (asr_w0_s16_m_tied1, svint16_t, uint16_t, z0 = svasr_m (p0, z0, x0)) /* -** asr_w0_s16_m_untied: { xfail *-*-* } +** asr_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** asr z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asr_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asr_s8.c index 992e93fdef7a6a425d247229ebc14801caf02ef0..5cf3a712c282534031e1dbf301f82058467da4ec 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asr_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/asr_s8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (asr_w0_s8_m_tied1, svint8_t, uint8_t, z0 = svasr_m (p0, z0, x0)) /* -** asr_w0_s8_m_untied: { xfail *-*-* } +** asr_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** asr z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_s16.c index c80f5697f5f475cb052527b2a0af5c37b794ba3b..9cf22ebe7fc37a12f9ef3d0a5c76b9c7db82d0ae 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_s16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (bic_w0_s16_m_tied1, svint16_t, int16_t, z0 = svbic_m (p0, z0, x0)) /* -** bic_w0_s16_m_untied: { xfail *-*-* } +** bic_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** bic z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_s8.c index 0958a34039394d79ecd00ac3c855c01cecbce86a..6795716810c8ba79da1c4e96d8eeef1cfdd1dc40 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_s8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (bic_w0_s8_m_tied1, svint8_t, int8_t, z0 = svbic_m (p0, z0, x0)) /* -** bic_w0_s8_m_untied: { xfail *-*-* } +** bic_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** bic z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_u16.c index 30209ffb418f410094afd9df594dad98aa380a5d..5409954caff45d6c12bd13c4e090712f72e8da0e 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_u16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (bic_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = svbic_m (p0, z0, x0)) /* -** bic_w0_u16_m_untied: { xfail *-*-* } +** bic_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** bic z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_u8.c index 80c489b9cdb2b6c6dfd3ab5377bc902f8ef86f6d..a0fbae4796259694b6918a88d9743c4edb9f390d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bic_u8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (bic_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = svbic_m (p0, z0, x0)) /* -** bic_w0_u8_m_untied: { xfail *-*-* } +** bic_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** bic z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_s32.c index 605bd1b30f25f4b2b2bb9e923a9e7dfee8784b07..e9603adf20b79bb96cb1f8ea7e804c308212b319 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_s32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_s32.c @@ -54,7 +54,7 @@ TEST_DUAL_ZX (dot_w0_s32_tied1, svint32_t, svint8_t, int8_t, z0 = svdot (z0, z4, x0)) /* -** dot_w0_s32_untied: { xfail *-*-* } +** dot_w0_s32_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** sdot z0\.s, z4\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_s64.c index b6574740b7e7a9a9ff5f79568d8590d2744ad7a4..7a13c62c535150d827e4247de3151588e61d9e68 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_s64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_s64.c @@ -54,7 +54,7 @@ TEST_DUAL_ZX (dot_w0_s64_tied1, svint64_t, svint16_t, int16_t, z0 = svdot (z0, z4, x0)) /* -** dot_w0_s64_untied: { xfail *-*-* } +** dot_w0_s64_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** sdot z0\.d, z4\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_u32.c index 541e71cc212e7ce0d96a550c373c4c30a0db58ea..e46cac469d98fc59408296676566c61f88fc1c77 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_u32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_u32.c @@ -54,7 +54,7 @@ TEST_DUAL_ZX (dot_w0_u32_tied1, svuint32_t, svuint8_t, uint8_t, z0 = svdot (z0, z4, x0)) /* -** dot_w0_u32_untied: { xfail *-*-* } +** dot_w0_u32_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** udot z0\.s, z4\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_u64.c index cc0e853737df001f4d46c0a12edad45dd568f745..67576c8da171ff61bb32db4f89b2dd3074be48e0 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_u64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/dot_u64.c @@ -54,7 +54,7 @@ TEST_DUAL_ZX (dot_w0_u64_tied1, svuint64_t, svuint16_t, uint16_t, z0 = svdot (z0, z4, x0)) /* -** dot_w0_u64_untied: { xfail *-*-* } +** dot_w0_u64_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** udot z0\.d, z4\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_s16.c index 7cf73609a1aa188e0385838803fe75f45014a1bc..123cdfb0a7a74be73be8bea5b21ec2593a21f96a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_s16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (eor_w0_s16_m_tied1, svint16_t, int16_t, z0 = sveor_m (p0, z0, x0)) /* -** eor_w0_s16_m_untied: { xfail *-*-* } +** eor_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** eor z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_s8.c index 083ac2dde06e43dbdcdcf441c7d50ea77ac5c9cd..5da5908ac36bb729564e2e810a43965bd0913be3 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_s8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (eor_w0_s8_m_tied1, svint8_t, int8_t, z0 = sveor_m (p0, z0, x0)) /* -** eor_w0_s8_m_untied: { xfail *-*-* } +** eor_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** eor z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_u16.c index 40b43a5f89b480a6286c1fcc0746375eb8031914..b3c2e0c4e0b4320653b663f55246e9aa59afa722 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_u16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (eor_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = sveor_m (p0, z0, x0)) /* -** eor_w0_u16_m_untied: { xfail *-*-* } +** eor_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** eor z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_u8.c index 006637699e8b199aad22112b72d748c04f8f5257..021af308174b1d5e0003e7a2960cc821739c4aab 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/eor_u8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (eor_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = sveor_m (p0, z0, x0)) /* -** eor_w0_u8_m_untied: { xfail *-*-* } +** eor_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** eor z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s16.c index edaaca5f155b9af6cd7dd1d15ff94e86c82c486f..67db99697ee88367f8393f9580b4cc11655c2327 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (lsl_w0_s16_m_tied1, svint16_t, uint16_t, z0 = svlsl_m (p0, z0, x0)) /* -** lsl_w0_s16_m_untied: { xfail *-*-* } +** lsl_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** lsl z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s8.c index 9a9cc959c33da729324920a6946c15cb6ba099bd..67a09a745e24e08c29bdbadde1b2f9640683a1d0 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (lsl_w0_s8_m_tied1, svint8_t, uint8_t, z0 = svlsl_m (p0, z0, x0)) /* -** lsl_w0_s8_m_untied: { xfail *-*-* } +** lsl_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** lsl z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u16.c index 57db0fda66af3d642eeacd22ec3bd48c94b34048..b5e7386ce632a672b49b4bc05d8380fbc62bc0bb 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (lsl_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = svlsl_m (p0, z0, x0)) /* -** lsl_w0_u16_m_untied: { xfail *-*-* } +** lsl_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** lsl z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u8.c index 894b5513857b5949a6942156148778a9ae9cadbe..905bf9ed1692ab596af0237a7b33fa40bca24ddd 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (lsl_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = svlsl_m (p0, z0, x0)) /* -** lsl_w0_u8_m_untied: { xfail *-*-* } +** lsl_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** lsl z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsr_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsr_u16.c index 61575645fad086970193875926d051ecc6482ef6..a41411986f798e251e73915542f999f8468fd2eb 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsr_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsr_u16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (lsr_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = svlsr_m (p0, z0, x0)) /* -** lsr_w0_u16_m_untied: { xfail *-*-* } +** lsr_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** lsr z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsr_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsr_u8.c index a049ca90556e5daa42a928a82a1a704803194cd6..b773eedba7fe5b4e390170076a32d9281527d690 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsr_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsr_u8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (lsr_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = svlsr_m (p0, z0, x0)) /* -** lsr_w0_u8_m_untied: { xfail *-*-* } +** lsr_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** lsr z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_s16.c index 02a6d4588b85f315e8e695b196db8bbf5c214454..bb6e0ea31c521dfb8199aff6409b56335d492320 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_s16.c @@ -54,7 +54,7 @@ TEST_UNIFORM_ZX (mad_w0_s16_m_tied1, svint16_t, int16_t, z0 = svmad_m (p0, z0, z1, x0)) /* -** mad_w0_s16_m_untied: { xfail *-*-* } +** mad_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** mad z0\.h, p0/m, z2\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_s8.c index 90d712686ca5ab9752c245dcf2ae4230546fd9fc..adc6972a7dca903a148e83b649140f8b97f10eee 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_s8.c @@ -54,7 +54,7 @@ TEST_UNIFORM_ZX (mad_w0_s8_m_tied1, svint8_t, int8_t, z0 = svmad_m (p0, z0, z1, x0)) /* -** mad_w0_s8_m_untied: { xfail *-*-* } +** mad_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** mad z0\.b, p0/m, z2\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_u16.c index 1d2ad9c5fc9d972c08bbf690b1fb4fb4d26c6f29..5b3c390b14c8b26b268cad5b364ac32a13a502b5 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_u16.c @@ -54,7 +54,7 @@ TEST_UNIFORM_ZX (mad_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = svmad_m (p0, z0, z1, x0)) /* -** mad_w0_u16_m_untied: { xfail *-*-* } +** mad_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** mad z0\.h, p0/m, z2\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_u8.c index 0b4b1b8cfe6e3b00eb4b1fe0516ca84fd2418aa0..a23c813f18f1a82b9dca777a84d44c2d2993c6ce 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mad_u8.c @@ -54,7 +54,7 @@ TEST_UNIFORM_ZX (mad_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = svmad_m (p0, z0, z1, x0)) /* -** mad_w0_u8_m_untied: { xfail *-*-* } +** mad_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** mad z0\.b, p0/m, z2\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_s16.c index 6a21675228274043ec4ed46405964015a9f34744..d5f5e6e629dcadf40618dd7156a39fda36b3896a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_s16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (max_w0_s16_m_tied1, svint16_t, int16_t, z0 = svmax_m (p0, z0, x0)) /* -** max_w0_s16_m_untied: { xfail *-*-* } +** max_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** smax z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_s8.c index c651a26f0d1a92bdaca0ea7260421a6e251e2622..e23dbeeec6b33ef8f28ddde8a52af1e1cbb3e815 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_s8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (max_w0_s8_m_tied1, svint8_t, int8_t, z0 = svmax_m (p0, z0, x0)) /* -** max_w0_s8_m_untied: { xfail *-*-* } +** max_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** smax z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_u16.c index 9a0b9543169d9a626e20009a8a838ba16fd6c48c..9ad6705ab703b204a78b07174590cbaa8813731d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_u16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (max_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = svmax_m (p0, z0, x0)) /* -** max_w0_u16_m_untied: { xfail *-*-* } +** max_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** umax z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_u8.c index 04c9ddb36a23c13e345781c04c3ef566e9c0f2af..6326891f68005c6223afe0c1f24ffa1b81d059e3 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/max_u8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (max_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = svmax_m (p0, z0, x0)) /* -** max_w0_u8_m_untied: { xfail *-*-* } +** max_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** umax z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_s16.c index 14dfcc4c333b69fe24a4a9f978c02999f8abffce..1cf12277add40827921a4a1004d59e6706977acf 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_s16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (min_w0_s16_m_tied1, svint16_t, int16_t, z0 = svmin_m (p0, z0, x0)) /* -** min_w0_s16_m_untied: { xfail *-*-* } +** min_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** smin z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_s8.c index 714b1576d5c6fa27d2648c2db0e38076aeb266c0..4edc0b72fadbbe508d7b9666f6d438163eb8c2cb 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_s8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (min_w0_s8_m_tied1, svint8_t, int8_t, z0 = svmin_m (p0, z0, x0)) /* -** min_w0_s8_m_untied: { xfail *-*-* } +** min_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** smin z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_u16.c index df35cf1135ec0fcf7a6528f78657271b95b8defc..2147f96d09f251703845745f2fbe505793bf51cd 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_u16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (min_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = svmin_m (p0, z0, x0)) /* -** min_w0_u16_m_untied: { xfail *-*-* } +** min_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** umin z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_u8.c index 2ca274278a29a0e16e0756a5015f438bfa90f839..734925e6ea348316ee8cf6a3b9356f38c2f819ea 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/min_u8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (min_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = svmin_m (p0, z0, x0)) /* -** min_w0_u8_m_untied: { xfail *-*-* } +** min_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** umin z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_s16.c index f3ed191db6abe5947313cf9cc9259735f39aa789..c016acd816290082b4dde6b83ca4f7c74f975ae0 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_s16.c @@ -54,7 +54,7 @@ TEST_UNIFORM_ZX (mla_w0_s16_m_tied1, svint16_t, int16_t, z0 = svmla_m (p0, z0, z1, x0)) /* -** mla_w0_s16_m_untied: { xfail *-*-* } +** mla_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** mla z0\.h, p0/m, z2\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_s8.c index 47468947d78b686ee83a309ad7ff2f31deed5872..ccbf145850acf927ebdc02ad950bd518606eb79d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_s8.c @@ -54,7 +54,7 @@ TEST_UNIFORM_ZX (mla_w0_s8_m_tied1, svint8_t, int8_t, z0 = svmla_m (p0, z0, z1, x0)) /* -** mla_w0_s8_m_untied: { xfail *-*-* } +** mla_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** mla z0\.b, p0/m, z2\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_u16.c index 7238e428f68668c23ef46d62a6bfb036bc669641..c3121bb761261c1acf632709ff4836b2fd4e5692 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_u16.c @@ -54,7 +54,7 @@ TEST_UNIFORM_ZX (mla_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = svmla_m (p0, z0, z1, x0)) /* -** mla_w0_u16_m_untied: { xfail *-*-* } +** mla_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** mla z0\.h, p0/m, z2\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_u8.c index 832ed41410e39b1c0e554799d9d881357939ab1c..ecc70274cb6e452b1576d02968b8afe5a7dc7fac 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mla_u8.c @@ -54,7 +54,7 @@ TEST_UNIFORM_ZX (mla_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = svmla_m (p0, z0, z1, x0)) /* -** mla_w0_u8_m_untied: { xfail *-*-* } +** mla_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** mla z0\.b, p0/m, z2\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_s16.c index e199829c4adc8da64824e5523e77a02b1dc0acf4..7be0a4128f6165a65ef2a2f2defb659c50d64b45 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_s16.c @@ -54,7 +54,7 @@ TEST_UNIFORM_ZX (mls_w0_s16_m_tied1, svint16_t, int16_t, z0 = svmls_m (p0, z0, z1, x0)) /* -** mls_w0_s16_m_untied: { xfail *-*-* } +** mls_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** mls z0\.h, p0/m, z2\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_s8.c index c60c431455f099fc45e5ad2a026a72a6f7ae3eb9..fc3a65c7a0944e5c6865a2ddb899a06d15b21976 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_s8.c @@ -54,7 +54,7 @@ TEST_UNIFORM_ZX (mls_w0_s8_m_tied1, svint8_t, int8_t, z0 = svmls_m (p0, z0, z1, x0)) /* -** mls_w0_s8_m_untied: { xfail *-*-* } +** mls_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** mls z0\.b, p0/m, z2\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_u16.c index e8a9f5cd94c6d823f988915373bfa5eebbc44c45..10779fb6674aefef7bcbd209dbc94ec3badb4801 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_u16.c @@ -54,7 +54,7 @@ TEST_UNIFORM_ZX (mls_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = svmls_m (p0, z0, z1, x0)) /* -** mls_w0_u16_m_untied: { xfail *-*-* } +** mls_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** mls z0\.h, p0/m, z2\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_u8.c index 0489aaa7cf96af5d0d02233f813b0b95119b1169..c9277e11cb5cefbe43511da5e01a74aa5f7eac6c 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mls_u8.c @@ -54,7 +54,7 @@ TEST_UNIFORM_ZX (mls_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = svmls_m (p0, z0, z1, x0)) /* -** mls_w0_u8_m_untied: { xfail *-*-* } +** mls_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** mls z0\.b, p0/m, z2\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_s16.c index 56347cfb91828d45f5609c030e0869c650c5fd2f..52f3721c93633568f390cc6b7196af38a715b844 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_s16.c @@ -54,7 +54,7 @@ TEST_UNIFORM_ZX (msb_w0_s16_m_tied1, svint16_t, int16_t, z0 = svmsb_m (p0, z0, z1, x0)) /* -** msb_w0_s16_m_untied: { xfail *-*-* } +** msb_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** msb z0\.h, p0/m, z2\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_s8.c index d7fcafdd0dfab6f4b1f7da8551570ab898ca2eab..381773c4a2b43538a336a63a36f4d3307e0e405f 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_s8.c @@ -54,7 +54,7 @@ TEST_UNIFORM_ZX (msb_w0_s8_m_tied1, svint8_t, int8_t, z0 = svmsb_m (p0, z0, z1, x0)) /* -** msb_w0_s8_m_untied: { xfail *-*-* } +** msb_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** msb z0\.b, p0/m, z2\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_u16.c index 437a96040e12ca2dc83d8dc56ff2dbf14d3728ba..3b710f72c2dcce03df64634b35a5838330eda410 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_u16.c @@ -54,7 +54,7 @@ TEST_UNIFORM_ZX (msb_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = svmsb_m (p0, z0, z1, x0)) /* -** msb_w0_u16_m_untied: { xfail *-*-* } +** msb_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** msb z0\.h, p0/m, z2\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_u8.c index 5665ec9e32075c0d8a9665ab624c4dfde2042d5a..a0e86c799183d758a5be4a5116c592aba9d50021 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/msb_u8.c @@ -54,7 +54,7 @@ TEST_UNIFORM_ZX (msb_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = svmsb_m (p0, z0, z1, x0)) /* -** msb_w0_u8_m_untied: { xfail *-*-* } +** msb_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** msb z0\.b, p0/m, z2\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s16.c index aa08bc2740507c7df20a31acea455b61e937ae4e..52c6767ede0df73ac5b5a7c32c283c13f46d1c85 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (mul_w0_s16_m_tied1, svint16_t, int16_t, z0 = svmul_m (p0, z0, x0)) /* -** mul_w0_s16_m_untied: { xfail *-*-* } +** mul_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** mul z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s8.c index 012e6f250989dd0965b72bbec26d05facf0d6bda..5fc9d93b2b4567f381521c63d9b174cdd4dea1e0 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_s8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (mul_w0_s8_m_tied1, svint8_t, int8_t, z0 = svmul_m (p0, z0, x0)) /* -** mul_w0_s8_m_untied: { xfail *-*-* } +** mul_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** mul z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u16.c index 300987eb6e63677a0fa5e0f2b99f39700f9520bb..b081d230be3ed49044c506da156bc00bbaeb28a6 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (mul_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = svmul_m (p0, z0, x0)) /* -** mul_w0_u16_m_untied: { xfail *-*-* } +** mul_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** mul z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u8.c index b2745a48f506cabee8fe9d952c7d89fa8eabdd45..e02be8b343e4e02d765bfea3a55e5f2f43345867 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mul_u8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (mul_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = svmul_m (p0, z0, x0)) /* -** mul_w0_u8_m_untied: { xfail *-*-* } +** mul_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** mul z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_s16.c index a81532f5d8987dc2405cf0a51ca476052f5b984e..3cd3a2477052ad17c435a9bcb0db92789a2b8611 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_s16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (mulh_w0_s16_m_tied1, svint16_t, int16_t, z0 = svmulh_m (p0, z0, x0)) /* -** mulh_w0_s16_m_untied: { xfail *-*-* } +** mulh_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** smulh z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_s8.c index f9cd01afdc964f89e6fd24a057aa17f69bb3172c..08ead93a80da38a9df5dc770141f84a23e5ac1a6 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_s8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (mulh_w0_s8_m_tied1, svint8_t, int8_t, z0 = svmulh_m (p0, z0, x0)) /* -** mulh_w0_s8_m_untied: { xfail *-*-* } +** mulh_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** smulh z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_u16.c index e9173eb243ec9c2514809fd0bdf208a7811377a8..01a0de738bb980adfcd0394ca221fe765fb8207c 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_u16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (mulh_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = svmulh_m (p0, z0, x0)) /* -** mulh_w0_u16_m_untied: { xfail *-*-* } +** mulh_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** umulh z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_u8.c index db7b1be1bdf92ec534ae8d467cb44d0df380423a..ce547ffbe2b6ced08ad52f366800f68c7bda9dfb 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mulh_u8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (mulh_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = svmulh_m (p0, z0, x0)) /* -** mulh_w0_u8_m_untied: { xfail *-*-* } +** mulh_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** umulh z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_s16.c index 62b707a9c696164ec1da32daac76182f3dbcf1fa..c0a3aaf3dfe6b7bf29dfdf91a16b16e64d4b966a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_s16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (orr_w0_s16_m_tied1, svint16_t, int16_t, z0 = svorr_m (p0, z0, x0)) /* -** orr_w0_s16_m_untied: { xfail *-*-* } +** orr_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** orr z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_s8.c index b6483b6e76ec82e0e6e99e701271fb2fe3d507b5..96c265d856ab5aba848a04c44c1ebc2db790e21d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_s8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (orr_w0_s8_m_tied1, svint8_t, int8_t, z0 = svorr_m (p0, z0, x0)) /* -** orr_w0_s8_m_untied: { xfail *-*-* } +** orr_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** orr z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_u16.c index 000a0444c9b08f8c17bc44183381f57c5136081a..8757ff18499b28fd4e3156abfa9e331058b895a8 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_u16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (orr_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = svorr_m (p0, z0, x0)) /* -** orr_w0_u16_m_untied: { xfail *-*-* } +** orr_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** orr z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_u8.c index efe5591b47287412ec558ece8a9449302b9df31d..c9701f2c3492520f15c369ca74b60a2c370b78f2 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/orr_u8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (orr_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = svorr_m (p0, z0, x0)) /* -** orr_w0_u8_m_untied: { xfail *-*-* } +** orr_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** orr z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/scale_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/scale_f16.c index 9c554255b443844d04427ce5777264921a3c5f61..50a718d46cf772ec12697d14bee61a3dfb59f6ec 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/scale_f16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/scale_f16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (scale_w0_f16_m_tied1, svfloat16_t, int16_t, z0 = svscale_m (p0, z0, x0)) /* -** scale_w0_f16_m_untied: { xfail *-*-* } +** scale_w0_f16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** fscale z0\.h, p0/m, z0\.h, \1 @@ -211,7 +211,7 @@ TEST_UNIFORM_ZX (scale_w0_f16_x_tied1, svfloat16_t, int16_t, z0 = svscale_x (p0, z0, x0)) /* -** scale_w0_f16_x_untied: { xfail *-*-* } +** scale_w0_f16_x_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** fscale z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_s16.c index aea8ea2b4aa545b5e1dc0416f972a2dfec512ba4..fcab3a87162d5df76371166951efb18fde493e55 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_s16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (sub_w0_s16_m_tied1, svint16_t, int16_t, z0 = svsub_m (p0, z0, x0)) /* -** sub_w0_s16_m_untied: { xfail *-*-* } +** sub_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** sub z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_s8.c index 0d7ba99aa5695c97e74ffc729dc01a96d2fbeec5..4de12f0b387d9d595c5bc4043018aaabdd643425 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_s8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (sub_w0_s8_m_tied1, svint8_t, int8_t, z0 = svsub_m (p0, z0, x0)) /* -** sub_w0_s8_m_untied: { xfail *-*-* } +** sub_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** sub z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_u16.c index 89620e159bf3b55a88c00900c901cafb547510b1..d682efa93eac4c97984e75d302268c2b478e07b9 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_u16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (sub_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = svsub_m (p0, z0, x0)) /* -** sub_w0_u16_m_untied: { xfail *-*-* } +** sub_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** sub z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_u8.c index 4552041910f7e86cbe896c04971da1b974a5eda0..39bc519c642585eba13fda8edd8060dff5627371 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sub_u8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (sub_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = svsub_m (p0, z0, x0)) /* -** sub_w0_u8_m_untied: { xfail *-*-* } +** sub_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** sub z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_s16.c index d3dad62dafeb93db1f2a309e4f4caab967a6dedd..ad6f4519e536adab2c45ad015b922d4c96714ab7 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_s16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (subr_w0_s16_m_tied1, svint16_t, int16_t, z0 = svsubr_m (p0, z0, x0)) /* -** subr_w0_s16_m_untied: { xfail *-*-* } +** subr_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** subr z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_s8.c index 90d2a6de9a5fc935fd134c459b89829a933f116d..c31948202e2405990d0c6c99bd11fcb564983cc9 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_s8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (subr_w0_s8_m_tied1, svint8_t, int8_t, z0 = svsubr_m (p0, z0, x0)) /* -** subr_w0_s8_m_untied: { xfail *-*-* } +** subr_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** subr z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_u16.c index 379a80fb189796f747c92948d33ff3bf8cf6d0a7..631593aad78af792659842fd635b3335ea439366 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_u16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (subr_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = svsubr_m (p0, z0, x0)) /* -** subr_w0_u16_m_untied: { xfail *-*-* } +** subr_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** subr z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_u8.c index fe5f96da833565d6013383281e14005f380410ba..b9ab757ca81b75d1d76fc969982e078db76b8a28 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/subr_u8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (subr_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = svsubr_m (p0, z0, x0)) /* -** subr_w0_u8_m_untied: { xfail *-*-* } +** subr_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** subr z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bcax_s16.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bcax_s16.c index acad87d963540c6cbf3df1a929ac368c754007a7..2fb2bdff574222033b090498b93b99efae68073e 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bcax_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bcax_s16.c @@ -66,7 +66,7 @@ TEST_UNIFORM_ZX (bcax_w0_s16_tied2, svint16_t, int16_t, z0 = svbcax (z1, z0, x0)) /* -** bcax_w0_s16_untied: { xfail *-*-*} +** bcax_w0_s16_untied: ** mov (z[0-9]+)\.h, w0 ** movprfx z0, z1 ** bcax z0\.d, z0\.d, (z2\.d, \1\.d|\1\.d, z2\.d) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bcax_s8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bcax_s8.c index 548aafad85739d8420bd2c14bb877f14d8e755bc..3925f56ff20ca9db559a338587e1f19db8e9a0a6 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bcax_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bcax_s8.c @@ -66,7 +66,7 @@ TEST_UNIFORM_ZX (bcax_w0_s8_tied2, svint8_t, int8_t, z0 = svbcax (z1, z0, x0)) /* -** bcax_w0_s8_untied: { xfail *-*-*} +** bcax_w0_s8_untied: ** mov (z[0-9]+)\.b, w0 ** movprfx z0, z1 ** bcax z0\.d, z0\.d, (z2\.d, \1\.d|\1\.d, z2\.d) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bcax_u16.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bcax_u16.c index b63a4774ba73e5df19fcc5190483a3fda4092598..589e868b205c492b510aafd21d77bb187d35429d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bcax_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bcax_u16.c @@ -66,7 +66,7 @@ TEST_UNIFORM_ZX (bcax_w0_u16_tied2, svuint16_t, uint16_t, z0 = svbcax (z1, z0, x0)) /* -** bcax_w0_u16_untied: { xfail *-*-*} +** bcax_w0_u16_untied: ** mov (z[0-9]+)\.h, w0 ** movprfx z0, z1 ** bcax z0\.d, z0\.d, (z2\.d, \1\.d|\1\.d, z2\.d) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bcax_u8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bcax_u8.c index 0957d58bd0ecd348ea4148ce84e05ffcb2848bcd..ee0b603830b702fd7e99723d129e5369ded0ab9a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bcax_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/bcax_u8.c @@ -66,7 +66,7 @@ TEST_UNIFORM_ZX (bcax_w0_u8_tied2, svuint8_t, uint8_t, z0 = svbcax (z1, z0, x0)) /* -** bcax_w0_u8_untied: { xfail *-*-*} +** bcax_w0_u8_untied: ** mov (z[0-9]+)\.b, w0 ** movprfx z0, z1 ** bcax z0\.d, z0\.d, (z2\.d, \1\.d|\1\.d, z2\.d) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qadd_s16.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qadd_s16.c index 6330c4265bb17b80f12a884e663db342b9c346b2..286f2e2b969139106f8a38b41b42097c9a79c276 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qadd_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qadd_s16.c @@ -163,7 +163,7 @@ TEST_UNIFORM_ZX (qadd_w0_s16_m_tied1, svint16_t, int16_t, z0 = svqadd_m (p0, z0, x0)) /* -** qadd_w0_s16_m_untied: { xfail *-*-* } +** qadd_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** sqadd z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qadd_s8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qadd_s8.c index 61343beacb899b843c2358b609cc26a1ca1110a3..ad439892a6749aa3d346424f8b2aebcd4bd4762c 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qadd_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qadd_s8.c @@ -163,7 +163,7 @@ TEST_UNIFORM_ZX (qadd_w0_s8_m_tied1, svint8_t, int8_t, z0 = svqadd_m (p0, z0, x0)) /* -** qadd_w0_s8_m_untied: { xfail *-*-* } +** qadd_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** sqadd z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qadd_u16.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qadd_u16.c index f6c7ca9e075b7106209b858763a0cec160210ddf..9dafc3617ef84cf5a6ac13ad532a0e63065c7409 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qadd_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qadd_u16.c @@ -166,7 +166,7 @@ TEST_UNIFORM_ZX (qadd_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = svqadd_m (p0, z0, x0)) /* -** qadd_w0_u16_m_untied: { xfail *-*-* } +** qadd_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** uqadd z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qadd_u8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qadd_u8.c index 6c856e2871c26e1fbfa32c4e37df60c8884e76dd..a485cf3eeb656dded02c7eba8944757d164fbf6c 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qadd_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qadd_u8.c @@ -163,7 +163,7 @@ TEST_UNIFORM_ZX (qadd_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = svqadd_m (p0, z0, x0)) /* -** qadd_w0_u8_m_untied: { xfail *-*-* } +** qadd_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** uqadd z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qdmlalb_s16.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qdmlalb_s16.c index 4d1e90395e212b323f304f837504f2d8b158afc8..4880a6940d2981dd37b049431a68c326264c9503 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qdmlalb_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qdmlalb_s16.c @@ -54,7 +54,7 @@ TEST_DUAL_ZX (qdmlalb_w0_s16_tied1, svint16_t, svint8_t, int8_t, z0 = svqdmlalb (z0, z4, x0)) /* -** qdmlalb_w0_s16_untied: { xfail *-*-* } +** qdmlalb_w0_s16_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** sqdmlalb z0\.h, z4\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qdmlalb_s32.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qdmlalb_s32.c index 94373773e61e3ad6ce0ff5c2a7fda38f8e2086cb..03eebba5997c583768253586c252ec13c939b890 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qdmlalb_s32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qdmlalb_s32.c @@ -54,7 +54,7 @@ TEST_DUAL_ZX (qdmlalb_w0_s32_tied1, svint32_t, svint16_t, int16_t, z0 = svqdmlalb (z0, z4, x0)) /* -** qdmlalb_w0_s32_untied: { xfail *-*-* } +** qdmlalb_w0_s32_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** sqdmlalb z0\.s, z4\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qdmlalbt_s16.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qdmlalbt_s16.c index d591db3cfb8da203395b3b5e2955805381a3e4f3..0b3d5279db96bd7a39f286c6c5b37d9e1dea7d5a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qdmlalbt_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qdmlalbt_s16.c @@ -54,7 +54,7 @@ TEST_DUAL_ZX (qdmlalbt_w0_s16_tied1, svint16_t, svint8_t, int8_t, z0 = svqdmlalbt (z0, z4, x0)) /* -** qdmlalbt_w0_s16_untied: { xfail *-*-*} +** qdmlalbt_w0_s16_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** sqdmlalbt z0\.h, z4\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qdmlalbt_s32.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qdmlalbt_s32.c index e8326fed6171531cad3dd1c8c921d89bc1f29ce9..9f2dd464e638d8dbe7d15b1fa1c1538aef18169a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qdmlalbt_s32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qdmlalbt_s32.c @@ -54,7 +54,7 @@ TEST_DUAL_ZX (qdmlalbt_w0_s32_tied1, svint32_t, svint16_t, int16_t, z0 = svqdmlalbt (z0, z4, x0)) /* -** qdmlalbt_w0_s32_untied: { xfail *-*-*} +** qdmlalbt_w0_s32_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** sqdmlalbt z0\.s, z4\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsub_s16.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsub_s16.c index c102e58ed910c07aef6bee739f45fb96dd5aed80..618a61bf48fd912014b59874372e8d22eb7ee325 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsub_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsub_s16.c @@ -163,7 +163,7 @@ TEST_UNIFORM_ZX (qsub_w0_s16_m_tied1, svint16_t, int16_t, z0 = svqsub_m (p0, z0, x0)) /* -** qsub_w0_s16_m_untied: { xfail *-*-* } +** qsub_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** sqsub z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsub_s8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsub_s8.c index 067ee6e6cb1026fc7691268c47d318f4e67aa66c..f0d6b97bf97cb511e3e3a8c1d01948bbe28e393d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsub_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsub_s8.c @@ -163,7 +163,7 @@ TEST_UNIFORM_ZX (qsub_w0_s8_m_tied1, svint8_t, int8_t, z0 = svqsub_m (p0, z0, x0)) /* -** qsub_w0_s8_m_untied: { xfail *-*-* } +** qsub_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** sqsub z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsub_u16.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsub_u16.c index 61be74634723fe1cac7a5c2e38b5d5e72d73dd84..3e87dd162bfe0494d060098c0640094591ef6072 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsub_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsub_u16.c @@ -166,7 +166,7 @@ TEST_UNIFORM_ZX (qsub_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = svqsub_m (p0, z0, x0)) /* -** qsub_w0_u16_m_untied: { xfail *-*-* } +** qsub_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** uqsub z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsub_u8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsub_u8.c index 686b2b425fb5f0ff9439571f7c518aa4b2e43167..92bf92909a7874a8bb4e073250b9f71e1bc82ebe 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsub_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsub_u8.c @@ -163,7 +163,7 @@ TEST_UNIFORM_ZX (qsub_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = svqsub_m (p0, z0, x0)) /* -** qsub_w0_u8_m_untied: { xfail *-*-* } +** qsub_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** uqsub z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsubr_s16.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsubr_s16.c index 577310d9614be6f063e473eb2d1b6be7aebf4cc2..e42821849b266391555d39773efa6f072bfa810c 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsubr_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsubr_s16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (qsubr_w0_s16_m_tied1, svint16_t, int16_t, z0 = svqsubr_m (p0, z0, x0)) /* -** qsubr_w0_s16_m_untied: { xfail *-*-* } +** qsubr_w0_s16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** sqsubr z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsubr_s8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsubr_s8.c index ce814a8393e94f50ecff8869649bf0acbb8eeb7e..92e66f70cbfdb066be1e2b5a745f57dff0b85c43 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsubr_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsubr_s8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (qsubr_w0_s8_m_tied1, svint8_t, int8_t, z0 = svqsubr_m (p0, z0, x0)) /* -** qsubr_w0_s8_m_untied: { xfail *-*-* } +** qsubr_w0_s8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** sqsubr z0\.b, p0/m, z0\.b, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsubr_u16.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsubr_u16.c index f406bf2ed86c606bd984671b30c925b1c1233fd4..8018fdaef9e3d2a99a916aeae114ad273ea8ee92 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsubr_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsubr_u16.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (qsubr_w0_u16_m_tied1, svuint16_t, uint16_t, z0 = svqsubr_m (p0, z0, x0)) /* -** qsubr_w0_u16_m_untied: { xfail *-*-* } +** qsubr_w0_u16_m_untied: ** mov (z[0-9]+\.h), w0 ** movprfx z0, z1 ** uqsubr z0\.h, p0/m, z0\.h, \1 diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsubr_u8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsubr_u8.c index 7b487fd93b19d4ad620541069759fd0b05564b1c..bb29faa83504c4d1d0df942dfba2ed936c3986a1 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsubr_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qsubr_u8.c @@ -43,7 +43,7 @@ TEST_UNIFORM_ZX (qsubr_w0_u8_m_tied1, svuint8_t, uint8_t, z0 = svqsubr_m (p0, z0, x0)) /* -** qsubr_w0_u8_m_untied: { xfail *-*-* } +** qsubr_w0_u8_m_untied: ** mov (z[0-9]+\.b), w0 ** movprfx z0, z1 ** uqsubr z0\.b, p0/m, z0\.b, \1