From patchwork Mon May 9 06:43:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: liuhongt X-Patchwork-Id: 1628347 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=KyS5JMDw; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4KxWpp6hPqz9sGV for ; Mon, 9 May 2022 16:43:45 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D6FBF3857368 for ; Mon, 9 May 2022 06:43:42 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D6FBF3857368 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1652078622; bh=58EEzJ/dijBrVYxwdA30ezZa6xIUzVET8fuhN+dAb4o=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=KyS5JMDwWw+ZiA3clDLEJk+rLMRaC3b8dqAKkd4eQu7GEtjAcf9OGl+ZEUZiJGOH+ aNJNUmPjZphq9KsOSUoCQIvhXIPhyAyC3K6VVssXtBqT6aQ5VMNlfzcOzokawFrTWu +N6z+DHm8p2cWn3JAy9JIKhnxkSt11H0+/zDNS9A= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by sourceware.org (Postfix) with ESMTPS id 30EF83858C54 for ; Mon, 9 May 2022 06:43:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 30EF83858C54 X-IronPort-AV: E=McAfee;i="6400,9594,10341"; a="269095829" X-IronPort-AV: E=Sophos;i="5.91,210,1647327600"; d="scan'208";a="269095829" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2022 23:43:20 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,210,1647327600"; d="scan'208";a="696234251" Received: from scymds01.sc.intel.com ([10.148.94.138]) by orsmga004.jf.intel.com with ESMTP; 08 May 2022 23:43:20 -0700 Received: from shliclel051.sh.intel.com (shliclel051.sh.intel.com [10.239.236.51]) by scymds01.sc.intel.com with ESMTP id 2496hJSL024451; Sun, 8 May 2022 23:43:19 -0700 To: gcc-patches@gcc.gnu.org Subject: [PATCH] Optimize vec_setv8{hi,hf}_0 + pmovzxbq to pmovzxbq. Date: Mon, 9 May 2022 14:43:18 +0800 Message-Id: <20220509064318.80922-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.18.1 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: liuhongt via Gcc-patches From: liuhongt Reply-To: liuhongt Cc: =ubizjak@gmail.com Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Clean up of 16-bit uppers is not needed for pmovzxbq/pmovsxbq. Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. Ok for trunk? gcc/ChangeLog: PR target/105072 * config/i386/sse.md (*sse4_1_v2qiv2di2_1): New define_insn. (*sse4_1_zero_extendv2qiv2di2_2): New pre_reload define_insn_and_split. gcc/testsuite/ChangeLog: * gcc.target/i386/pr105072.c: New test. --- gcc/config/i386/sse.md | 45 +++++++++++++++++++++--- gcc/testsuite/gcc.target/i386/pr105072.c | 24 +++++++++++++ 2 files changed, 65 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr105072.c diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 7b791def542..47f8b18b82e 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -22297,15 +22297,52 @@ (define_insn "sse4_1_v2qiv2di2" (set_attr "prefix" "orig,orig,maybe_evex") (set_attr "mode" "TI")]) +(define_insn "*sse4_1_v2qiv2di2_1" + [(set (match_operand:V2DI 0 "register_operand" "=v") + (any_extend:V2DI + (match_operand:V2QI 1 "memory_operand" "m")))] + "TARGET_SSE4_1 && " + "%vpmovbq\t{%1, %0|%0, %1}" + [(set_attr "type" "ssemov") + (set_attr "prefix_extra" "1") + (set_attr "prefix" "maybe_evex") + (set_attr "mode" "TI")]) + (define_expand "v2qiv2di2" [(set (match_operand:V2DI 0 "register_operand") (any_extend:V2DI - (match_operand:V2QI 1 "register_operand")))] + (match_operand:V2QI 1 "nonimmediate_operand")))] "TARGET_SSE4_1" { - rtx op1 = force_reg (V2QImode, operands[1]); - op1 = lowpart_subreg (V16QImode, op1, V2QImode); - emit_insn (gen_sse4_1_v2qiv2di2 (operands[0], op1)); + if (!MEM_P (operands[1])) + { + rtx op1 = force_reg (V2QImode, operands[1]); + op1 = lowpart_subreg (V16QImode, op1, V2QImode); + emit_insn (gen_sse4_1_v2qiv2di2 (operands[0], op1)); + DONE; + } +}) + +(define_insn_and_split "*sse4_1_zero_extendv2qiv2di2_2" + [(set (match_operand:V2DI 0 "register_operand") + (zero_extend:V2DI + (vec_select:V2QI + (subreg:V16QI + (vec_merge:V8_128 + (vec_duplicate:V8_128 + (match_operand: 1 "nonimmediate_operand")) + (match_operand:V8_128 2 "const0_operand") + (const_int 1)) 0) + (parallel [(const_int 0) (const_int 1)]))))] + "TARGET_SSE4_1 && ix86_pre_reload_split ()" + "#" + "&& 1" + [(const_int 0)] +{ + if (!MEM_P (operands[1])) + operands[1] = force_reg (mode, operands[1]); + operands[1] = lowpart_subreg (V2QImode, operands[1], mode); + emit_insn (gen_zero_extendv2qiv2di2 (operands[0], operands[1])); DONE; }) diff --git a/gcc/testsuite/gcc.target/i386/pr105072.c b/gcc/testsuite/gcc.target/i386/pr105072.c new file mode 100644 index 00000000000..54e229731b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr105072.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-msse4.1 -O2" } */ +/* { dg-final { scan-assembler-times {(?n)pmovzxbq[ \t]+} "4" } } */ +/* { dg-final { scan-assembler-not {(?n)pinsrw[ \t]+} } } */ + +#include + +__m128i foo (void *p){ + return _mm_cvtepu8_epi64(_mm_loadu_si16(p)); +} + +__m128i foo2 (short a){ + return _mm_cvtepu8_epi64(_mm_set_epi16(0, 0, 0, 0, 0, 0, 0, a)); +} + +__m128i +foo3 (void *p){ + return _mm_cvtepu8_epi64((__m128i)__extension__(__m128h) {*(_Float16 const*)p, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f}); +} + +__m128i +foo4 (_Float16 a){ + return _mm_cvtepu8_epi64((__m128i)__extension__(__m128h) {a, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f}); +}