From patchwork Sun May 8 19:43:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 1628155 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.a=rsa-sha256 header.s=badeba3b8450 header.b=KPG+FxkK; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4KxFBQ1yjXz9sGf for ; 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Mon, 9 May 2022 05:44:24 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1652039024; bh=mGjWYLEwtu+ry5GXvt2ravbif89/+OFp+v9Ndwokqdo=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=KPG+FxkKQDZ5nsfn9b/rDbyRj/EIqKAafJrmd0UKHk3sF7F0EpIr9E0HuW+sj9MmE F6jSp87+YhIrpWvSy/70KQZZgiUasjqmT3gk+bqpdehgm0Tu1LSAxs+xcWauIFHWJO LN0zyxBJ2Q90EaNevt4+QnKnN3sWHZxrhChH4Y5M= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([37.201.215.103]) by mail.gmx.net (mrgmx104 [212.227.17.168]) with ESMTPSA (Nemesis) id 1M59C8-1noskF3cxw-001D9L; Sun, 08 May 2022 21:43:43 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Subject: [PATCH v3 1/7] dt-bindings: timer: nuvoton, npcm7xx-timer: Allow specifying all clocks Date: Sun, 8 May 2022 21:43:26 +0200 Message-Id: <20220508194333.2170161-2-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220508194333.2170161-1-j.neuschaefer@gmx.net> References: <20220508194333.2170161-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:+B8D9NNv1GquKXyh+yewe8u/YXwDSp0omRF9EcPdcedfR2AXylE J1AAfDCtk1qY+HAxFunLVRrV18OJHIvc7EDyOOtcTwouPCChp/DNsHnUQHZDqgWERyuPagV X3P1BvR4gdkav6U/K/2NPsrhWLngw/NR5mURmKEnd+ZzDRYHM7q7F0VB6IL7wxqCkulSdi9 N3W8ciYjZX4nRwIkhXYvg== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1;V03:K0:3V62gOaobJc=:u7MPmttD/cbQagij6o+M6e A1ZgpIfOP04t2VpF2yls4Fr1yKyPFRpoJAVOsfVK3lip+W4IH6N1atgx+OYVetTttNeE6sJe8 UFvKAKZ7rIDLPMnxXkzCQ1HTarfQ8W+Zdsks+9dSjg25zN1RbNF+wUUfeS1qBa4yj21neK38i +FsmfZSiHWlv9dIa14fF+lceiHFEElLdVfZK1uj+YZbqPveniamE8ccpQIK0/U1xuFaFgCKsU 6CsIy0FsbEE9DdBDpwL0FDsfkAUHJ8CLvvIVEtmHIAf8Xo3YId+07sCAZLFKCPH12bvRQPqSx AtdPOYd+4htYu86XBjRSkKiHSkG9w2hG/XtTEGea32xKLScSm7Mue2rPzc1PhK8FyelEb3Fhk kfB65E7zXM3FTwmUcSkZKQsMSHpsobQpHu7t3+mYvYFt0E3iVe3ld0dsWUGL7l8/0veOTPTdk Hfl89lyE9m/kuTbw2DycNFTu08GAlP3+8hfpCdI8Qbp0GvmYlYqyGDOlAJ3sZCqZor6+x1OkE fks595DFnq3ROcqdSVcSqvtx5Gp5WLVrAwAp+pC0MyzboFr/0erS1Wosk6O6QCSrc+xrGw4Du s9ZnU7q9PXs6aiR06M8ckI4AZuIUlxggw8Aa1lGiOh69MokAfR3mnxSZ83zwopw0Np1eYRneb 5mkm5b3cok+GZ8QLShpqXTBICOXyzxW9/d1gXsL7PY7QfCvjA6y8IvFt/8n60BT+Jxj6YMfsl EvTPmKJSW3pcYtthQu5mPTaR9BL3KvcHzROGLEFbAszRf6BhamQJx8zWC7oGL9NAzEowy/ZIE 39fepLWo06hJoD64GqoCZmf6uQ6gK/wV8Y8EcIGhBe5yRniHbRo43EzVlwppfdWCjwYASYEca QQRS3fC1+C71MdUIpJdvuRq9k85w7VejOD/Oj5bLgM1/5EihGiA0CsjHWs/m5Sjw3633cTci2 tdmO2yicl189R7qgV92XYLkvyVi2TL/C+WASWvEkZ8F4VwBKk289fpCssVSTDQRCud5PwkTpU AGVvu1qOjbkaFI/DRQsk+P2ODF8N6DLo9cKituwDI3IwO8qU7ifhLkfAnKzWfMAIcD64b30/8 6v6fStfcg2PBro= X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Herring , devicetree@vger.kernel.org, Wim Van Sebroeck , linux-watchdog@vger.kernel.org, Stephen Boyd , Patrick Venture , Michael Turquette , Daniel Lezcano , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Avi Fishman , Rob Herring , Benjamin Fair , Philipp Zabel , Krzysztof Kozlowski , Tali Perry , Thomas Gleixner , Guenter Roeck , Tomer Maimon Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" The timer module contains multiple timers. In the WPCM450 SoC, each timer runs off a clock can be gated individually. To model this correctly, the timer node in the devicetree needs to take multiple clock inputs. Signed-off-by: Jonathan Neuschäfer Reviewed-by: Rob Herring --- v3: - Add R-b tag v2: - no changes --- .../devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) -- 2.35.1 diff --git a/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml b/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml index 0cbc26a721514..023c999113c38 100644 --- a/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml +++ b/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml @@ -23,7 +23,13 @@ properties: - description: The timer interrupt of timer 0 clocks: - maxItems: 1 + items: + - description: The reference clock for timer 0 + - description: The reference clock for timer 1 + - description: The reference clock for timer 2 + - description: The reference clock for timer 3 + - description: The reference clock for timer 4 + minItems: 1 required: - compatible From patchwork Sun May 8 19:43:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 1628160 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.a=rsa-sha256 header.s=badeba3b8450 header.b=JsMF/b6z; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2404:9400:2:0:216:3eff:fee1:b9f1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4KxFFr11N4z9sGf for ; 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Mon, 9 May 2022 05:44:24 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1652039025; bh=n76/hLRRaMIrLkiSBCnvLg8F9/bppo8blXTP7lMhyu8=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=JsMF/b6z2Skbt7dmEjaQFgi6n9aqnm+yZEXi1SShVosusMlDmprqtCk7KYMW+xJGh Kzzk9IFiSm7haSLwph0ncQnntmtHe5hKRPQh+fH6h58KpHinu+tm6JFvzfa+G0M5us Vf7GANO/ublwGjiAzpZccFqkGZMm1bd0N7eyaHJI= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([37.201.215.103]) by mail.gmx.net (mrgmx105 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MWzfl-1nH8hM1DHl-00XIKc; Sun, 08 May 2022 21:43:45 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Subject: [PATCH v3 2/7] clocksource: timer-npcm7xx: Enable timer 1 clock before use Date: Sun, 8 May 2022 21:43:27 +0200 Message-Id: <20220508194333.2170161-3-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220508194333.2170161-1-j.neuschaefer@gmx.net> References: <20220508194333.2170161-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:pWq1JPNigWSSaZHAqUAune7+HNV0oDFRi3ixapHifQJW0Vw3bl/ ZoyJWWix1P1YxeKAny6kOHF4FsWecJhiDo5Op2QjeFM+JDOeeYyzhycm3Hw/owLu+uB7wj/ VLvVbzMZeQ9vIrhVFIlFCv/3JfTOULSFwDy3qoDCRrYVsVipPTVfSv+YfbSTYkNyvE0TRd3 UzseGXZwNwnHRnzeqk74Q== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1;V03:K0:9SqJwJa9skw=:TtwrXU+6EBNvKZjWzfmS89 Op3XOyAcftg/gHGbODC7HSllJCQpDC4Q6PGOTYQsPRxJXHQakAPqqg1f0SD1KV+oePCXNTgYf L2CsSSYunb75A1sOVWh287HuaW8PsMNscNn5caV/yZ2Yvs8c9zUth8DWjfk+3v4guVXxkw9Ht H37inUOmOpm5ryEzdTiaFbSk2EtggvmfDAXi2m2kzxYjW54dXAF2dd0ly+MYezDoST4aVEMjj 0Rg4/8lp4FlmvVL1GtmGW9dIcAAAxO1Zn4hXmKKwsmkq9+R8FOAUlyPVu0wLJ/XHENWR4q4t0 bmzvxRE78a47zxKMe7qZMUGl8mS+wmPExe4HqCfL9Bq4Y/i1JdaQB1n58fahr0p90AdIyUsAh 6AUc8ZlTc9c82fexYbiigJpo+IB+m5pnGPK2pUP+Z8xNC7Yixminpqm3ZKTHDL9B6Z04yRuxF eqoPCuxO17cKZ8k2D5g7gXiqz9DrlfhQEeWzjRRwEJZXbHcu994oU8zlaffRRYCDZUwZPgMHp PIi8g6IfWxMHqHjhSAbn4dYEEasd4DlIkfqCsWEKbYj/Ts65v2q3xAAHeo41XiBPflBCWO1+d f8sfLZqyTi8K0WhsiDmRlIcWGyi1U4BqL+UuwlIpZMGiEQ6bT2a99QU8smbictQWGntTrWYDM vyhk4/T02WVt69YxD7GtcaDqzAbEsQFdz+Lvi/Lufkkn+qLfa44pysndmuGhGcQ9CEHuUqtkq 34ybixg9Mb7U9OiKBrODAltqZ2nJhxr1ZzMWgUBJgNfsj9WsfIuD2VhSO2/nFdSQe+MnvWTh8 YD8cFADF+QJnsS+rPo7h4bBFdmPQh3X8uC5j43xasIZawB/Sx5bXpLiucqjgZVs4ij8JSpR7M YaNfTJi9hKV2/CeFnRj43RUsRZ7DvNV/KR7PxTE1lHSJ22nS8fLyp2HdMUv34wBo7Wyo9ri3B mT2Mag489GvzYFH4uOrKxK/y9W5KAVd6pSBKia123ORKtbX0b1rzdEMrRST9gIFr2c2xdqo3+ hYPbmoy/Ptem282D/WFggiKkkgtaLs3B+4Lil3tRlwsDyvd0K4qofFScheSdTXvj9+OsXnVsG 4NGl0QfWIdGqXA= X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Wim Van Sebroeck , linux-watchdog@vger.kernel.org, Stephen Boyd , Patrick Venture , Michael Turquette , Daniel Lezcano , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Avi Fishman , Rob Herring , Benjamin Fair , Philipp Zabel , Krzysztof Kozlowski , Tali Perry , Thomas Gleixner , Guenter Roeck , Tomer Maimon Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" In the WPCM450 SoC, the clocks for each timer can be gated individually. To prevent the timer 1 clock from being gated, enable it explicitly. Signed-off-by: Jonathan Neuschäfer --- v3: - no changes v2: - Provide context in pr_warn message v1: - https://lore.kernel.org/lkml/20220422183012.444674-3-j.neuschaefer@gmx.net/ --- drivers/clocksource/timer-npcm7xx.c | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.35.1 diff --git a/drivers/clocksource/timer-npcm7xx.c b/drivers/clocksource/timer-npcm7xx.c index a00520cbb660a..9af30af5f989a 100644 --- a/drivers/clocksource/timer-npcm7xx.c +++ b/drivers/clocksource/timer-npcm7xx.c @@ -188,6 +188,7 @@ static void __init npcm7xx_clocksource_init(void) static int __init npcm7xx_timer_init(struct device_node *np) { + struct clk *clk; int ret; ret = timer_of_init(np, &npcm7xx_to); @@ -199,6 +200,15 @@ static int __init npcm7xx_timer_init(struct device_node *np) npcm7xx_to.of_clk.rate = npcm7xx_to.of_clk.rate / (NPCM7XX_Tx_MIN_PRESCALE + 1); + /* Enable the clock for timer1, if it exists */ + clk = of_clk_get(np, 1); + if (clk) { + if (!IS_ERR(clk)) + clk_prepare_enable(clk); + else + pr_warn("%pOF: Failed to get clock for timer1: %pe", np, clk); + } + npcm7xx_clocksource_init(); npcm7xx_clockevents_init(); From patchwork Sun May 8 19:43:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 1628157 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.a=rsa-sha256 header.s=badeba3b8450 header.b=Tbtd0oOd; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2404:9400:2:0:216:3eff:fee1:b9f1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4KxFCm0Ccxz9sGf for ; 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Mon, 9 May 2022 05:44:24 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1652039027; bh=XVfOBublJT697s4b334rAe6W/GabYUlUTBRHBuTBhbk=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=Tbtd0oOdkMsDXF1n3Ux0ph2RxJiqyYb0tDY6P++BmhN/e+iznGvekhTOLxOzVjlT4 igmUWjro1WUZHg1O3GobuQXl0BpDFZpHh+RzHq+mWs93r8mllPLNSgLuc78oVS0MTA GoHI1D2jI1TjKTaS1G6BElFwn6Rtoo0LjwXgEf2s= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([37.201.215.103]) by mail.gmx.net (mrgmx105 [212.227.17.168]) with ESMTPSA (Nemesis) id 1N8ofO-1nu3cK3CBq-015oXV; Sun, 08 May 2022 21:43:46 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Subject: [PATCH v3 3/7] watchdog: npcm: Enable clock if provided Date: Sun, 8 May 2022 21:43:28 +0200 Message-Id: <20220508194333.2170161-4-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220508194333.2170161-1-j.neuschaefer@gmx.net> References: <20220508194333.2170161-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:vzkFSMPPiFMDmjP7Vq0zkUC7L1qOOrUXx77prPxKxM5JG7X5Bw1 6failCDgS4gKXyhQaublZGP7D3tqW6fJyFX+9hLCjc4rpt4Yr9g0gzqZfWifABWCas2Wndz sjZOvqDUULn6wEzEb12IPa41+sDFls2w5G8n4cfH2kYLUF2O5u7/oj7N3wEijQ9tGuI0Bgj 2hgBVc30Qr2xnLxdevVRA== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1;V03:K0:zl9at1OVUvw=:DHCHsKZqeDHrG2eeIxE8MF 4qykzY0abfuq0Nkh5diTE0IlRkrYeqRBk4630PBA6ruBHDa+Ezxa+ot4w4lgE33zPIyNnzJ3D dTgHMGKzj/TNLRLTx1B+IJvHoh1sY1RCogaNWJ/Pgi3y5Wd4Iffv/9mUGLb3pW4RK81+q6YTK YY9iPL5F3pX7DQrO/xJkWme/oUAwJP049gm74EBn4LKnV1rP54dBRhQTj0stCHXbZ8aCY8gYc v+89X6RltU5Ptb2Wplvt99sdnEyb85zS3lw57Hl5Z2hkAxRKmy/tBpt72WWGmtjZRWT/fkAPM TZtomYXwpNTdtRl94Pyv0/HmkIMSA4L4jyNGsB3drYBol3oyyJ/4niEfLXlFgKHT4lzeO1MHM j9qk1YSMlEx2v7KgVvluc/x3vyoj/pcbLHdkL0xkoEunfPrfyWsxwQU5C87K9H2Y9GoE/Hhcj Gepabk1f5e1dxVFrAvHpxwyCV1/0G4NxjvOSqZqXN//P+uEm3SLlnOmldfKNOtdlLakHrghc1 H8hnJS1BAOhZwpnAEer3KlxPQqHkY6zAHs4Fldia/ANUy9viBMrqaclFJsRNO7fzEoyX6N73f af9xtZdr4ZbMf4WwzO9q2VGJg5h+Im0ILjUqgYgoA/JbzQBSire9ErIEo9J7TVxWa4hEuqVxF wrmhCChpMAMlbRqg9XbsID3FQoGPSZIBWgbBt0PrE8ntkr6yGlcyC9ezBxoIG6XowiLHivzG3 0KxC2DBXJ2pGwWLjXjwafwGCF/d3S4bfVe8f5XuLIZ0p2tFyC32Bgt5ZlpU3CmvcNg4gitiB9 r3nVhoqycmtQ0bs7fgyryAZUAxNw5dmJ4Bp9hl196irU/Fdy6a1zwH8JfUPB4XQ4OHCVG8YQw 05NoycP93i789V7ZzsaZiS5o5SBXCfx6OFBF0sIgNwJqKxxDyQo7RY0sRcOf8TzSNEEURmlw4 oXiH8aqVL4yvLfIYhfclXD1zZzjV2YMiM5dd77brc30OBr09C7oe/iYeOP6eV6tFHMa/29MCp mrXYnCy+yaAY4f49g9PWbpiQ5E6c55GInx41N2637GQAekCA81AeHcb8d4lUb6X0574Gg1DeH hm/fEOJSKndp18= X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Wim Van Sebroeck , linux-watchdog@vger.kernel.org, Stephen Boyd , Patrick Venture , Michael Turquette , Daniel Lezcano , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Avi Fishman , Rob Herring , Benjamin Fair , Philipp Zabel , Krzysztof Kozlowski , Tali Perry , Thomas Gleixner , Guenter Roeck , Tomer Maimon Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" On the Nuvoton WPCM450 SoC, with its upcoming clock driver, peripheral clocks are individually gated and ungated. Therefore, the watchdog driver must be able to ungate the watchdog clock. Signed-off-by: Jonathan Neuschäfer --- v3: - Add enable/disable calls to npcm_wdt_restart handler - Not applied due to the above change: Acked-by: Guenter Roeck v2: - https://lore.kernel.org/lkml/20220429172030.398011-4-j.neuschaefer@gmx.net/ - Add clk_disable_unprepare call, suggested by Guenter Roeck v1: - https://lore.kernel.org/lkml/20220422183012.444674-4-j.neuschaefer@gmx.net/ --- drivers/watchdog/npcm_wdt.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) -- 2.35.1 diff --git a/drivers/watchdog/npcm_wdt.c b/drivers/watchdog/npcm_wdt.c index 28a24caa2627c..a1240a906ef2a 100644 --- a/drivers/watchdog/npcm_wdt.c +++ b/drivers/watchdog/npcm_wdt.c @@ -3,6 +3,7 @@ // Copyright (c) 2018 IBM Corp. #include +#include #include #include #include @@ -43,6 +44,7 @@ struct npcm_wdt { struct watchdog_device wdd; void __iomem *reg; + struct clk *clk; }; static inline struct npcm_wdt *to_npcm_wdt(struct watchdog_device *wdd) @@ -66,6 +68,9 @@ static int npcm_wdt_start(struct watchdog_device *wdd) struct npcm_wdt *wdt = to_npcm_wdt(wdd); u32 val; + if (wdt->clk) + clk_prepare_enable(wdt->clk); + if (wdd->timeout < 2) val = 0x800; else if (wdd->timeout < 3) @@ -100,6 +105,9 @@ static int npcm_wdt_stop(struct watchdog_device *wdd) writel(0, wdt->reg); + if (wdt->clk) + clk_disable_unprepare(wdt->clk); + return 0; } @@ -147,9 +155,15 @@ static int npcm_wdt_restart(struct watchdog_device *wdd, { struct npcm_wdt *wdt = to_npcm_wdt(wdd); + if (wdt->clk) + clk_prepare_enable(wdt->clk); + writel(NPCM_WTR | NPCM_WTRE | NPCM_WTE, wdt->reg); udelay(1000); + if (wdt->clk) + clk_disable_unprepare(wdt->clk); + return 0; } @@ -191,6 +205,10 @@ static int npcm_wdt_probe(struct platform_device *pdev) if (IS_ERR(wdt->reg)) return PTR_ERR(wdt->reg); + wdt->clk = devm_clk_get_optional(&pdev->dev, NULL); + if (IS_ERR(wdt->clk)) + return PTR_ERR(wdt->clk); + irq = platform_get_irq(pdev, 0); if (irq < 0) return irq; From patchwork Sun May 8 19:43:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 1628161 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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secure) header.d=gmx.net header.i=@gmx.net header.a=rsa-sha256 header.s=badeba3b8450 header.b=BsbbGe7O; dkim-atps=neutral X-Original-To: openbmc@lists.ozlabs.org Delivered-To: openbmc@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmx.net (client-ip=212.227.17.22; helo=mout.gmx.net; envelope-from=j.neuschaefer@gmx.net; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.a=rsa-sha256 header.s=badeba3b8450 header.b=BsbbGe7O; dkim-atps=neutral Received: from mout.gmx.net (mout.gmx.net [212.227.17.22]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4KxFB33yfPz3bdj for ; Mon, 9 May 2022 05:44:27 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1652039031; bh=cVIo2y04SnJPxviT81wXrXj4/hncq3oQghRYaLvheWw=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=BsbbGe7O8H1fXGsZQUVAOfsz/cANTh74gyGsuekiNMaC5m6j3S25Dl60GidDvmFdp A72HpsBZgFnT74oULRy9xOpExAcvKuWGAjD1s5aNqcz7/cXvYBg4TiSKeUvIeloXFs DgCC/PXikYCESZz8U8sN0CA5jqAW+KNPGARr+Q8E= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([37.201.215.103]) by mail.gmx.net (mrgmx105 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MEm27-1nZDoa1Sv5-00GJfz; Sun, 08 May 2022 21:43:51 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Subject: [PATCH v3 4/7] dt-bindings: clock: Add Nuvoton WPCM450 clock/reset controller Date: Sun, 8 May 2022 21:43:29 +0200 Message-Id: <20220508194333.2170161-5-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220508194333.2170161-1-j.neuschaefer@gmx.net> References: <20220508194333.2170161-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:x0W7vH7QZ+HL+wxKDa4ZeKQqLWBOeq5uBVM+JKwP9VO9iVhbmIB tKKyNSd3lKZLMW8+kbKfyUQIF7JVxjnYP3u2axzi03CjKSdJo9WULQ8SWlaqGKVzcYvHQE+ oswdlr2sZLCwzDG2EVR2EVaadhd8LBtttvSPYXB8U2S9dztu+qjLRchJyYmZIVhP+nM2Xyh r2eNJJA9wCk9yaJeMg4QQ== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1;V03:K0:k9PwBt0AZnw=:R6ZVN4PsqfDOc7pT9fbOxo SSkddudSghnmvtDG/oL6e2O8JlKyqpQ04f7wHCUfoj78bJulhiK97tlktmFiKKVHwMgv3BT9z NmGF1I2MY486F/ijhlLDimdB4qwhXugQSrNYsPNnNeJjcYYVaE7VomsnzOpRGSQCFnz4ShbNk fyq+EWs14oyzf+KS7gSHEpLEtD2/M72H2kEtUkEvTXgbMvzDDnFjNSiAG8bmIGQ8Mn1rDiD03 DkgUSHkQpJmm42wRNsdgPfrRGzNwfhljaR0dh/nqe9wYKxCA2Qm3Ew/u+9WHAiy9DGdGnUu1y DlBwHY3NbCut/PU6LMudCue43ayzvCLIgsdCiJPH2MuS9E2hULDvBEF30A8JB8MEYqj4T7wGl hkxki/tNaYtrFGheJEHSxh/IKmqFWz5CAPgD+nam8nPVwX6+qrJ4JKa096UYQtDa7rt9D2YcZ RxvvP36QHkFfV+KP4YVjs0s4ohSiucUVgLx3C6vWYcuvYH6l9tS1/0dqpSwS+WuCoFH7QzZZg /3+D8prJnxERA1j2eTlpihm+SPHRA0NBp78duSRTTyzyTgoogi20vmnIOm9UteDlih9QoLlj8 j8ea9s5gGjCiA7veIVsxEyGMu64MRzLpJ4VPJ/s+yLZAUNPUMEYPQS8zdRQEzgcI3OXOd05LC NBOTdkE0h3AXB8e0pcKJrT4S+QMmbMdYXPyxLZi622ZYfLW9xSGmcX5nHWuqlEwWV5r593l7a BzblKc3SYhT+GWVlWvYw+I9JerbiDZBUGFj0S5IPVefgIkhUGpEnFHehRB7QCsrUFH28vfSHP bk1Bo/G2JaufCqVKcF3MRX0s+VpTJeKhNCGmQCcygc+sQfAQOK4TiiUzLFdlq3v9LYKDZlQdD 4nixZzSP61HqntLrlVucs6VbGYAue5HSYj0+j5BY6BgqJ0VIJMeRY7VJz9LxDfFJJY/NXtYNa 1j4gk5VQpKoKKCMoZj0Def0vQzrPyl4Wy0ueftXNwJ82te09uKmYKNz8rU5mhZkqIj05XoXKh FMwzBoq7z12q/X9a3iPWVToZdVzFl9emCfglBF9gqzF1NygfBOppZEr52oAgT+VK1iMOZbIOV QsDBLYtftrpme4= X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Wim Van Sebroeck , linux-watchdog@vger.kernel.org, Stephen Boyd , Patrick Venture , Michael Turquette , Daniel Lezcano , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Avi Fishman , Rob Herring , Benjamin Fair , Philipp Zabel , Krzysztof Kozlowski , Tali Perry , Thomas Gleixner , Guenter Roeck , Tomer Maimon Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" The Nuvoton WPCM450 SoC has a combined clock and reset controller. Add a devicetree binding for it, as well as definitions for the bit numbers used by it. Signed-off-by: Jonathan Neuschäfer --- v3: - Change clock-output-names and clock-names from "refclk" to "ref", suggested by Krzysztof Kozlowski v2: - https://lore.kernel.org/lkml/20220429172030.398011-5-j.neuschaefer@gmx.net/ - Various improvements, suggested by Krzysztof Kozlowski v1: - https://lore.kernel.org/lkml/20220422183012.444674-5-j.neuschaefer@gmx.net/ --- .../bindings/clock/nuvoton,wpcm450-clk.yaml | 66 ++++++++++++++++++ .../dt-bindings/clock/nuvoton,wpcm450-clk.h | 67 +++++++++++++++++++ 2 files changed, 133 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml create mode 100644 include/dt-bindings/clock/nuvoton,wpcm450-clk.h -- 2.35.1 diff --git a/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml b/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml new file mode 100644 index 0000000000000..525024a58df4c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/nuvoton,wpcm450-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton WPCM450 clock controller + +maintainers: + - Jonathan Neuschäfer + +description: + The clock controller of the Nuvoton WPCM450 SoC supplies clocks and resets to + the rest of the chip. + +properties: + compatible: + const: nuvoton,wpcm450-clk + + reg: + maxItems: 1 + + clocks: + items: + - description: Reference clock oscillator (should be 48 MHz) + + clock-names: + items: + - const: ref + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +examples: + - | + #include + #include + + refclk: clock-48mhz { + /* 48 MHz reference oscillator */ + compatible = "fixed-clock"; + clock-output-names = "ref"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + + clk: clock-controller@b0000200 { + reg = <0xb0000200 0x100>; + compatible = "nuvoton,wpcm450-clk"; + clocks = <&refclk>; + clock-names = "ref"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/nuvoton,wpcm450-clk.h b/include/dt-bindings/clock/nuvoton,wpcm450-clk.h new file mode 100644 index 0000000000000..86e1c895921b7 --- /dev/null +++ b/include/dt-bindings/clock/nuvoton,wpcm450-clk.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H +#define _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H + +/* Clocks based on CLKEN bits */ +#define WPCM450_CLK_FIU 0 +#define WPCM450_CLK_XBUS 1 +#define WPCM450_CLK_KCS 2 +#define WPCM450_CLK_SHM 4 +#define WPCM450_CLK_USB1 5 +#define WPCM450_CLK_EMC0 6 +#define WPCM450_CLK_EMC1 7 +#define WPCM450_CLK_USB0 8 +#define WPCM450_CLK_PECI 9 +#define WPCM450_CLK_AES 10 +#define WPCM450_CLK_UART0 11 +#define WPCM450_CLK_UART1 12 +#define WPCM450_CLK_SMB2 13 +#define WPCM450_CLK_SMB3 14 +#define WPCM450_CLK_SMB4 15 +#define WPCM450_CLK_SMB5 16 +#define WPCM450_CLK_HUART 17 +#define WPCM450_CLK_PWM 18 +#define WPCM450_CLK_TIMER0 19 +#define WPCM450_CLK_TIMER1 20 +#define WPCM450_CLK_TIMER2 21 +#define WPCM450_CLK_TIMER3 22 +#define WPCM450_CLK_TIMER4 23 +#define WPCM450_CLK_MFT0 24 +#define WPCM450_CLK_MFT1 25 +#define WPCM450_CLK_WDT 26 +#define WPCM450_CLK_ADC 27 +#define WPCM450_CLK_SDIO 28 +#define WPCM450_CLK_SSPI 29 +#define WPCM450_CLK_SMB0 30 +#define WPCM450_CLK_SMB1 31 + +/* Other clocks */ +#define WPCM450_CLK_USBPHY 32 + +#define WPCM450_NUM_CLKS 33 + +/* Resets based on IPSRST bits */ +#define WPCM450_RESET_FIU 0 +#define WPCM450_RESET_EMC0 6 +#define WPCM450_RESET_EMC1 7 +#define WPCM450_RESET_USB0 8 +#define WPCM450_RESET_USB1 9 +#define WPCM450_RESET_AES_PECI 10 +#define WPCM450_RESET_UART 11 +#define WPCM450_RESET_MC 12 +#define WPCM450_RESET_SMB2 13 +#define WPCM450_RESET_SMB3 14 +#define WPCM450_RESET_SMB4 15 +#define WPCM450_RESET_SMB5 16 +#define WPCM450_RESET_PWM 18 +#define WPCM450_RESET_TIMER 19 +#define WPCM450_RESET_ADC 27 +#define WPCM450_RESET_SDIO 28 +#define WPCM450_RESET_SSPI 29 +#define WPCM450_RESET_SMB0 30 +#define WPCM450_RESET_SMB1 31 + +#define WPCM450_NUM_RESETS 32 + +#endif /* _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H */ From patchwork Sun May 8 19:43:30 2022 Content-Type: text/plain; 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Mon, 9 May 2022 05:44:26 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1652039032; bh=STTQoU0Sy8AHWtV5pttLaup41ExmdLj7vMbHpMMcIaI=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=YX/rOCUpfUos0952/SYCVcW3WeHHLmrfMa+TpEoqiKWo/5gghjBsirvjryF8uyO1k hl221DfyokbMxUUhatWD2Ur8TSkSgJlYWCqXP6y3TU59UUVvbfBPv6fRqjKQ/Jeogw 2GSuQzWAi/PAgh7bZwFOmVxnIOMFWPe7X4+b/u+s= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([37.201.215.103]) by mail.gmx.net (mrgmx105 [212.227.17.168]) with ESMTPSA (Nemesis) id 1N7QxB-1nrZRd2Fif-017jSc; Sun, 08 May 2022 21:43:52 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Subject: [PATCH v3 5/7] ARM: dts: wpcm450: Add clock controller node Date: Sun, 8 May 2022 21:43:30 +0200 Message-Id: <20220508194333.2170161-6-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220508194333.2170161-1-j.neuschaefer@gmx.net> References: <20220508194333.2170161-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:0ezSuU0zJBwh/ZGu333EDA+hPHK33sk6Mj8LKS926qLuWkkV0Lr dlWJ34pFrBPMP+BubdQlge6s8v05g/+Pw8q/DkOblN8fJZJXz6/G+h55hNbBSRoVg5QhuME c96yu2NoB9ByjKLcIk9UWVAlf3xUNrZdS+U7kt13w8l9lH6rxbylF9SfU8+ygCu1iIR94GN EeW6+i0WdHMcl83YXieiw== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1;V03:K0:hBfIvakNOYo=:mxNjkROiVYonEK1pOMv76V AV7jo26iOQybtrajPGVaCxGrHTPgAyZsyu50/u9Mmv4K1driDuNWXBaowvw1FtK8/mzmpBhoD ek9Nq6pzPavd+mUnYrSTtbMQV1ScIKduBP28Fy4Qu4GpS9JPoV/m/hxGwn1wEZ1KTyj9gYO2t mavKGYhY3MnbowCvFso/PyyHDGjChrTjPwl9pnXIpZ4Pwh/e4TG7od9X3Hs0MWrOdZZJ8x6Hp H7CXRX74gqZp4XW/WFCBGjdxKGKS74Qvm1l3qa/yKWjjI14j2saDfR8Y84/OVbmPiexWIhhis hf3djXzT1jG6d5ngB/nQsdoj1Z9rKa73s+AGAjdkYHU7XvaGMvmXMOEZ97dDM6bfQrGn93jv+ gpUkNpSWVMygGr55tm8k64U63O0SvECs8O1K5wXu+b5b/jEDKrLIc+mn9+uMA/SU0EnKW49Zk EqVHNPAmRUVVzAxC8HbChhxIIitk3lQq6rfvYgtuZAnhPbIwEQzAxN2Ib5ZPebbqTJ4LHmC4d dLOJi8sRBEFuP1X6S9zVIVrATxtzeFJHG6mH2xUrmXAf5x2pPBaSjzU9McfoF+lOAnSROtxoC P9BGHAuiHW4iyEtnapDrDCE8M5ThGPAo7qNrHh2grPwhTgsYDPB7zma97V0qzfpmo1wxAtT4M v32a5Cwa+QgGbCo1J5pID+cFDXj40XRQVxvJsZb5e9Xw1tMQLu/DlLWJ0+M30Lv9UlLnW6ys1 dzK0ZpBoYa0jSJgcNhItaXBjEhSAFDv8ZY6wfgkpvz1vvtwPCFoYnMm6/w+GxrTYOq6+cT2SX LNdE3V2AGtV+XiupBIGJBFtSahNzuCCFybs5TjiIF70sBN2bXq2Km3a1sTTkCvhiq2B6aRqo0 vM2YkBjGuGAbW4XbYuQjAfITGIPYxnd/v7Hf3VnWP02TZVRj10k+KQgYqc8Ppn388JlW+N80P nnaKS+A2SWH/82N9jMiGR9DrnMLF1RnSwACB0szJuQ7jIFfeGs38LqQ2sUs7h9T7K7zZaTcJD 8+KITAnYZQ5ck33U0ABcd6j+skb4e+u6zUOurQT7nJoTu/haYTONEYx3WXf3nPdEzW+0ynB9e XadG9D6dDllPFc= X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Wim Van Sebroeck , linux-watchdog@vger.kernel.org, Stephen Boyd , Patrick Venture , Michael Turquette , Daniel Lezcano , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Avi Fishman , Rob Herring , Benjamin Fair , Philipp Zabel , Krzysztof Kozlowski , Tali Perry , Thomas Gleixner , Guenter Roeck , Tomer Maimon Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" This declares the clock controller and the necessary 48 Mhz reference clock in the WPCM450 device. Switching devices over to the clock controller is intentionally done in a separate patch to give time for the clock controller driver to land. Signed-off-by: Jonathan Neuschäfer --- v3: - Change clock-output-names and clock-names from "refclk" to "ref" v2: - https://lore.kernel.org/lkml/20220429172030.398011-6-j.neuschaefer@gmx.net/ - no changes --- arch/arm/boot/dts/nuvoton-wpcm450.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) -- 2.35.1 diff --git a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi index 1c63ab14c4383..515e943787416 100644 --- a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi +++ b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi @@ -39,6 +39,14 @@ clk24m: clock-24mhz { #clock-cells = <0>; }; + refclk: clock-48mhz { + /* 48 MHz reference oscillator */ + compatible = "fixed-clock"; + clock-output-names = "ref"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -51,6 +59,15 @@ gcr: syscon@b0000000 { reg = <0xb0000000 0x200>; }; + clk: clock-controller@b0000200 { + compatible = "nuvoton,wpcm450-clk"; + reg = <0xb0000200 0x100>; + clocks = <&refclk>; + clock-names = "ref"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + serial0: serial@b8000000 { compatible = "nuvoton,wpcm450-uart"; reg = <0xb8000000 0x20>; From patchwork Sun May 8 19:43:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 1628162 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.a=rsa-sha256 header.s=badeba3b8450 header.b=Dpfznk9P; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2404:9400:2:0:216:3eff:fee1:b9f1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4KxFHD65VTz9sFr for ; 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Mon, 9 May 2022 05:44:34 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1652039035; bh=ARdVvvj+QR6zj7jH7tmlSixKEYcbCohZuth1Zlpb6F4=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=Dpfznk9P5+Yq1uW37Fv+kXuztyzVDIJqiZ1RTH0o+osGfBHJO90neIqP/+FOyxJtc uwqj3Qlsc2B2Gffe4g+gZntbf2dT4xv+/r9oxkFdbLFnZ615SzAS9WECWigsgPNFrK Hty2UuYQUUGltmw/PqHEOrLDQsRRmeVFHIUS3wws= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([37.201.215.103]) by mail.gmx.net (mrgmx005 [212.227.17.190]) with ESMTPSA (Nemesis) id 1N6KUd-1nqTVy18WX-016eKc; Sun, 08 May 2022 21:43:55 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Subject: [PATCH v3 6/7] clk: wpcm450: Add Nuvoton WPCM450 clock/reset controller driver Date: Sun, 8 May 2022 21:43:31 +0200 Message-Id: <20220508194333.2170161-7-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220508194333.2170161-1-j.neuschaefer@gmx.net> References: <20220508194333.2170161-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:KrpzxJaSjCYOmWH1WrKsORKB3XhG/BxLuk+BPqLi4ogcSYKtqLf OWP9cG9FxjGoYQ9KxPIPzhQkWVg0cd7t9Jo2j6f46VPCExNnJDiTfoT9WI0f77BQhtp0HxG /nkghhKP7ya9gw4jiOrYctS8YU10mhgpZo55fkTGyXIsFo95TrU1M52MAEOmX8lSKN8x5vK SAhv3vArrb/5JqeMe2cgA== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1;V03:K0:agU9m9EU81E=:b49ndZc+x+GHg9prjc6On9 VyHjkR9O4Bo51NIQPB48B/VmmBOhi+CyHHWDWVowcAfxMJtyPF0L1DWqKcUQDmXaykCYh0lvx v8PoWV/5/jUmn1yRVIznPby2RXC9JCvjcwo9vZq4cTZEbOKgM9km4PzRVzFTN9V57h0UiHyIX 0KjbOD9eCO+iwhEz8VRxz0vk28iEtd07U96LNlHrAbUaSzh2UQwxdIAuJU0T7jPNyq347erUn MQMESDHVfL3dgUZl8Wbd9Eg+71FqVaZPab7PB9f/xtXz/W3RhVtKsO2glPxHG3m/hz5YENz53 89Gacz0BqrpzrH1dwC5jVAgC5qybsNuU9l2xOc/GDCUo0L42S1YkmRCEAtqHWjtIORV9p3W+W +JDE7HyU4Dxbs3SsmgEbun6Z1iIDEnWt6/U7Tw9+0tA3kUjGHnVp8Vw5pkV1433NiRlfkoN7S mSuExaeiYsOx7U+7+8fnXqAgjpfPdD+4Zg69gHxKMx+ibJpSQMQDu8znq6CGaEL/xbCiVaKxG IuqCqOl22G6dQXDnnv8iD1yPFG5c6izB9RvJV64KpO6GQYC45YjshlCN+U/hOu7plv/nmTdkk 78ykgJfxT3bABT+wE7gNoRzqkgpHZnb/elB4odJeLljOz9k2hHpvX715TpNBDo3RrOiYJ8c4H TxZzoZFNND9CrHSbvo2uyYuZiVtFmagly0VZgCF6+e00g4RJTIOVELDf20mmBRXpR/SGP4n4B QsD8HgFPzogCBn9ZdfRRxWErMg6U5XycidieCpRYuzDmlbBHmPdnGvH2p7B5G2pqJrqvbBH28 ud6ltgGXtSJVFR2A0uCBsDrWqgWOgUlBjXc8DXAoavUusyxJ490+SjWCaqEXYA1iPTkNnLXM3 yufm2jvSINukOJMhs0flAw1bcEJGhqUdZ4cwI0SATbi7Mdw4GVV3Ozucq5vwB23r8rYrpkFpi HIxI2Q1uNleK111zoBsWTuMKvrR9ZULQ1x9Mne37/bLQ3LSSMMJaFToe9YNgurVLuCagL37UZ 2gubdWdltOppIJSN6RZ2/4Fszlr2QnRylesnhwJKxhMdjazcT5KkJD7PVarQ6d5RvJufozvzg Epu0x12hbKWLgs= X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Wim Van Sebroeck , linux-watchdog@vger.kernel.org, Stephen Boyd , Patrick Venture , Michael Turquette , Daniel Lezcano , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Avi Fishman , Rob Herring , Benjamin Fair , Philipp Zabel , Krzysztof Kozlowski , Tali Perry , Thomas Gleixner , Guenter Roeck , Tomer Maimon Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" This driver implements the following features w.r.t. the clock and reset controller in the WPCM450 SoC: - It calculates the rates for all clocks managed by the clock controller - It leaves the clock tree mostly unchanged, except that it enables/ disables clock gates based on usage. - It exposes the reset lines managed by the controller using the Generic Reset Controller subsystem NOTE: If the driver and the corresponding devicetree node are present, the driver will disable "unused" clocks. This is problem until the clock relations are properly declared in the devicetree (in a later patch). Until then, the clk_ignore_unused kernel parameter can be used as a workaround. Signed-off-by: Jonathan Neuschäfer --- v3: - Change reference clock name from "refclk" to "ref" - Remove unused variable in return path of wpcm450_clk_register_pll - Remove unused divisor tables v2: - https://lore.kernel.org/lkml/20220429172030.398011-7-j.neuschaefer@gmx.net/ - no changes --- drivers/clk/Makefile | 1 + drivers/clk/clk-wpcm450.c | 363 ++++++++++++++++++++++++++++++++++++++ drivers/reset/Kconfig | 2 +- 3 files changed, 365 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/clk-wpcm450.c -- 2.35.1 diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 2bd5ffd595bf3..07edb0f4ba8ba 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -73,6 +73,7 @@ obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o obj-$(CONFIG_COMMON_CLK_RS9_PCIE) += clk-renesas-pcie.o obj-$(CONFIG_COMMON_CLK_VC5) += clk-versaclock5.o obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o +obj-$(CONFIG_ARCH_WPCM450) += clk-wpcm450.o obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o # please keep this section sorted lexicographically by directory path name diff --git a/drivers/clk/clk-wpcm450.c b/drivers/clk/clk-wpcm450.c new file mode 100644 index 0000000000000..09f40d6f9c896 --- /dev/null +++ b/drivers/clk/clk-wpcm450.c @@ -0,0 +1,363 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Nuvoton WPCM450 clock and reset controller driver. + * + * Copyright (C) 2022 Jonathan Neuschäfer + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +struct wpcm450_clk_pll { + struct clk_hw hw; + void __iomem *pllcon; + u8 flags; +}; + +#define to_wpcm450_clk_pll(_hw) container_of(_hw, struct wpcm450_clk_pll, hw) + +#define PLLCON_FBDV GENMASK(24, 16) +#define PLLCON_PRST BIT(13) +#define PLLCON_PWDEN BIT(12) +#define PLLCON_OTDV GENMASK(10, 8) +#define PLLCON_INDV GENMASK(5, 0) + +static unsigned long wpcm450_clk_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct wpcm450_clk_pll *pll = to_wpcm450_clk_pll(hw); + unsigned long fbdv, indv, otdv; + u64 rate; + u32 pllcon; + + if (parent_rate == 0) { + pr_err("%s: parent rate is zero", __func__); + return 0; + } + + pllcon = readl_relaxed(pll->pllcon); + + indv = FIELD_GET(PLLCON_INDV, pllcon) + 1; + fbdv = FIELD_GET(PLLCON_FBDV, pllcon) + 1; + otdv = FIELD_GET(PLLCON_OTDV, pllcon) + 1; + + rate = (u64)parent_rate * fbdv; + do_div(rate, indv * otdv); + + return rate; +} + +static int wpcm450_clk_pll_is_enabled(struct clk_hw *hw) +{ + struct wpcm450_clk_pll *pll = to_wpcm450_clk_pll(hw); + u32 pllcon; + + pllcon = readl_relaxed(pll->pllcon); + + return !(pllcon & PLLCON_PRST); +} + +static void wpcm450_clk_pll_disable(struct clk_hw *hw) +{ + struct wpcm450_clk_pll *pll = to_wpcm450_clk_pll(hw); + u32 pllcon; + + pllcon = readl_relaxed(pll->pllcon); + pllcon |= PLLCON_PRST | PLLCON_PWDEN; + writel(pllcon, pll->pllcon); +} + +static const struct clk_ops wpcm450_clk_pll_ops = { + .recalc_rate = wpcm450_clk_pll_recalc_rate, + .is_enabled = wpcm450_clk_pll_is_enabled, + .disable = wpcm450_clk_pll_disable +}; + +static struct clk_hw * +wpcm450_clk_register_pll(void __iomem *pllcon, const char *name, + const char *parent_name, unsigned long flags) +{ + struct wpcm450_clk_pll *pll; + struct clk_init_data init; + int ret; + + pll = kzalloc(sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.ops = &wpcm450_clk_pll_ops; + init.parent_names = &parent_name; + init.num_parents = 1; + init.flags = flags; + + pll->pllcon = pllcon; + pll->hw.init = &init; + + ret = clk_hw_register(NULL, &pll->hw); + if (ret) { + kfree(pll); + return ERR_PTR(ret); + } + + return &pll->hw; +} + +#define REG_CLKEN 0x00 +#define REG_CLKSEL 0x04 +#define REG_CLKDIV 0x08 +#define REG_PLLCON0 0x0c +#define REG_PLLCON1 0x10 +#define REG_PMCON 0x14 +#define REG_IRQWAKECON 0x18 +#define REG_IRQWAKEFLAG 0x1c +#define REG_IPSRST 0x20 + +struct wpcm450_pll_data { + const char *name; + const char *parent_name; + unsigned int reg; + unsigned long flags; +}; + +static const struct wpcm450_pll_data pll_data[] = { + { "pll0", "ref", REG_PLLCON0, 0 }, + { "pll1", "ref", REG_PLLCON1, 0 }, +}; + +struct wpcm450_clksel_data { + const char *name; + const char *const *parent_names; + unsigned int num_parents; + const u32 *table; + int shift; + int width; + int index; + unsigned long flags; +}; + +static const u32 parent_table[] = { 0, 1, 2 }; +static const char *const default_parents[] = { "pll0", "pll1", "ref" }; +static const char *const huart_parents[] = { "ref", "refdiv2" }; + +static const struct wpcm450_clksel_data clksel_data[] = { + { "cpusel", default_parents, ARRAY_SIZE(default_parents), + parent_table, 0, 2, -1, CLK_IS_CRITICAL }, + { "clkout", default_parents, ARRAY_SIZE(default_parents), + parent_table, 2, 2, -1, 0 }, + { "usbphy", default_parents, ARRAY_SIZE(default_parents), + parent_table, 6, 2, -1, 0 }, + { "uartsel", default_parents, ARRAY_SIZE(default_parents), + parent_table, 8, 2, WPCM450_CLK_USBPHY, 0 }, + { "huartsel", huart_parents, ARRAY_SIZE(huart_parents), + parent_table, 10, 1, -1, 0 }, +}; + +static const struct clk_div_table div_fixed2[] = { + { .val = 0, .div = 2 }, + { } +}; + +struct wpcm450_clkdiv_data { + const char *name; + const char *parent_name; + int div_flags; + const struct clk_div_table *table; + int shift; + int width; + unsigned long flags; +}; + +static struct wpcm450_clkdiv_data clkdiv_data_early[] = { + { "refdiv2", "ref", 0, div_fixed2, 0, 0 }, +}; + +static const struct wpcm450_clkdiv_data clkdiv_data[] = { + { "cpu", "cpusel", 0, div_fixed2, 0, 0, CLK_IS_CRITICAL }, + { "adcdiv", "ref", CLK_DIVIDER_POWER_OF_TWO, NULL, 28, 2, 0 }, + { "apb", "ahb", CLK_DIVIDER_POWER_OF_TWO, NULL, 26, 2, 0 }, + { "ahb", "cpu", CLK_DIVIDER_POWER_OF_TWO, NULL, 24, 2, 0 }, + { "uart", "uartsel", 0, NULL, 16, 4, 0 }, + { "ahb3", "ahb", CLK_DIVIDER_POWER_OF_TWO, NULL, 8, 2, 0 }, +}; + +struct wpcm450_clken_data { + const char *name; + const char *parent_name; + int bitnum; + unsigned long flags; +}; + +static const struct wpcm450_clken_data clken_data[] = { + { "fiu", "ahb3", WPCM450_CLK_FIU, 0 }, + { "xbus", "ahb3", WPCM450_CLK_XBUS, 0 }, + { "kcs", "apb", WPCM450_CLK_KCS, 0 }, + { "shm", "ahb3", WPCM450_CLK_SHM, 0 }, + { "usb1", "ahb", WPCM450_CLK_USB1, 0 }, + { "emc0", "ahb", WPCM450_CLK_EMC0, 0 }, + { "emc1", "ahb", WPCM450_CLK_EMC1, 0 }, + { "usb0", "ahb", WPCM450_CLK_USB0, 0 }, + { "peci", "apb", WPCM450_CLK_PECI, 0 }, + { "aes", "apb", WPCM450_CLK_AES, 0 }, + { "uart0", "uart", WPCM450_CLK_UART0, 0 }, + { "uart1", "uart", WPCM450_CLK_UART1, 0 }, + { "smb2", "apb", WPCM450_CLK_SMB2, 0 }, + { "smb3", "apb", WPCM450_CLK_SMB3, 0 }, + { "smb4", "apb", WPCM450_CLK_SMB4, 0 }, + { "smb5", "apb", WPCM450_CLK_SMB5, 0 }, + { "huart", "huartsel", WPCM450_CLK_HUART, 0 }, + { "pwm", "apb", WPCM450_CLK_PWM, 0 }, + { "timer0", "refdiv2", WPCM450_CLK_TIMER0, 0 }, + { "timer1", "refdiv2", WPCM450_CLK_TIMER1, 0 }, + { "timer2", "refdiv2", WPCM450_CLK_TIMER2, 0 }, + { "timer3", "refdiv2", WPCM450_CLK_TIMER3, 0 }, + { "timer4", "refdiv2", WPCM450_CLK_TIMER4, 0 }, + { "mft0", "apb", WPCM450_CLK_MFT0, 0 }, + { "mft1", "apb", WPCM450_CLK_MFT1, 0 }, + { "wdt", "refdiv2", WPCM450_CLK_WDT, 0 }, + { "adc", "adcdiv", WPCM450_CLK_ADC, 0 }, + { "sdio", "ahb", WPCM450_CLK_SDIO, 0 }, + { "sspi", "apb", WPCM450_CLK_SSPI, 0 }, + { "smb0", "apb", WPCM450_CLK_SMB0, 0 }, + { "smb1", "apb", WPCM450_CLK_SMB1, 0 }, +}; + +static DEFINE_SPINLOCK(wpcm450_clk_lock); + +static void __init wpcm450_clk_init(struct device_node *clk_np) +{ + struct clk_hw_onecell_data *clk_data; + static struct clk_hw **hws; + static struct clk_hw *hw; + void __iomem *clk_base; + int i, ret; + struct reset_controller_dev *rcdev; + + clk_base = of_iomap(clk_np, 0); + if (!clk_base) { + pr_err("%pOFP: failed to map registers\n", clk_np); + of_node_put(clk_np); + return; + } + of_node_put(clk_np); + + clk_data = kzalloc(struct_size(clk_data, hws, WPCM450_NUM_CLKS), GFP_KERNEL); + if (!clk_data) + goto err_unmap; + + clk_data->num = WPCM450_NUM_CLKS; + hws = clk_data->hws; + + for (i = 0; i < WPCM450_NUM_CLKS; i++) + hws[i] = ERR_PTR(-ENOENT); + + // PLLs + for (i = 0; i < ARRAY_SIZE(pll_data); i++) { + const struct wpcm450_pll_data *data = &pll_data[i]; + + hw = wpcm450_clk_register_pll(clk_base + data->reg, data->name, + data->parent_name, data->flags); + if (IS_ERR(hw)) { + pr_info("Failed to register PLL: %pe", hw); + goto err_free; + } + } + + // Early divisors (REF/2) + for (i = 0; i < ARRAY_SIZE(clkdiv_data_early); i++) { + const struct wpcm450_clkdiv_data *data = &clkdiv_data_early[i]; + + hw = clk_hw_register_divider_table(NULL, data->name, data->parent_name, + data->flags, clk_base + REG_CLKDIV, + data->shift, data->width, data->div_flags, + data->table, &wpcm450_clk_lock); + if (IS_ERR(hw)) { + pr_err("Failed to register div table: %pe\n", hw); + goto err_free; + } + } + + // Selects/muxes + for (i = 0; i < ARRAY_SIZE(clksel_data); i++) { + const struct wpcm450_clksel_data *data = &clksel_data[i]; + + hw = clk_hw_register_mux_table(NULL, data->name, data->parent_names, + data->num_parents, data->flags, + clk_base + REG_CLKSEL, data->shift, + BIT(data->width) - 1, 0, data->table, + &wpcm450_clk_lock); + if (IS_ERR(hw)) { + pr_err("Failed to register mux: %pe\n", hw); + goto err_free; + } + if (data->index >= 0) + clk_data->hws[data->index] = hw; + } + + // Divisors + for (i = 0; i < ARRAY_SIZE(clkdiv_data); i++) { + const struct wpcm450_clkdiv_data *data = &clkdiv_data[i]; + + hw = clk_hw_register_divider_table(NULL, data->name, data->parent_name, + data->flags, clk_base + REG_CLKDIV, + data->shift, data->width, data->div_flags, + data->table, &wpcm450_clk_lock); + if (IS_ERR(hw)) { + pr_err("Failed to register divider: %pe\n", hw); + goto err_free; + } + } + + // Enables/gates + for (i = 0; i < ARRAY_SIZE(clken_data); i++) { + const struct wpcm450_clken_data *data = &clken_data[i]; + + hw = clk_hw_register_gate(NULL, data->name, data->parent_name, data->flags, + clk_base + REG_CLKEN, data->bitnum, + data->flags, &wpcm450_clk_lock); + if (IS_ERR(hw)) { + pr_err("Failed to register gate: %pe\n", hw); + goto err_free; + } + clk_data->hws[data->bitnum] = hw; + } + + ret = of_clk_add_hw_provider(clk_np, of_clk_hw_onecell_get, clk_data); + if (ret) + pr_err("Failed to add DT provider: %d\n", ret); + + // Reset controller + rcdev = kzalloc(sizeof(*rcdev), GFP_KERNEL); + if (!rcdev) + goto err_free; + rcdev->owner = THIS_MODULE; + rcdev->nr_resets = WPCM450_NUM_RESETS; + rcdev->ops = &reset_simple_ops; + rcdev->of_node = clk_np; + ret = reset_controller_register(rcdev); + if (ret) + pr_err("Failed to register reset controller: %d\n", ret); + + of_node_put(clk_np); + return; + +err_free: + kfree(clk_data->hws); +err_unmap: + iounmap(clk_base); + of_node_put(clk_np); +} + +CLK_OF_DECLARE(wpcm450_clk_init, "nuvoton,wpcm450-clk", wpcm450_clk_init); diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index b496028b6bfaf..50a3c1403c335 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -201,7 +201,7 @@ config RESET_SCMI config RESET_SIMPLE bool "Simple Reset Controller Driver" if COMPILE_TEST - default ARCH_ASPEED || ARCH_BCM4908 || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC + default ARCH_ASPEED || ARCH_BCM4908 || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC || ARCH_NPCM help This enables a simple reset controller driver for reset lines that that can be asserted and deasserted by toggling bits in a contiguous, From patchwork Sun May 8 19:43:32 2022 Content-Type: text/plain; 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Mon, 9 May 2022 05:44:25 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1652039036; bh=ZMFFSXatdPBOGp95nTHs++I59HrGyDFQ5G/SIMPqqhM=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=RjEIdeqKWDmOJO5dgr+BdpN++zY6zcrKaVZ2pnkcdtLw5XNe3asI7lmlLvJNsJyXj PvVtQPC7xkGaziwR5ghao0q6zoDZWd0jjllui6MmaX0xEHS7IoWTcVCaCHLusQ+ID6 jZsZM3gb3oez8m7qJInVhpAihqewZ06TnaZY6F+Y= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([37.201.215.103]) by mail.gmx.net (mrgmx104 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MEm6F-1nZDoV2X3D-00GJDe; Sun, 08 May 2022 21:43:56 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Subject: [PATCH v3 7/7] ARM: dts: wpcm450: Switch clocks to clock controller Date: Sun, 8 May 2022 21:43:32 +0200 Message-Id: <20220508194333.2170161-8-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220508194333.2170161-1-j.neuschaefer@gmx.net> References: <20220508194333.2170161-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:kkDcTVKHYxQWJty64O/zo4HzicYg5+GXVtXaJFZY35ZwbBQKgYd zvZ0lSKISIrw6iDMJ30CaX1EaqdEq5W5IO9XJUBy0Gh7/8kqKAEiVS3LhmC6TI7z9IQucXf JqKzmNiJsHin8PcaWclRQQ5oU0oXvgvqiaouMJH5V6j0w9Kk4bgsuy7UwJU5jOzpZ74yA9m +xh6sCA5teAj0W96PLtEw== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1;V03:K0:h7PjhEGAGOY=:E9L81qjT7kzz0e1fwo1uT7 hP7PDfwv9bFJoDbDNnAEoAeD6NEVYJPBRko2AGHhE2c4NefKXvFE+mKhavU6F132Pc0Ga84WC jG+5Oc5Hg0WtD7vI/Qx9dcU7qjLROxeUhOAQCNiNkhbKs2MoOwUver026OQbwrsPgPm4LBmOC TLdqKJ1RVwRv5ZSzuT7chMxc4qU+YdCrkHBF58CgwQDz9YZA9ZG20hcKyLodBiv5SIDQSDjrS mu+3ffQjErTwwkioRN/2l7Be4b8Kzi4BcXTyLyL+CyNQT+bqRhIn+gQy8+Ye+RwPXOU+xipyd 6F1JK4aHJf6SzOJdNmWBUKNtkx8+p1SnJeVtjU6VpGuAIowdksfXwih+1vhYwFHR2benybRk3 E8tSm+YyqXHbPjjDqSkxn/5wYNXHfU6Vz/euXhJEVHPru0tHID+wPfTsSEKXfNBSSnfiYsT0E bbnHBmOe9CRkNO1noDUUixS6PItcivvP2Xo33MeSXE0eXUewx3f7xZnJG8xJA+Ggc0QavlIfn Hp6K9ZScZ6kAEBkRwPJrJuHhHsYdxFtRfdSyhjVQsAcZcmZrXYZv0sh/LB+8zpTSRu/NLoOFM AKfvDfBq+UspetCK7m3vnW7RCbvg2nIL14mwfcp02+y+l+uoB7d+Sl5U8EbFRlD6huvwpexvv ghDkuJ2yrptKI1a49kcTtECiYe+KNtR1BO+zEgTeM+TG0FNH3fq6lLcivQ6Uk+YycR1BTFNfF 3bU+WjihzPQF4h1OgOIHULAngsFKFw4FYFxDMXHp42pKDuJF7s+UhCKqZVDTpqRitgHEuG6JA BGtlo8BSF/TUlG4lwa7q+FcIwQEOLQQh1GalrIieqlKkeHNaeLuTGLlckdF0RetlbtheLLhqE Vp0SWHJDzskYAcEw6xGZdaLrBLQb9afN+UoydsSlz65hBfErrB/VC+v+HGnrxzsyn64s0Vlm4 tq798DMw7fpFLru9XucyPLtcNsGmQbgr2KZIgHvrJ5xGnlX7X+s1dfhULtOO8gS5FUYmLHwKi 7iibNhowRvgn9ewxJwU45M1lLex5AsQdEEFWnYMFkZ+9qi6BFFCHMCFTP1QmAgqwrQGhC2oME C30VTj5QQgijc0= X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Wim Van Sebroeck , linux-watchdog@vger.kernel.org, Stephen Boyd , Patrick Venture , Michael Turquette , Daniel Lezcano , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Avi Fishman , Rob Herring , Benjamin Fair , Philipp Zabel , Krzysztof Kozlowski , Tali Perry , Thomas Gleixner , Guenter Roeck , Tomer Maimon Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" This change is incompatible with older kernels because it requires the clock controller driver, but I think that's acceptable because WPCM450 support is generally still in an early phase. Signed-off-by: Jonathan Neuschäfer --- v2, v3: - no changes --- arch/arm/boot/dts/nuvoton-wpcm450.dtsi | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) -- 2.35.1 diff --git a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi index 515e943787416..d5ed95ef810e8 100644 --- a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi +++ b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi @@ -2,6 +2,7 @@ // Copyright 2021 Jonathan Neuschäfer #include +#include / { compatible = "nuvoton,wpcm450"; @@ -32,13 +33,6 @@ cpu@0 { }; }; - clk24m: clock-24mhz { - /* 24 MHz dummy clock */ - compatible = "fixed-clock"; - clock-frequency = <24000000>; - #clock-cells = <0>; - }; - refclk: clock-48mhz { /* 48 MHz reference oscillator */ compatible = "fixed-clock"; @@ -73,7 +67,7 @@ serial0: serial@b8000000 { reg = <0xb8000000 0x20>; reg-shift = <2>; interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk24m>; + clocks = <&clk WPCM450_CLK_UART0>; pinctrl-names = "default"; pinctrl-0 = <&bsp_pins>; status = "disabled"; @@ -84,7 +78,7 @@ serial1: serial@b8000100 { reg = <0xb8000100 0x20>; reg-shift = <2>; interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk24m>; + clocks = <&clk WPCM450_CLK_UART1>; status = "disabled"; }; @@ -92,14 +86,18 @@ timer0: timer@b8001000 { compatible = "nuvoton,wpcm450-timer"; interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; reg = <0xb8001000 0x1c>; - clocks = <&clk24m>; + clocks = <&clk WPCM450_CLK_TIMER0>, + <&clk WPCM450_CLK_TIMER1>, + <&clk WPCM450_CLK_TIMER2>, + <&clk WPCM450_CLK_TIMER3>, + <&clk WPCM450_CLK_TIMER4>; }; watchdog0: watchdog@b800101c { compatible = "nuvoton,wpcm450-wdt"; interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; reg = <0xb800101c 0x4>; - clocks = <&clk24m>; + clocks = <&clk WPCM450_CLK_WDT>; }; aic: interrupt-controller@b8002000 {