From patchwork Tue May 3 16:01:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 1625640 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=JORjjpNq; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4Kt4VT01n6z9sBB for ; Wed, 4 May 2022 02:02:40 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0CF983953834 for ; Tue, 3 May 2022 16:02:37 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 0CF983953834 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1651593757; bh=IuVDD3lbIe/uLeSGTOd0v/q9DcuPCba0uiNh/dExaT4=; h=Date:Subject:To:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=JORjjpNqVsqGB+QQfNBXUqcescie0LyDHnJ01d1ASVils48NAaPLwA738RTGKq8BE Q1phrtQxtp1V6dRKMrWu6EMJjkcwxB1MbXauoL95KveSX4uBMxHylhP4nUJr5NqVQ1 GPiFrnYa1NYyyoPr/Q5BOYTW9bqoUYCvlm0nh7w8= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-qt1-x832.google.com (mail-qt1-x832.google.com [IPv6:2607:f8b0:4864:20::832]) by sourceware.org (Postfix) with ESMTPS id F2C20395251C for ; Tue, 3 May 2022 16:01:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org F2C20395251C Received: by mail-qt1-x832.google.com with SMTP id fu47so13793322qtb.5 for ; Tue, 03 May 2022 09:01:54 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=IuVDD3lbIe/uLeSGTOd0v/q9DcuPCba0uiNh/dExaT4=; b=OrhJj8f6Vk0xvoYh7wC18p5aCfRasIIwFwcZXmZrYeiYBT6vLnyN2R/TbTipI3/nRl +ljjdWSO0Lo28Ko6LOSDrhTuxF7KRhfpgws/Ys1A+99Mp7tkt7Ym2EZ2C/+J6nWHhDXJ pSMt2Haji+rjELRgW0kK7AigGEjxXgsG5QwoPlbKawe11ilZAs0EqpGq9+kBZWFkGTGm ARpmEmFYYKsqKVMLQVwsenG8IuN+ntbgpKgDjX5xN97avtE2DpM4tq17tcOOeaITpQYB TwwU7jklO2mO2gFkuq7zcExmD5G+sTiA3fZHZnX8zM4qCMrcWq4uNhC7GUstcOYoHtb0 Spsg== X-Gm-Message-State: AOAM5337kwQs+Iz9xabUtNZVPscz8IQ8eH+ZWXiaj2lzkR8ucjHUKtae Zd0MWgw+Ky5UwbUkkt+s0evYeub2IVskhAbvuG38+mHSGwfipg== X-Google-Smtp-Source: ABdhPJzSTfIzVQPMHolXMqbarS2xlBF/WXNCuP6x7Gr3BJbwEOcVVCZ9J9cWOCKy12SHBSywJudMZEGCP0cvVQo/mj4= X-Received: by 2002:a05:622a:413:b0:2f3:7c4e:4303 with SMTP id n19-20020a05622a041300b002f37c4e4303mr15139289qtx.57.1651593713796; Tue, 03 May 2022 09:01:53 -0700 (PDT) MIME-Version: 1.0 Date: Tue, 3 May 2022 18:01:42 +0200 Message-ID: Subject: [PATCH] i386: Optimize _mm_storeu_si16 w/o SSE4 [PR105079] To: "gcc-patches@gcc.gnu.org" X-Spam-Status: No, score=-8.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Uros Bizjak via Gcc-patches From: Uros Bizjak Reply-To: Uros Bizjak Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Optimize _mm_storeu_si16 to use MOVD from a SSE to an integer register instead of PEXTRW from a low word of the SSE register to an integer reg. Avoid the transformation when optimizing for size for targets without TARGET_INTER_UNIT_MOVES_FROM_VEC capability, where the transformation results in two moves via a memory location. 2022-05-03 Uroš Bizjak gcc/ChangeLog: PR target/105079 * config/i386/sse.md (*vec_extract_0_mem): New pre-reload define_insn_and_split pattern. gcc/testsuite/ChangeLog: PR target/105079 * gcc.target/i386/pr105079.c: New test. * gcc.target/i386/pr95483-1.c (dg-options): Use -msse4.1. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Pushed to master. Uros. diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 5e93aa23b47..7b791def542 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -19021,6 +19021,26 @@ (define_insn "sse2_loadld" (define_mode_iterator PEXTR_MODE12 [(V16QI "TARGET_SSE4_1") V8HI]) +(define_insn_and_split "*vec_extract_0_mem" + [(set (match_operand: 0 "memory_operand") + (vec_select: + (match_operand:PEXTR_MODE12 1 "register_operand") + (parallel [(const_int 0)])))] + "TARGET_SSE2 + && !TARGET_SSE4_1 + && (TARGET_INTER_UNIT_MOVES_FROM_VEC + || optimize_function_for_speed_p (cfun)) + && ix86_pre_reload_split ()" + "#" + "&& 1" + [(set (match_dup 2) (match_dup 3)) + (set (match_dup 0) (match_dup 4))] +{ + operands[2] = gen_reg_rtx (SImode); + operands[3] = gen_lowpart (SImode, force_reg (mode, operands[1])); + operands[4] = gen_lowpart (mode, operands[2]); +}) + (define_insn "*vec_extract" [(set (match_operand: 0 "register_sse4nonimm_operand" "=r,m") (vec_select: diff --git a/gcc/testsuite/gcc.target/i386/pr105079.c b/gcc/testsuite/gcc.target/i386/pr105079.c new file mode 100644 index 00000000000..4ecf864afde --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr105079.c @@ -0,0 +1,11 @@ +/* PR target/105079 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2 -mno-sse4.1" } */ +/* { dg-final { scan-assembler-not "pextrw" } } */ + +#include + +void store16 (void *p, __m128i v) +{ + _mm_storeu_si16 (p, v); +} diff --git a/gcc/testsuite/gcc.target/i386/pr95483-1.c b/gcc/testsuite/gcc.target/i386/pr95483-1.c index 0f3e0bf9280..26b2e8275eb 100644 --- a/gcc/testsuite/gcc.target/i386/pr95483-1.c +++ b/gcc/testsuite/gcc.target/i386/pr95483-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -msse2" } */ +/* { dg-options "-O2 -msse4.1" } */ /* { dg-final { scan-assembler-times "pxor\[ \\t\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "pinsrw\[ \\t\]+\[^\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ /* { dg-final { scan-assembler-times "pextrw\[ \\t\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*(?:\n|\[ \\t\]+#)" 1 } } */