From patchwork Fri Apr 22 18:30:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 1621227 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.a=rsa-sha256 header.s=badeba3b8450 header.b=eyIq38Ti; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4KlT2r5Brdz9s09 for ; Sat, 23 Apr 2022 08:04:20 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231807AbiDVWHL (ORCPT ); Fri, 22 Apr 2022 18:07:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35150 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231637AbiDVWHE (ORCPT ); Fri, 22 Apr 2022 18:07:04 -0400 Received: from mout.gmx.net (mout.gmx.net [212.227.17.22]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4DE1F31DDC; Fri, 22 Apr 2022 13:52:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1650660721; bh=nH5nbmzHe/xRwz0pWDdjzn30b813GPDvATKACfo4I6g=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=eyIq38Ti8Xyoy7E0KkA29w0DkaRlW8dP8h5wyY9BNqYn3J9bSSzUP+PiTaibG9SWW ub/Uupa1SinGBG1AycTDetvFx9E3NVW1btY5UCZ0+WtMgR2lprvv76u7jqnf9PXAlo APJT4bkv9v2gXLwuJ7IC7ZKkhZzyEIufDZb39CVI= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([87.78.190.74]) by mail.gmx.net (mrgmx104 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MGQnF-1nh6473Djx-00GnuC; Fri, 22 Apr 2022 20:31:46 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Daniel Lezcano , Thomas Gleixner , Philipp Zabel , Wim Van Sebroeck , Guenter Roeck Subject: [PATCH 1/7] dt-bindings: timer: nuvoton,npcm7xx-timer: Allow specifying all clocks Date: Fri, 22 Apr 2022 20:30:06 +0200 Message-Id: <20220422183012.444674-2-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220422183012.444674-1-j.neuschaefer@gmx.net> References: <20220422183012.444674-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:lnBh/Tpvgmu7+wHhf+H5KmdyA2JGqflwIdExxJyori80ywRZSGg flOvQpXx/6FTotPushCAlRjkrTtc6+4Al0ktSv+PUZ0hpSYy2O5QKr8ZpiSt5c26UcjQFfW MAWFL4Hz8F9vQWjXrGC1jMgB2bGBiqgY4p203hrVJHH/jNtRhzgk4N0vl6J4PqBB2kLE79S VYINyKnXBIFnjHKOVSF+g== X-UI-Out-Filterresults: notjunk:1;V03:K0:GH6IMDgDjVk=:zwNWdBjXT58bbmqMOK1ZyH eKVkZYuRPsrGXFJR11x2HGexmFcrG5npjb3hw1G81xS9+G68DLMvyuSJV4bJk3zuLcYVJqa1M JWCQfcfDk5UKkQ1rlenE34gpA7hztwRAbHJ3iV6js3KyzuDVsz7Xo8zK/L+L4Yi0F085xgL+o PCIGn+niJIKUgnUVAwQKaQOF7iMw9eTwkXwpmnLbOjTqD5eJ5aG1UDFcRwINNWUvcvI5O4cda FQUNnGTdL7ujQZfXVbbM0ZBbIDcDFeIdagpMtfYnq0h+zFg8PJZCOlhXMwVdT6ULcVnprY1UJ n9mFbqmetOirWzDWemHEOkTuSHZQn2h6rEShW8mtcEW/nVfKJPcy4FF5BtIidgV33NM6mm8A+ HWaHmQUaszJdqIepItfxN51b9DovnEQJd8AU8r4F2m9W8TQYAMToGJq0RoC/wG+Qi+iq0q/8E 7L+7jniWOs5WQJj1+KSh+kuXBI8o60eik0JBj2P/bYnPGx6z7TzbU3u5mD1m0eknZ7YbQKvRX s6Qq7qwu3VdY3zwYawvsipVz9/hbIhNvnDjTHZIKK9021lvFY89Y3dXQ25/yJzSUyP/h6vqAC mLWNBcsefhfoCOf9EMY7Y1iHQRXaNOLMcDomv1Gyb2d+IzEBcAXNewrk7kZA4RPMlnF+ydcF0 uH9kNHGGrDq+QvsnKHjBZWQxvezef3FAaaap6IRxvIKEeoDaNWDkMUCY/5bQPd5gF45Q9Nxtq bTPPVTzxFfMC5IkLZt3dGT+Vk5g6/FZ6r2Md5bslCrwrI9K6x5mQVeWdZVfnfEaGf/iLPNVuq FHTow+h+Ja7faVEPIx8RBs0/dP7YTJttdutvqRV1pNbPZp2FRYYC8g4Yv11aWbFNKS8X82J/F AbdPHOZSjmZ2I6JKMpkNbmZ8BIU3SisXUpxy2UqgVlrc3oVBR+87o8v+DQAX2Fv2QenHhXDu3 QdDCeqGp3hOCaon8nS6Fx4843UHajRwjuzgvPIqr5Atg1Hgt07zD4FqllQMD+y/9T0Rmf/6Y0 k5EC7jZo/XUQXoyyEyQ+Mpit8AG9G6ArfHdlYaDKkfSa5ZtaKLXdUEMTQY/i3vNI1kTulkD9T DSKFokWsM0Uosw= X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The timer module contains multiple timers. In the WPCM450 SoC, each timer runs off a clock can be gated individually. To model this correctly, the timer node in the devicetree needs to take multiple clock inputs. Signed-off-by: Jonathan Neuschäfer --- .../devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) -- 2.35.1 diff --git a/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml b/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml index 0cbc26a721514..023c999113c38 100644 --- a/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml +++ b/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml @@ -23,7 +23,13 @@ properties: - description: The timer interrupt of timer 0 clocks: - maxItems: 1 + items: + - description: The reference clock for timer 0 + - description: The reference clock for timer 1 + - description: The reference clock for timer 2 + - description: The reference clock for timer 3 + - description: The reference clock for timer 4 + minItems: 1 required: - compatible From patchwork Fri Apr 22 18:30:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 1621226 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.a=rsa-sha256 header.s=badeba3b8450 header.b=HwCRogHH; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4KlT2b5Jtbz9s09 for ; Sat, 23 Apr 2022 08:04:07 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231733AbiDVWG4 (ORCPT ); Fri, 22 Apr 2022 18:06:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36156 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231448AbiDVWGt (ORCPT ); Fri, 22 Apr 2022 18:06:49 -0400 Received: from mout.gmx.net (mout.gmx.net [212.227.17.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 45848208225; Fri, 22 Apr 2022 13:51:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1650660663; bh=Cymelfm0dfRc/xEvMKwoybWU1kDdiYfz3b2fHT5KUdI=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=HwCRogHH7SWrMLArbABWdkNz9fT6p7rcGoBcLx+u0005kKgylL4dxLQGgWTo1Iacv dRBl4e6l4+Wf4aFTLFHnE0rBn2/WY6x4yukN5yrbSoGO6sI05HEbW7VuiVmC1TBKIX E4htHAAfiFIpafJYnSc4LXiIirwpyR4fE0cwIzNc= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([87.78.190.74]) by mail.gmx.net (mrgmx105 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MaJ3t-1nNDlX1HTp-00WIyP; Fri, 22 Apr 2022 20:31:54 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Daniel Lezcano , Thomas Gleixner , Philipp Zabel , Wim Van Sebroeck , Guenter Roeck Subject: [PATCH 4/7] dt-bindings: clock: Add Nuvoton WPCM450 clock/reset controller Date: Fri, 22 Apr 2022 20:30:09 +0200 Message-Id: <20220422183012.444674-5-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220422183012.444674-1-j.neuschaefer@gmx.net> References: <20220422183012.444674-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:vVjrm1cK8AXlnpuGK08RSnmA6OQJ45C2q8UnLt+ebe9CliGV0GN Ti2LnJqA3CI0GUJriFLVzIgrC/GGhXhNMKKv5axP3W5W5BC44FV5INXkhXh9NVzreAFDXxf hYXaumjri/r402YVm6eqffixmakJCzbvAgc+taVHDAyxrjDdf0CQZBv5XXpMOXqvZrkmJI7 35zbHFwBeKYBTxHW9dkrg== X-UI-Out-Filterresults: notjunk:1;V03:K0:AQbNhO89mNA=:MLaOVMQJPve9D6gl13SY/6 x8dcmv0TrOwv0Dt9s/OHQeDH+TS4WpahFEojBRnVKjA0QTtUw9/5BS1Q+9M8eB+kl2Sjpwr91 WfjgcDxVlCnoqeH8gdoSLC5spPNpj0y+6rlPXXRgd6aXGPCkWA2bxhs3H9UrGBEKJ3BZ02k6f t0fIT6LypHwcmRM/wU/N3mTMXDAGQ/KKmp8ndmWYnn2a4khJTds02H4xTy/3ELG6FVo2OaAI2 DPMoqgGiRuURMcpM3zAAmbG6LslC0SZSikMZQeLBWxvdLG5cMWBKl9X82oaaeKvgJJd2/3qjs HeegIG4YCVpyVZ0B1SAAYWSE1OHspveo+GFscRINf5Mm5Y1w+INy6Sr8r8syauCif31k2ekI9 8YUn1zACpgCsrfLfiIn6xVI+rXKtuxEyZdgUufWw+mSIO74TBzcap3W2hH5CVEU4D5duvcQOW fI2mqGEvWAzfAvy+Mdf/Yyl+8NvQ6jLI51cYWGVSHwdkARttm2IOR7QZg1CQRYXQSmVEFPdDh wDsCYwMQCrYW77UTgwE/acBO0rqBSJpf4NuY0QOKb1sjV5v+V3uM2k5Votzjcy8n2U5WMtHNf H/kJhGOCDr0y8Ab8k9HfW6dIWxBhUYqcfudxkAQUlrzPCdzT6oPXrK7YeXhTKON67TbUoKg3f u35H//9VxDbAzjxbESXvZzSWdDtp3o2excOpCWvEqFfXR8OHIudXDSgTTp5ViIevS0qbf8r1Z Q638FC4SAjmNt+Ulv8gWs/xPCmsiFpWKrOWtx8bXgWbWlM3LiBRza3kSAXy5jA/nPElUIe43G RTC3mgFDpwfOF2inXuLNEIhFw1FEe1+9nq3LycJFFrutTjSOiuOlpc1KWCl0QixV11MgkdZKs wJEOHUHFPnU1VhOkKE1bJH2g9fPfyV/xa+2zW2U1UAnHfOwPeQf9CsPeKHcrO+lNtXB58mGyc NqZ2XX7y72Twtb0TtY0P8/71imq+/JAUlwhzh4a2EWxlNEEx7jPLKL/cXtGAATPBI8gjVzszw xCbS8HIhZVYaGHjKRI0/g0XvN1iD2AaO8pOj1iOu8SQjOQNC0TdEJzR9IFHZRZwAtu/zH5K4m SCxdsoE7MH07PM= X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Nuvoton WPCM450 SoC has a combined clock and reset controller. Add a devicetree binding for it, as well as definitions for the bit numbers used by it. Signed-off-by: Jonathan Neuschäfer --- .../bindings/clock/nuvoton,wpcm450-clk.yaml | 74 +++++++++++++++++++ .../dt-bindings/clock/nuvoton,wpcm450-clk.h | 67 +++++++++++++++++ 2 files changed, 141 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml create mode 100644 include/dt-bindings/clock/nuvoton,wpcm450-clk.h -- 2.35.1 diff --git a/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml b/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml new file mode 100644 index 0000000000000..0fffa8a68dee4 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/nuvoton,wpcm450-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton WPCM450 clock controller binding + +maintainers: + - Jonathan Neuschäfer + +description: + This binding describes the clock controller of the Nuvoton WPCM450 SoC, which + supplies clocks and resets to the rest of the chip. + +properties: + compatible: + const: nuvoton,wpcm450-clk + + reg: + maxItems: 1 + + clocks: + items: + - description: Reference clock oscillator (should be 48 MHz) + + clock-names: + items: + - const: refclk + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +examples: + - | + #include + #include + + refclk: clock-48mhz { + /* 48 MHz reference oscillator */ + compatible = "fixed-clock"; + clock-output-names = "refclk"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + + clk: clock-controller@b0000200 { + reg = <0xb0000200 0x100>; + compatible = "nuvoton,wpcm450-clk"; + clocks = <&refclk>; + clock-names = "refclk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + serial@b8000000 { + compatible = "nuvoton,wpcm450-uart"; + reg = <0xb8000000 0x20>; + reg-shift = <2>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk WPCM450_CLK_UART0>; + }; diff --git a/include/dt-bindings/clock/nuvoton,wpcm450-clk.h b/include/dt-bindings/clock/nuvoton,wpcm450-clk.h new file mode 100644 index 0000000000000..86e1c895921b7 --- /dev/null +++ b/include/dt-bindings/clock/nuvoton,wpcm450-clk.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H +#define _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H + +/* Clocks based on CLKEN bits */ +#define WPCM450_CLK_FIU 0 +#define WPCM450_CLK_XBUS 1 +#define WPCM450_CLK_KCS 2 +#define WPCM450_CLK_SHM 4 +#define WPCM450_CLK_USB1 5 +#define WPCM450_CLK_EMC0 6 +#define WPCM450_CLK_EMC1 7 +#define WPCM450_CLK_USB0 8 +#define WPCM450_CLK_PECI 9 +#define WPCM450_CLK_AES 10 +#define WPCM450_CLK_UART0 11 +#define WPCM450_CLK_UART1 12 +#define WPCM450_CLK_SMB2 13 +#define WPCM450_CLK_SMB3 14 +#define WPCM450_CLK_SMB4 15 +#define WPCM450_CLK_SMB5 16 +#define WPCM450_CLK_HUART 17 +#define WPCM450_CLK_PWM 18 +#define WPCM450_CLK_TIMER0 19 +#define WPCM450_CLK_TIMER1 20 +#define WPCM450_CLK_TIMER2 21 +#define WPCM450_CLK_TIMER3 22 +#define WPCM450_CLK_TIMER4 23 +#define WPCM450_CLK_MFT0 24 +#define WPCM450_CLK_MFT1 25 +#define WPCM450_CLK_WDT 26 +#define WPCM450_CLK_ADC 27 +#define WPCM450_CLK_SDIO 28 +#define WPCM450_CLK_SSPI 29 +#define WPCM450_CLK_SMB0 30 +#define WPCM450_CLK_SMB1 31 + +/* Other clocks */ +#define WPCM450_CLK_USBPHY 32 + +#define WPCM450_NUM_CLKS 33 + +/* Resets based on IPSRST bits */ +#define WPCM450_RESET_FIU 0 +#define WPCM450_RESET_EMC0 6 +#define WPCM450_RESET_EMC1 7 +#define WPCM450_RESET_USB0 8 +#define WPCM450_RESET_USB1 9 +#define WPCM450_RESET_AES_PECI 10 +#define WPCM450_RESET_UART 11 +#define WPCM450_RESET_MC 12 +#define WPCM450_RESET_SMB2 13 +#define WPCM450_RESET_SMB3 14 +#define WPCM450_RESET_SMB4 15 +#define WPCM450_RESET_SMB5 16 +#define WPCM450_RESET_PWM 18 +#define WPCM450_RESET_TIMER 19 +#define WPCM450_RESET_ADC 27 +#define WPCM450_RESET_SDIO 28 +#define WPCM450_RESET_SSPI 29 +#define WPCM450_RESET_SMB0 30 +#define WPCM450_RESET_SMB1 31 + +#define WPCM450_NUM_RESETS 32 + +#endif /* _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H */