From patchwork Fri Apr 22 18:30:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 1621097 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.a=rsa-sha256 header.s=badeba3b8450 header.b=XcrOKbKj; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2404:9400:2:0:216:3eff:fee1:b9f1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4KlNLp1qFnz9s0r for ; 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Sat, 23 Apr 2022 04:32:30 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1650652307; bh=nH5nbmzHe/xRwz0pWDdjzn30b813GPDvATKACfo4I6g=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=XcrOKbKj5+k5k5MRW3lnNx3b2BzH1muMhUPLRVbJ3jIMoPSPgc2ydeSkFlAb2Fr8L zce8KB4yozHjdmE5SKTbziLmYiyG0YjClyndUaO3Zf20ugQ9QDlAt4/KbtS5KUxZ6Y 1VGkDJIhm7QY6/sDlCOHs9JpkW/PtYC98dYI+R+o= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([87.78.190.74]) by mail.gmx.net (mrgmx104 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MGQnF-1nh6473Djx-00GnuC; Fri, 22 Apr 2022 20:31:46 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Subject: [PATCH 1/7] dt-bindings: timer: nuvoton, npcm7xx-timer: Allow specifying all clocks Date: Fri, 22 Apr 2022 20:30:06 +0200 Message-Id: <20220422183012.444674-2-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220422183012.444674-1-j.neuschaefer@gmx.net> References: <20220422183012.444674-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:lnBh/Tpvgmu7+wHhf+H5KmdyA2JGqflwIdExxJyori80ywRZSGg flOvQpXx/6FTotPushCAlRjkrTtc6+4Al0ktSv+PUZ0hpSYy2O5QKr8ZpiSt5c26UcjQFfW MAWFL4Hz8F9vQWjXrGC1jMgB2bGBiqgY4p203hrVJHH/jNtRhzgk4N0vl6J4PqBB2kLE79S VYINyKnXBIFnjHKOVSF+g== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1;V03:K0:cTH8WXWnjoQ=:lyV5jFTtKdRZz3DTJCjI5K mMu7S2YOs5tSjCYabifnHXAu6aLwokhANbJBAXa850vOgiyWU7hoQjs1uYSwaVB3opmvKlijU 9sCH4DrNAvCwuPr5qXzGlwMmbMkgcwER0V4LnWbLX8pSrfzCf7eumPMOLGkOL50gn+aqREL1y iuyrMGetPG6BhSTgLdYSK5rkYdoDSrkHhrDZ1fhnRjGEfiEPvJt6bMPIULYXVDxRuDEBku7LI dD91EvU2c07T6C2xaERVV1JYaeaAy6WAwmTwXuXuBO0T1YcEIvo46N5GUnQ4ulHvvzFFokFZU AoddDQhNJ5a9RM21vR12Fg8LaE8UfSMly6JWVoYIQ6X81wvDqEWergSxPGL0bF/ArVf2D08S4 jbaSkZPYPM6pBdkUA/oqcB//2KPWtDuuprFFTdGSmeP3G7PWIfeUxcIC58rbjPKj649758P/Y eFk3Ki5KPk0jLwSqGZqx+A6pFh92myD4e9bxPIYvxfpwM2zHdvslnkddGtepywQCTVDts9l12 rWkY/1a+4TFvEvxuAvINqegQ/NmR5FyDjgQE5QXrPK8FOS1RZDxzgAbuP/XM3jpO1bjAPxYVo 2H9gKY/z7anwlvz9ZUHvfC7dTDwEe32zCezbFVioI1+hwZwr0OuTOJjIkRosoy+K3kyD3BlTF am4dFA999wmVKr/p8RyKDm6IeIsxN8Fw3OqFz3KVFeEbJaoqczlw2BubXLb+EZsMTqWlRjWWF AeKjWRncurTd/jruVjBIB2PlHsQ8HUzXt003PKInqjDXn2m5B1LEIXBy1bBqF41g3SdRxyLE1 mMO/pPcKnuiOiYTgJQazuOrVOzZT0AiiLniXGne826dzY/ntmGCpmV+Tk22L7Ver5H1FhIGlx ft00hCqlkyzAqExTQ87j9PDfmv4Pk0JCr3cficbv9NdU09tnuMjEFD2sA66yK6N5y84ULPHxv 0hwo6NQTurSuzuxXvIcYvmRoBv+z8peIZZpOgsi+mVTni/zD/kV5qMjzeq6SiEvSNk+qBji4w C0+PvGKvhnqu2oaDDKOkNf0fTeko0p98st5ZpNpHhafcClsEDeAhidX2CCKOUrJpM6Bk4OzCm gSJVOmEh6V8ZYg= X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Wim Van Sebroeck , linux-watchdog@vger.kernel.org, Stephen Boyd , Patrick Venture , Michael Turquette , Daniel Lezcano , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Avi Fishman , Rob Herring , Benjamin Fair , Philipp Zabel , Krzysztof Kozlowski , Tali Perry , Thomas Gleixner , Guenter Roeck , Tomer Maimon Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" The timer module contains multiple timers. In the WPCM450 SoC, each timer runs off a clock can be gated individually. To model this correctly, the timer node in the devicetree needs to take multiple clock inputs. Signed-off-by: Jonathan Neuschäfer --- .../devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) -- 2.35.1 diff --git a/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml b/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml index 0cbc26a721514..023c999113c38 100644 --- a/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml +++ b/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml @@ -23,7 +23,13 @@ properties: - description: The timer interrupt of timer 0 clocks: - maxItems: 1 + items: + - description: The reference clock for timer 0 + - description: The reference clock for timer 1 + - description: The reference clock for timer 2 + - description: The reference clock for timer 3 + - description: The reference clock for timer 4 + minItems: 1 required: - compatible From patchwork Fri Apr 22 18:30:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 1621107 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1650652308; bh=XAbU/WwnBQTi9/OidcyFLjRJfgJl6FaI1cL4Ta59NpE=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=D5c6BNuUtvegOGNSGvbeXaBV4pudnxeFpT9TW2nUtf+kLo3ykkOMzOYVOrPLHYw5g vFbQvoqirE9y4DP9GvWHiEEHmo6NJBRtYL9ApwQCufx6V4JkGsYzHPe8/MTpz+stcb gsl/C2AG5uzuCZCUDiZ63pyragftLNMtYn34PooM= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([87.78.190.74]) by mail.gmx.net (mrgmx004 [212.227.17.190]) with ESMTPSA (Nemesis) id 1MxlzI-1o6V013bxO-00zIaz; Fri, 22 Apr 2022 20:31:47 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Subject: [PATCH 2/7] clocksource: timer-npcm7xx: Enable timer 1 clock before use Date: Fri, 22 Apr 2022 20:30:07 +0200 Message-Id: <20220422183012.444674-3-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220422183012.444674-1-j.neuschaefer@gmx.net> References: <20220422183012.444674-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:uovlBSQszsD4TcZ6IjORpDv2zAitS8WCPXKi91TdybsXvyz7lqO rC2FC41F/kJUCpFHd1VviHlqQLLBrFbdETf+eE8nbVimOfnWkBZ30HFJmtlAYF1Jwirim+1 uMWQPfc4mPu19lplwt6TaEE58ze9BYNz5EI1+XTE1tlzCw3t9XOIahvNn5e/tYf/l/wShmM vpo+JqSHVFco1wj+MDB2Q== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1;V03:K0:kt2z91rRdcE=:58S2TF6gkz18jfO0KkiERs hYXl3pgxdM56NsrMXdy+48jlVZtKebIJPZdsLNGAekwywMoXJPAftncZrBRKPwsofFs6eAIMd 8GOYdTMZ3RkIp5CNqUN4NOkblPX0hEof4DjTkgWo1dDn8on2ccfwq9VhbDfjOdaIviEWFkbxc waN5xv6bUUTujuCp0ZGS5q3lNHnjCbcGIfOKYDK8714sGTGrpCHtbTaEs5jXeddX3EYR9HCYK +Nz+ifrkt42tybWTZV+CzNvF6wG+gZTV15QogVYYzl2YBtnIs9UgwqxgHFBiIPBiCECkYjnEs oyG4QzzZLT0GrzU8RNAcdiqAHvE4YXkxGNCQo3Uy+I3unhsx0shQArXrhk5mHw89L99pIAGFp 1PjM8VHO7dFzATycMu923lEV7ds7QlodUlhoYrU5ndAFYIxhVJwkawbnRidxi4ZsWMJ0IO3SK /8UiR5zMobx3EHo0WwEcxosaTU5T5UY0N3hkzFULUinjnLBGE/eHfWbwuZI8rqM4VOpr1tlft mcKHASvqp9gGShEcgxD8oKBE3hAndLnB4wFm5Txezwoz4Z6RShpFnoWX9aIiUUEjpsikF7QjG uRBltJhWu9e/ByVgg8H7pPbOIsSb1KSkzlOqS+3co32rPUCHbl6S763F6KcRFw7ELgNX/Hld9 QgRRdGDrUSomfqkarX0gmbK/uhRONRzudIjTbMwIVb1ZoMyJqdy2GGg3kyofTM508PcEGP2pl x6ysQkBIsv/8JiEyxIs8nN0RGbNGjHXq5FjzHnDyE4XkY94S3Hh3clsKiLTxfBXDytOl76T7S C5UjU33sQGLByCz9tZvUiiaOHWDG0GCf+ZFyrEtGHu+gCyc0oYOrTIzvVIwYZCulwTJzPcc7A pMWAplCYze02hP03JHNCOK0QC23mlY6d6b2C/tgzW2JtdGr1+JZt4JMKwggRzIMbY4PoDy7iO OQHKOj+TUM96fn9n1j8hyOCDpeIuqo9UefhSbZQ815dJQcZIvibHeU1WW+BJDt1yDrQaTyyQS kYwtSxbHhoc/JOIBQ63O1VcTsFfbfIneg2aPbHE2Cu2DTaI4GGGxqrhrEg8XyxGpaJ+UnNP27 JiwFSajrHCgMsg= X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Wim Van Sebroeck , linux-watchdog@vger.kernel.org, Stephen Boyd , Patrick Venture , Michael Turquette , Daniel Lezcano , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Avi Fishman , Rob Herring , Benjamin Fair , Philipp Zabel , Krzysztof Kozlowski , Tali Perry , Thomas Gleixner , Guenter Roeck , Tomer Maimon Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" In the WPCM450 SoC, the clocks for each timer can be gated individually. To prevent the timer 1 clock from being gated, enable it explicitly. Signed-off-by: Jonathan Neuschäfer --- drivers/clocksource/timer-npcm7xx.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) -- 2.35.1 diff --git a/drivers/clocksource/timer-npcm7xx.c b/drivers/clocksource/timer-npcm7xx.c index a00520cbb660a..974269b6b0c36 100644 --- a/drivers/clocksource/timer-npcm7xx.c +++ b/drivers/clocksource/timer-npcm7xx.c @@ -188,17 +188,29 @@ static void __init npcm7xx_clocksource_init(void) static int __init npcm7xx_timer_init(struct device_node *np) { + struct clk *clk; int ret; ret = timer_of_init(np, &npcm7xx_to); - if (ret) + if (ret) { + pr_warn("timer_of_init failed: %d\n", ret); return ret; + } /* Clock input is divided by PRESCALE + 1 before it is fed */ /* to the counter */ npcm7xx_to.of_clk.rate = npcm7xx_to.of_clk.rate / (NPCM7XX_Tx_MIN_PRESCALE + 1); + /* Enable the clock for timer1, if it exists */ + clk = of_clk_get(np, 1); + if (clk) { + if (!IS_ERR(clk)) + clk_prepare_enable(clk); + else + pr_warn("Failed to get clock for timer1: %pe", clk); + } + npcm7xx_clocksource_init(); npcm7xx_clockevents_init(); From patchwork Fri Apr 22 18:30:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 1621098 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.a=rsa-sha256 header.s=badeba3b8450 header.b=McZMXG4R; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4KlNMV0d4bz9s0r for ; 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Sat, 23 Apr 2022 04:32:31 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1650652310; bh=8RE6J/48SaezMLYOSRQdb+dos/63a0S80cGWNaaY89M=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=McZMXG4R3dWFUQumN0DawVnIhuFfInIU4+KAy6T4wMDKADtRF2feoamdWEVgEA9mm KVEFezUzWXB3zfjm7+7ENohEgD3Ueb0qxcdw5x6IXYN/Gc6Y1gfOpTVKLsOm98g+SF 2LCIifg50JAi1AkvsYryxYXvb0lzyi1ewlGH8/Ro= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([87.78.190.74]) by mail.gmx.net (mrgmx105 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MaJ3t-1nNDlI3YKj-00WIp0; Fri, 22 Apr 2022 20:31:49 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Subject: [PATCH 3/7] watchdog: npcm: Enable clock if provided Date: Fri, 22 Apr 2022 20:30:08 +0200 Message-Id: <20220422183012.444674-4-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220422183012.444674-1-j.neuschaefer@gmx.net> References: <20220422183012.444674-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:DzdlIpOpxoHVmzoWSwK/nL5QieYQdzPf0cfyielup2/bHsKDAwQ N2kbPBEm068bJ2qlsUpy1PuMDBxL0Al4q+6mC29jVCwWJ/ZDGDodyr0gOx42IbCkPI7CSfx IoV+Hxjssgj5OQwTO2pN9A2e91iagZFyoIx2I3C0VnPPyceNuz2gFz1TMWf3aXtkNj8+Rde HcSt22thU4XWdRXPBq43A== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1;V03:K0:Q6muYwwBmOU=:XBhc30hzd6wXZguPW3xRtz DdwsVQEK+pMfcJV1KuXz0Npbh+HhJQLX0+wE3ri9G7EcUC5WJabgwj4V2SD4EG2UpjpiN42Uh T+r46GZk/HV1bG8IuSGaKzivCcLgt2PnzhI9YIDPZJHtIQM5aRVAjs/OL1qh/b8DIq4SpFbhl hgqyy8MVvt2qJqiN4mgUPa3wPDthiqN5znkOYf2n464i/RXsJwS4EEsp/AGAtzj203GYJOIjO lgMz7Sa+Duk3nVijDKYztt0Iq1M25PAA4SIQ1xdapXzKNlLNNn5IKzrmJDdoQeRB7uZ4v6FD1 0fd3z29P2Cdw8ROipnR5+rMLAEcc2T4UcOFzmmOL191tGuIfX8x8s6hJ1c3YJJwY3f3Shla71 rztw7Z3PsZSiUh97FyjliYtbgos3c81W+aE94RZ9olujmqRaGT0k0IiHMYGX5pEKRuRVXjvn9 MvQYxfk+AA4Nx0jdMZiwJA12RUkPBpmM6QuOCMF+s/Tix/FP/iUtNqFBmmi1J9e894firyGlF Knz1ZgnOxnHBUReHAJrOgyLdTtCCJ2Y0lpULtYOY5grwuOgcehlLwravbwWxc1pKKjXRM8FwJ EKHYCcnUDwuFt0XM+jWkCYXYjgLqiaTFIj3dT+YiV8wAPzZp7QyJm9zkbpbfxqgisJSvZ0vK0 dIdyTA/6hsg66pUbiMSHRn4DkCT7GKfys+uriHvPSKvkPrOnVdg1Oq3BUNsvYmywcOEkAJEU7 MkWZ9hCZaAa2jI/Abpw5ZxhNm/IGG0Wf2S/vFz229V4xz+TbELanPk9YiUW9pvBvKWNbQeYuD k2NGQGzrVbTSLk4BnyC7n0KzZY8t9yCHeqmAho7S0BgaRuJIaMc8wc0qxo1XuTsEP65NiDMq7 t4G/aJyN8NIW1SnhryNHziwGN2V5+LEG1jU+1Kfr9Cqayd5nVjTmNr6l/J/wZbHlv0GeyxpbP OHIJ/NXBW7HWOne3TpERB58jIxvqL6PxdC7Mx/y6wD7a09apUebc7cEVWkcKW3zEdZWvLgF7B Os1/OWt0TztONeUSqkVtFt+Rr6NuJQ8VLASaJC40j+QBrjCajzDjE0zoqvj4vQ1Qu8IA6x3AF 7hX0ZgcbdvFMSQ= X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Wim Van Sebroeck , linux-watchdog@vger.kernel.org, Stephen Boyd , Patrick Venture , Michael Turquette , Daniel Lezcano , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Avi Fishman , Rob Herring , Benjamin Fair , Philipp Zabel , Krzysztof Kozlowski , Tali Perry , Thomas Gleixner , Guenter Roeck , Tomer Maimon Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" On the Nuvoton WPCM450 SoC, with its upcoming clock driver, peripheral clocks are individually gated and ungated. Therefore, the watchdog driver must be able to ungate the watchdog clock. Signed-off-by: Jonathan Neuschäfer --- drivers/watchdog/npcm_wdt.c | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.35.1 diff --git a/drivers/watchdog/npcm_wdt.c b/drivers/watchdog/npcm_wdt.c index 28a24caa2627c..6d27f0e16188e 100644 --- a/drivers/watchdog/npcm_wdt.c +++ b/drivers/watchdog/npcm_wdt.c @@ -3,6 +3,7 @@ // Copyright (c) 2018 IBM Corp. #include +#include #include #include #include @@ -180,6 +181,7 @@ static int npcm_wdt_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct npcm_wdt *wdt; + struct clk *clk; int irq; int ret; @@ -191,6 +193,13 @@ static int npcm_wdt_probe(struct platform_device *pdev) if (IS_ERR(wdt->reg)) return PTR_ERR(wdt->reg); + clk = devm_clk_get_optional(&pdev->dev, NULL); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + if (clk) + clk_prepare_enable(clk); + irq = platform_get_irq(pdev, 0); if (irq < 0) return irq; From patchwork Fri Apr 22 18:30:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 1621109 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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t=1650652314; bh=Cymelfm0dfRc/xEvMKwoybWU1kDdiYfz3b2fHT5KUdI=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=cPN+9d+KbcFfP/Rabi8abyM/lXhmut/YEfqQF/KKYe2vO9BaszkCjkmVRutdyGQ7Z tKFdYd9s7CKqIZ9bjA5VZvWMt/wULcqeL4QYd+usExVGqBP9UsYKnWQAglXfZNPMdR ZMm9jBtQuqFZwAlSn+yltkhrv6gXwPsuLW7r7YlE= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([87.78.190.74]) by mail.gmx.net (mrgmx105 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MaJ3t-1nNDlX1HTp-00WIyP; Fri, 22 Apr 2022 20:31:54 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Subject: [PATCH 4/7] dt-bindings: clock: Add Nuvoton WPCM450 clock/reset controller Date: Fri, 22 Apr 2022 20:30:09 +0200 Message-Id: <20220422183012.444674-5-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220422183012.444674-1-j.neuschaefer@gmx.net> References: <20220422183012.444674-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:vVjrm1cK8AXlnpuGK08RSnmA6OQJ45C2q8UnLt+ebe9CliGV0GN Ti2LnJqA3CI0GUJriFLVzIgrC/GGhXhNMKKv5axP3W5W5BC44FV5INXkhXh9NVzreAFDXxf hYXaumjri/r402YVm6eqffixmakJCzbvAgc+taVHDAyxrjDdf0CQZBv5XXpMOXqvZrkmJI7 35zbHFwBeKYBTxHW9dkrg== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1;V03:K0:tmZlAaWyGqM=:tw+2mnx7bshlkK7ct+VSf1 JvEH74Z+si9qk/83YOPxFfZijnszwjKiBP8GsoEO25kCZLpJS3Qa6+xUsvJuCRhBJtyFdSeFJ bYmYkWwXQjAy7GY1ZaUorzwzIjwS672Y3GtrzGEcxTN2y4YBhK0bHEn7obU1bcHu6/iMgKuqo Nl3hut7pxJ0XJM4DzBTQgGYi3d+NMS+YaZ9yp5iMlDxPolb1RESlEACZlxEmGJ0O7CRcNc0Uj 2nMJ7/U5ZtiiZy/I76qc9RWNo17wecpGpeIfFlFE2rro0bkNV0932htBmY9lut170+xVGq0LN 5cA/PiSOhn6OI+yIDVDaRPnaixe4w6GjZOpF7SfTTDqjQEMBf8tF28/N7dvMR5y4/tfp8KdSk 1KVfG3Ffg+ZnvBzYfpcw6Ik0IEQgUb71H68tJkGhpHV1gH+WC+6Rn5wkUE8kVh8gz+SQs7v9Z GuR1MCAaBd90q0l5lhoj49tP7sTOExHzYQCAUD7bfsg0I59pnS444+2nRikNR9Tea1CO4/1xb KxAzQxPkpf9QtRl8aObOdBDYD+tWrhIbMG0PWgouzSGV7K9vLnIpn0ckNlvoRDPCqfj95Okqc RWPA4odSF8/R+jm9ZN0OifrnDR/hZ5CBwappKUKKIhgp9kXIzoKYntRVVS1Vsjh19Yd7AbLZ4 ReQj+aIm+OlLTUnkISApdZpvGHRbsULY28lRtJD+LvzhjHT+E9EYvD7NLItHgcXaNV0/N5gT2 qzWi6312mFz9z2wAm8Azc9M5limwNIVUCWvjMyxodX4RfAjD1TnkUoL8hRH5JInQulC521EDA xcKOKr5Xsx+ezybIMEn/YsQPEf8NhLx6jI3TPMTU8uyx3FhQGCsRRIn/j7Vk3NL7aIKg9VWz9 VBWHvXPi4glo+99R4aTZeb3mYZv/TjCcxVhLdSBvLMiyUW8NSFbCAGeqvDemVv6i3whCmF2wp gsqRiE0bPs6Q0IRiyk/8IP4Dzd6cwbWjqB2cz1BsxgwvzXste4l6Kl2GgcAJp+hdA2b17GJ4j MYamUFzjKRvJobgiOzdh9cN0Ep+9xgdWMirxaBl826IOscvBFmOd3bcvDC2USxEoxOwhCkKut 87llxlHnOJRtNA= X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Wim Van Sebroeck , linux-watchdog@vger.kernel.org, Stephen Boyd , Patrick Venture , Michael Turquette , Daniel Lezcano , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Avi Fishman , Rob Herring , Benjamin Fair , Philipp Zabel , Krzysztof Kozlowski , Tali Perry , Thomas Gleixner , Guenter Roeck , Tomer Maimon Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" The Nuvoton WPCM450 SoC has a combined clock and reset controller. Add a devicetree binding for it, as well as definitions for the bit numbers used by it. Signed-off-by: Jonathan Neuschäfer --- .../bindings/clock/nuvoton,wpcm450-clk.yaml | 74 +++++++++++++++++++ .../dt-bindings/clock/nuvoton,wpcm450-clk.h | 67 +++++++++++++++++ 2 files changed, 141 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml create mode 100644 include/dt-bindings/clock/nuvoton,wpcm450-clk.h -- 2.35.1 diff --git a/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml b/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml new file mode 100644 index 0000000000000..0fffa8a68dee4 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/nuvoton,wpcm450-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton WPCM450 clock controller binding + +maintainers: + - Jonathan Neuschäfer + +description: + This binding describes the clock controller of the Nuvoton WPCM450 SoC, which + supplies clocks and resets to the rest of the chip. + +properties: + compatible: + const: nuvoton,wpcm450-clk + + reg: + maxItems: 1 + + clocks: + items: + - description: Reference clock oscillator (should be 48 MHz) + + clock-names: + items: + - const: refclk + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +examples: + - | + #include + #include + + refclk: clock-48mhz { + /* 48 MHz reference oscillator */ + compatible = "fixed-clock"; + clock-output-names = "refclk"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + + clk: clock-controller@b0000200 { + reg = <0xb0000200 0x100>; + compatible = "nuvoton,wpcm450-clk"; + clocks = <&refclk>; + clock-names = "refclk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + serial@b8000000 { + compatible = "nuvoton,wpcm450-uart"; + reg = <0xb8000000 0x20>; + reg-shift = <2>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk WPCM450_CLK_UART0>; + }; diff --git a/include/dt-bindings/clock/nuvoton,wpcm450-clk.h b/include/dt-bindings/clock/nuvoton,wpcm450-clk.h new file mode 100644 index 0000000000000..86e1c895921b7 --- /dev/null +++ b/include/dt-bindings/clock/nuvoton,wpcm450-clk.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H +#define _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H + +/* Clocks based on CLKEN bits */ +#define WPCM450_CLK_FIU 0 +#define WPCM450_CLK_XBUS 1 +#define WPCM450_CLK_KCS 2 +#define WPCM450_CLK_SHM 4 +#define WPCM450_CLK_USB1 5 +#define WPCM450_CLK_EMC0 6 +#define WPCM450_CLK_EMC1 7 +#define WPCM450_CLK_USB0 8 +#define WPCM450_CLK_PECI 9 +#define WPCM450_CLK_AES 10 +#define WPCM450_CLK_UART0 11 +#define WPCM450_CLK_UART1 12 +#define WPCM450_CLK_SMB2 13 +#define WPCM450_CLK_SMB3 14 +#define WPCM450_CLK_SMB4 15 +#define WPCM450_CLK_SMB5 16 +#define WPCM450_CLK_HUART 17 +#define WPCM450_CLK_PWM 18 +#define WPCM450_CLK_TIMER0 19 +#define WPCM450_CLK_TIMER1 20 +#define WPCM450_CLK_TIMER2 21 +#define WPCM450_CLK_TIMER3 22 +#define WPCM450_CLK_TIMER4 23 +#define WPCM450_CLK_MFT0 24 +#define WPCM450_CLK_MFT1 25 +#define WPCM450_CLK_WDT 26 +#define WPCM450_CLK_ADC 27 +#define WPCM450_CLK_SDIO 28 +#define WPCM450_CLK_SSPI 29 +#define WPCM450_CLK_SMB0 30 +#define WPCM450_CLK_SMB1 31 + +/* Other clocks */ +#define WPCM450_CLK_USBPHY 32 + +#define WPCM450_NUM_CLKS 33 + +/* Resets based on IPSRST bits */ +#define WPCM450_RESET_FIU 0 +#define WPCM450_RESET_EMC0 6 +#define WPCM450_RESET_EMC1 7 +#define WPCM450_RESET_USB0 8 +#define WPCM450_RESET_USB1 9 +#define WPCM450_RESET_AES_PECI 10 +#define WPCM450_RESET_UART 11 +#define WPCM450_RESET_MC 12 +#define WPCM450_RESET_SMB2 13 +#define WPCM450_RESET_SMB3 14 +#define WPCM450_RESET_SMB4 15 +#define WPCM450_RESET_SMB5 16 +#define WPCM450_RESET_PWM 18 +#define WPCM450_RESET_TIMER 19 +#define WPCM450_RESET_ADC 27 +#define WPCM450_RESET_SDIO 28 +#define WPCM450_RESET_SSPI 29 +#define WPCM450_RESET_SMB0 30 +#define WPCM450_RESET_SMB1 31 + +#define WPCM450_NUM_RESETS 32 + +#endif /* _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H */ From patchwork Fri Apr 22 18:30:10 2022 Content-Type: text/plain; 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Sat, 23 Apr 2022 04:32:36 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1650652315; bh=BHUkq4qIz1dh922+/iqR/+zEXRIaC4ZyZF4Bphn8Po8=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=WOQoej4LQV7pehkbxx/LFN6/QZW/wbVPlGFB9uakv59EcbIREz9Pdtnh9SwBQ3kBG 7IQL3Ya49XduW41FHp2LIVZXWuKEwSQ15EvGe1iNR7do5U13pmX/meO269rxU/SiW+ l1o2sQfa6w/FMwl7UY+wn5ZaakT6kxkaYqEZaYPs= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([87.78.190.74]) by mail.gmx.net (mrgmx105 [212.227.17.168]) with ESMTPSA (Nemesis) id 1N8ofO-1nvSO519eg-015ujL; Fri, 22 Apr 2022 20:31:55 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Subject: [PATCH 5/7] ARM: dts: wpcm450: Add clock controller node Date: Fri, 22 Apr 2022 20:30:10 +0200 Message-Id: <20220422183012.444674-6-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220422183012.444674-1-j.neuschaefer@gmx.net> References: <20220422183012.444674-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:Fag6c+9a1Pz3T5xG3Pe4SmIRM1zshVKs/bhtGtFRhEqmEKmvImL mQiew5bwtAn5jmH7DaPyUusvR9/woaryKVpQFAXUKgw39r3F9k9/a1u2LQItUrXdsy7diry CBT1J59AfeqO/3Z6yii0UgOL51/2BFCdmCC74iM+zjFRl7g/SRd0Lu5Q5I0YJ4tANpkLGDo PYSdA+hdkEp96fsM9/7sw== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1;V03:K0:FHS5GREvf+U=:A+388ueI27epBq/o5/JPE1 77zKVdTw8p87RexnMBTk1Uta8jvrAyIT7wLjVsHmRe6+EGGdjSsda4ALwVRH84JjezrYkgLIV HkWd3g9adYqJ7Ksy5w89HPga7O8H1rNaLeW8w6Xy3WEzz5okX1CdnQxTHP8OD1TI8iCoMkoSe 9/oZsxvc70gvTYruGwo7H6eJr+QPOIWdu3MXvlbfYP6Z9xSdckBq4XDmVqUr9aXud/eyRHAis vRemOkw+MYRfX9FkApUrWrHCDbpaZxrWNgXYCTrXWQl6tCllVR3zuKUvcwrwgk4zP0WxUC48P IJgF7DZR5IIMp58CuPzHmJow1lgfheMtE3qIUOY7IkeeY6Ex0t5lIMxyZD4wg+y2pBuBe8OVR FZJqwusFctNjjX+T1UujjnDkDmCepIrKeMZ7kBCGz2sKU1nFhkP869q8EnuPBx9h4BL0cP/B+ KUbfL2Ekn8k3e9rsXxDkvv4eTAZN1y9ZjMdH0hhg5UKftuInK8vcXcgGR83g68unH4HA/Lehr bfghZMlzyJmpTLaZlPXUhmz94JqvV8pj/cOvMqy4ZmLK1MvRt9Yb4hPhcoi2uaVM+NAnMJzB5 ZOQm+wvDyejtdlxAZjEubz1gN1tK9KSpXqaLxyZJM92V/W8SXS30BR1M4W9RF5Jqcl4SrlGFw Utn4qSWdN9jqUug9RvxLpTA9qxftwf9ZnoBxtfYWXi5eP6KD5fuR3CJ1QFcnBnhpBTU0jpLBy RGCO5Xt7IKxusKfqVrEmoIjymzC1IGWGuEKCv47IGI7LteiDoiMbjczxH4YlgjZzGZjOrex8/ XDgWUo34XRp8YrsQL8dtNFxfUjIsSrX4clGvTLTFWrqwFusWLD89rqB3igLg9CjHrQtr4nc+T N8KZnKDMtRlGbswogDsiy4FX1XEKuLPUakVrutS4Mbl52Cc4w6+ISkv8rSN1OVirewFDD0McW jYMgzpTfN3uhJ8YJXn3wpwAAhqgWGlZIdY2xW89OonoTAX/Vb00lef5jot8D9Jzr2G8NuolJ6 6yqAWmHiBBeE0zI2R9lwO6ysdMk2J1CgQC1rFL7l3yr7Qt0I6xB11qaihAaWs29G7EJqYJhwk SJHZxMop8EWIQ8= X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Wim Van Sebroeck , linux-watchdog@vger.kernel.org, Stephen Boyd , Patrick Venture , Michael Turquette , Daniel Lezcano , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Avi Fishman , Rob Herring , Benjamin Fair , Philipp Zabel , Krzysztof Kozlowski , Tali Perry , Thomas Gleixner , Guenter Roeck , Tomer Maimon Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" This declares the clock controller and the necessary 48 Mhz reference clock in the WPCM450 device. Switching devices over to the clock controller is intentionally done in a separate patch to give time for the clock controller driver to land. Signed-off-by: Jonathan Neuschäfer --- arch/arm/boot/dts/nuvoton-wpcm450.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) -- 2.35.1 diff --git a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi index 1c63ab14c4383..62d70fda7b520 100644 --- a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi +++ b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi @@ -39,6 +39,14 @@ clk24m: clock-24mhz { #clock-cells = <0>; }; + refclk: clock-48mhz { + /* 48 MHz reference oscillator */ + compatible = "fixed-clock"; + clock-output-names = "refclk"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -51,6 +59,15 @@ gcr: syscon@b0000000 { reg = <0xb0000000 0x200>; }; + clk: clock-controller@b0000200 { + compatible = "nuvoton,wpcm450-clk"; + reg = <0xb0000200 0x100>; + clocks = <&refclk>; + clock-names = "refclk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + serial0: serial@b8000000 { compatible = "nuvoton,wpcm450-uart"; reg = <0xb8000000 0x20>; From patchwork Fri Apr 22 18:30:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 1621105 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.a=rsa-sha256 header.s=badeba3b8450 header.b=khe27MIN; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4KlNPX6fcwz9s0r for ; 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Sat, 23 Apr 2022 04:32:32 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1650652317; bh=Z7teJIYqUSq12c5uTIxh9gTwy/vvO4uUbKqt8v51mdE=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=khe27MINcbDk1wnnET1Rnk73Da/M8lzLqxbVOIZ+ntl85vyI30kfIS5I7tGjBdi8w TIiuC5L5MXj/Ykql33h4URosbfF0jGYM0p8cR3IPxAVFkZPGLxXsgG1xzuQi7G35R6 JJaZ5mNVnMEQw6bHFdueP8PFBxB+g6tvwpEMg2+0= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([87.78.190.74]) by mail.gmx.net (mrgmx105 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MBUm7-1ncANu1Qv1-00Cxwe; Fri, 22 Apr 2022 20:31:57 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Subject: [PATCH 6/7] clk: wpcm450: Add Nuvoton WPCM450 clock/reset controller driver Date: Fri, 22 Apr 2022 20:30:11 +0200 Message-Id: <20220422183012.444674-7-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220422183012.444674-1-j.neuschaefer@gmx.net> References: <20220422183012.444674-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:gaCx0O9WDw+rwOFW3kkbLxaWxszoxkpE9hactbEFpdSE8StJcBX NsHfbRfFTuk6t2QdKLJXiFocCpwubMjU/Hfmb/gVwljXLT+BVvvVan3Snsh4sB7B0ZOf5Z6 RmVpMVnQ/aPMoGqQqb4yhNelNZTqSt88FZjFUuGMFq3ghJmbYFBr55CPSoOdSB1xh3+z+5p q528vyuc6nBZ3/yyf3mQw== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1;V03:K0:q9k8dyXCCz8=:sfXuxAqTQQxY6B0sW7qFsf xw0CmXMEyj2+gcPx5SK1bOy/ZoZQ0JSpnYSY8x7CoH/J7S9G0zaDZ+ysoZh1MRvCIx+6Rt0sS EZtu6do68sA5Pim2R+bDPybT0b1c2l53GxELIlzjd3knZzcCPefwKxdEIYq8Xcqe/M8h47LMO UEIm1c0VKxhrdHFKyZ7ON6TYgbfZ4HD3IoGn1SJjZ3GreBjugAfAUGrhqe2bjOQWked6ECt8r qTgJYmdg/OnDAvF212GXfMVwz+RBmLybEkCuK6hXkZTE0HMg51vSXmEQMETkDyZPNKjs1+ymj R29NjKB1yM1jffdtJNwg610N9FpcktWdTbHmLE9OmkJjES+wqGAWYFMFG1l14NtF15Y/2mrOG 6js2PxD5y9eip9QQ598k5xLSCIxwCN/F4emgJHgJvHNPxKrgsey7mG6+Y33sQraAyknECWOD8 9Bmar1C0T+eeJnSX1A6w+GhgOHbOgK8O+RwM9iMCsTMe4kdgvocFLYSl4f/HnBhc590xaF6K+ BoMZpOixb44lhYBlQMmazV031GjB98NjChLgKJJn7PpVmUzaIEoKtKywx7Fr3E65ulrMB9L6c hsl+S9xGx2GGnTgDC4zIn3UHR9aqfIMnI4RHo1R8GFKT5k+PZLT4ySZ/di1S3s+ytJD0FOQtZ 8klCYe0fu1AnUmzxNI8uUNcxHdvJSFdGQGSJHSRZcCn+EPcycQ8N41igza5Lm8Sd7yB/h7CU8 SCupDilEpFisswiVR3U9uOPsqRdHvCyk2Iqla2OGQtG/aIQt45FBOvgjLcRgR9WMPAJUeqF9E WD0to2e7rQnYhHwQZkHNTYu3264pGY3eOyLD339AKebT/2yFFm42KVJRDJrKHrrxleTtvSyv1 j2wr1UOHK2GHjkzswQj/jOOHKlLj9qdEU8Dsttox6IdQD1nXrIETPZuBaKfIY4JJC8giGkLxi XffU0PlnKL07KQ/4LJ4p7Bc36Ob7rLYiRnqywps0vnwkGzM5eK/cDhEsj8pxVUzGJn5Z9bv3/ JsjbrbkSGSdkF/HxKUK8xwP4pZPOVuMght9J4ogqmybnbTTxljJKApE1dH4tB8fQ/8BgUD2PT VYHZdHVxch5mEI= X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Wim Van Sebroeck , linux-watchdog@vger.kernel.org, Stephen Boyd , Patrick Venture , Michael Turquette , Daniel Lezcano , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Avi Fishman , Rob Herring , Benjamin Fair , Philipp Zabel , Krzysztof Kozlowski , Tali Perry , Thomas Gleixner , Guenter Roeck , Tomer Maimon Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" This driver implements the following features w.r.t. the clock and reset controller in the WPCM450 SoC: - It calculates the rates for all clocks managed by the clock controller - It leaves the clock tree mostly unchanged, except that it enables/ disables clock gates based on usage. - It exposes the reset lines managed by the controller using the Generic Reset Controller subsystem NOTE: If the driver and the corresponding devicetree node are present, the driver will disable "unused" clocks. This is problem until the clock relations are properly declared in the devicetree (in a later patch). Until then, the clk_ignore_unused kernel parameter can be used as a workaround. Signed-off-by: Jonathan Neuschäfer --- drivers/clk/Makefile | 1 + drivers/clk/clk-wpcm450.c | 378 ++++++++++++++++++++++++++++++++++++++ drivers/reset/Kconfig | 2 +- 3 files changed, 380 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/clk-wpcm450.c -- 2.35.1 diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 2bd5ffd595bf3..07edb0f4ba8ba 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -73,6 +73,7 @@ obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o obj-$(CONFIG_COMMON_CLK_RS9_PCIE) += clk-renesas-pcie.o obj-$(CONFIG_COMMON_CLK_VC5) += clk-versaclock5.o obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o +obj-$(CONFIG_ARCH_WPCM450) += clk-wpcm450.o obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o # please keep this section sorted lexicographically by directory path name diff --git a/drivers/clk/clk-wpcm450.c b/drivers/clk/clk-wpcm450.c new file mode 100644 index 0000000000000..3b62b5961d5f0 --- /dev/null +++ b/drivers/clk/clk-wpcm450.c @@ -0,0 +1,378 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Nuvoton WPCM450 clock and reset controller driver. + * + * Copyright (C) 2022 Jonathan Neuschäfer + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +struct wpcm450_clk_pll { + struct clk_hw hw; + void __iomem *pllcon; + u8 flags; +}; + +#define to_wpcm450_clk_pll(_hw) container_of(_hw, struct wpcm450_clk_pll, hw) + +#define PLLCON_FBDV GENMASK(24, 16) +#define PLLCON_PRST BIT(13) +#define PLLCON_PWDEN BIT(12) +#define PLLCON_OTDV GENMASK(10, 8) +#define PLLCON_INDV GENMASK(5, 0) + +static unsigned long wpcm450_clk_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct wpcm450_clk_pll *pll = to_wpcm450_clk_pll(hw); + unsigned long fbdv, indv, otdv; + u64 rate; + u32 pllcon; + + if (parent_rate == 0) { + pr_err("%s: parent rate is zero", __func__); + return 0; + } + + pllcon = readl_relaxed(pll->pllcon); + + indv = FIELD_GET(PLLCON_INDV, pllcon) + 1; + fbdv = FIELD_GET(PLLCON_FBDV, pllcon) + 1; + otdv = FIELD_GET(PLLCON_OTDV, pllcon) + 1; + + rate = (u64)parent_rate * fbdv; + do_div(rate, indv * otdv); + + return rate; +} + +static int wpcm450_clk_pll_is_enabled(struct clk_hw *hw) +{ + struct wpcm450_clk_pll *pll = to_wpcm450_clk_pll(hw); + u32 pllcon; + + pllcon = readl_relaxed(pll->pllcon); + + return !(pllcon & PLLCON_PRST); +} + +static void wpcm450_clk_pll_disable(struct clk_hw *hw) +{ + struct wpcm450_clk_pll *pll = to_wpcm450_clk_pll(hw); + u32 pllcon; + + pllcon = readl_relaxed(pll->pllcon); + pllcon |= PLLCON_PRST | PLLCON_PWDEN; + writel(pllcon, pll->pllcon); +} + +static const struct clk_ops wpcm450_clk_pll_ops = { + .recalc_rate = wpcm450_clk_pll_recalc_rate, + .is_enabled = wpcm450_clk_pll_is_enabled, + .disable = wpcm450_clk_pll_disable +}; + +static struct clk_hw * +wpcm450_clk_register_pll(void __iomem *pllcon, const char *name, + const char *parent_name, unsigned long flags) +{ + struct wpcm450_clk_pll *pll; + struct clk_init_data init; + struct clk_hw *hw; + int ret; + + pll = kzalloc(sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.ops = &wpcm450_clk_pll_ops; + init.parent_names = &parent_name; + init.num_parents = 1; + init.flags = flags; + + pll->pllcon = pllcon; + pll->hw.init = &init; + + ret = clk_hw_register(NULL, &pll->hw); + if (ret) { + kfree(pll); + hw = ERR_PTR(ret); + } + + return &pll->hw; +} + +#define REG_CLKEN 0x00 +#define REG_CLKSEL 0x04 +#define REG_CLKDIV 0x08 +#define REG_PLLCON0 0x0c +#define REG_PLLCON1 0x10 +#define REG_PMCON 0x14 +#define REG_IRQWAKECON 0x18 +#define REG_IRQWAKEFLAG 0x1c +#define REG_IPSRST 0x20 + +struct wpcm450_pll_data { + const char *name; + const char *parent_name; + unsigned int reg; + unsigned long flags; +}; + +static const struct wpcm450_pll_data pll_data[] = { + { "pll0", "refclk", REG_PLLCON0, 0 }, + { "pll1", "refclk", REG_PLLCON1, 0 }, +}; + +struct wpcm450_clksel_data { + const char *name; + const char *const *parent_names; + unsigned int num_parents; + const u32 *table; + int shift; + int width; + int index; + unsigned long flags; +}; + +static const u32 parent_table[] = { 0, 1, 2 }; +static const char *const default_parents[] = { "pll0", "pll1", "refclk" }; +static const char *const huart_parents[] = { "refclk", "refdiv2" }; + +static const struct wpcm450_clksel_data clksel_data[] = { + { "cpusel", default_parents, ARRAY_SIZE(default_parents), + parent_table, 0, 2, -1, CLK_IS_CRITICAL }, + { "clkout", default_parents, ARRAY_SIZE(default_parents), + parent_table, 2, 2, -1, 0 }, + { "usbphy", default_parents, ARRAY_SIZE(default_parents), + parent_table, 6, 2, -1, 0 }, + { "uartsel", default_parents, ARRAY_SIZE(default_parents), + parent_table, 8, 2, WPCM450_CLK_USBPHY, 0 }, + { "huartsel", huart_parents, ARRAY_SIZE(huart_parents), + parent_table, 10, 1, -1, 0 }, +}; + +static const struct clk_div_table div_default[] = { + { .val = 0, .div = 1, }, + { .val = 1, .div = 2, }, + { .val = 2, .div = 4, }, + { .val = 3, .div = 8, }, + { } +}; + +static const struct clk_div_table div_ahb[] = { + { .val = 0, .div = 1, }, + { .val = 1, .div = 2, }, + { } +}; + +static const struct clk_div_table div_fixed2[] = { + { .val = 0, .div = 2 }, + { } +}; + +struct wpcm450_clkdiv_data { + const char *name; + const char *parent_name; + int div_flags; + const struct clk_div_table *table; + int shift; + int width; + unsigned long flags; +}; + +static struct wpcm450_clkdiv_data clkdiv_data_early[] = { + { "refdiv2", "refclk", 0, div_fixed2, 0, 0 }, +}; + +static const struct wpcm450_clkdiv_data clkdiv_data[] = { + { "cpu", "cpusel", 0, div_fixed2, 0, 0, CLK_IS_CRITICAL }, + { "adcdiv", "refclk", CLK_DIVIDER_POWER_OF_TWO, NULL, 28, 2, 0 }, + { "apb", "ahb", CLK_DIVIDER_POWER_OF_TWO, NULL, 26, 2, 0 }, + { "ahb", "cpu", CLK_DIVIDER_POWER_OF_TWO, NULL, 24, 2, 0 }, + { "uart", "uartsel", 0, NULL, 16, 4, 0 }, + { "ahb3", "ahb", CLK_DIVIDER_POWER_OF_TWO, NULL, 8, 2, 0 }, +}; + +struct wpcm450_clken_data { + const char *name; + const char *parent_name; + int bitnum; + unsigned long flags; +}; + +static const struct wpcm450_clken_data clken_data[] = { + { "fiu", "ahb3", WPCM450_CLK_FIU, 0 }, + { "xbus", "ahb3", WPCM450_CLK_XBUS, 0 }, + { "kcs", "apb", WPCM450_CLK_KCS, 0 }, + { "shm", "ahb3", WPCM450_CLK_SHM, 0 }, + { "usb1", "ahb", WPCM450_CLK_USB1, 0 }, + { "emc0", "ahb", WPCM450_CLK_EMC0, 0 }, + { "emc1", "ahb", WPCM450_CLK_EMC1, 0 }, + { "usb0", "ahb", WPCM450_CLK_USB0, 0 }, + { "peci", "apb", WPCM450_CLK_PECI, 0 }, + { "aes", "apb", WPCM450_CLK_AES, 0 }, + { "uart0", "uart", WPCM450_CLK_UART0, 0 }, + { "uart1", "uart", WPCM450_CLK_UART1, 0 }, + { "smb2", "apb", WPCM450_CLK_SMB2, 0 }, + { "smb3", "apb", WPCM450_CLK_SMB3, 0 }, + { "smb4", "apb", WPCM450_CLK_SMB4, 0 }, + { "smb5", "apb", WPCM450_CLK_SMB5, 0 }, + { "huart", "huartsel", WPCM450_CLK_HUART, 0 }, + { "pwm", "apb", WPCM450_CLK_PWM, 0 }, + { "timer0", "refdiv2", WPCM450_CLK_TIMER0, 0 }, + { "timer1", "refdiv2", WPCM450_CLK_TIMER1, 0 }, + { "timer2", "refdiv2", WPCM450_CLK_TIMER2, 0 }, + { "timer3", "refdiv2", WPCM450_CLK_TIMER3, 0 }, + { "timer4", "refdiv2", WPCM450_CLK_TIMER4, 0 }, + { "mft0", "apb", WPCM450_CLK_MFT0, 0 }, + { "mft1", "apb", WPCM450_CLK_MFT1, 0 }, + { "wdt", "refdiv2", WPCM450_CLK_WDT, 0 }, + { "adc", "adcdiv", WPCM450_CLK_ADC, 0 }, + { "sdio", "ahb", WPCM450_CLK_SDIO, 0 }, + { "sspi", "apb", WPCM450_CLK_SSPI, 0 }, + { "smb0", "apb", WPCM450_CLK_SMB0, 0 }, + { "smb1", "apb", WPCM450_CLK_SMB1, 0 }, +}; + +static DEFINE_SPINLOCK(wpcm450_clk_lock); + +static void __init wpcm450_clk_init(struct device_node *clk_np) +{ + struct clk_hw_onecell_data *clk_data; + static struct clk_hw **hws; + static struct clk_hw *hw; + void __iomem *clk_base; + int i, ret; + struct reset_controller_dev *rcdev; + + clk_base = of_iomap(clk_np, 0); + if (!clk_base) { + pr_err("%pOFP: failed to map registers\n", clk_np); + of_node_put(clk_np); + return; + } + of_node_put(clk_np); + + clk_data = kzalloc(struct_size(clk_data, hws, WPCM450_NUM_CLKS), GFP_KERNEL); + if (!clk_data) + goto err_unmap; + + clk_data->num = WPCM450_NUM_CLKS; + hws = clk_data->hws; + + for (i = 0; i < WPCM450_NUM_CLKS; i++) + hws[i] = ERR_PTR(-ENOENT); + + // PLLs + for (i = 0; i < ARRAY_SIZE(pll_data); i++) { + const struct wpcm450_pll_data *data = &pll_data[i]; + + hw = wpcm450_clk_register_pll(clk_base + data->reg, data->name, + data->parent_name, data->flags); + if (IS_ERR(hw)) { + pr_info("Failed to register PLL: %pe", hw); + goto err_free; + } + } + + // Early divisors (REF/2) + for (i = 0; i < ARRAY_SIZE(clkdiv_data_early); i++) { + const struct wpcm450_clkdiv_data *data = &clkdiv_data_early[i]; + + hw = clk_hw_register_divider_table(NULL, data->name, data->parent_name, + data->flags, clk_base + REG_CLKDIV, + data->shift, data->width, data->div_flags, + data->table, &wpcm450_clk_lock); + if (IS_ERR(hw)) { + pr_err("Failed to register div table: %pe\n", hw); + goto err_free; + } + } + + // Selects/muxes + for (i = 0; i < ARRAY_SIZE(clksel_data); i++) { + const struct wpcm450_clksel_data *data = &clksel_data[i]; + + hw = clk_hw_register_mux_table(NULL, data->name, data->parent_names, + data->num_parents, data->flags, + clk_base + REG_CLKSEL, data->shift, + BIT(data->width) - 1, 0, data->table, + &wpcm450_clk_lock); + if (IS_ERR(hw)) { + pr_err("Failed to register mux: %pe\n", hw); + goto err_free; + } + if (data->index >= 0) + clk_data->hws[data->index] = hw; + } + + // Divisors + for (i = 0; i < ARRAY_SIZE(clkdiv_data); i++) { + const struct wpcm450_clkdiv_data *data = &clkdiv_data[i]; + + hw = clk_hw_register_divider_table(NULL, data->name, data->parent_name, + data->flags, clk_base + REG_CLKDIV, + data->shift, data->width, data->div_flags, + data->table, &wpcm450_clk_lock); + if (IS_ERR(hw)) { + pr_err("Failed to register divider: %pe\n", hw); + goto err_free; + } + } + + // Enables/gates + for (i = 0; i < ARRAY_SIZE(clken_data); i++) { + const struct wpcm450_clken_data *data = &clken_data[i]; + + hw = clk_hw_register_gate(NULL, data->name, data->parent_name, data->flags, + clk_base + REG_CLKEN, data->bitnum, + data->flags, &wpcm450_clk_lock); + if (IS_ERR(hw)) { + pr_err("Failed to register gate: %pe\n", hw); + goto err_free; + } + clk_data->hws[data->bitnum] = hw; + } + + ret = of_clk_add_hw_provider(clk_np, of_clk_hw_onecell_get, clk_data); + if (ret) + pr_err("Failed to add DT provider: %d\n", ret); + + // Reset controller + rcdev = kzalloc(sizeof(*rcdev), GFP_KERNEL); + if (!rcdev) + goto err_free; + rcdev->owner = THIS_MODULE; + rcdev->nr_resets = WPCM450_NUM_RESETS; + rcdev->ops = &reset_simple_ops; + rcdev->of_node = clk_np; + ret = reset_controller_register(rcdev); + if (ret) + pr_err("Failed to register reset controller: %d\n", ret); + + of_node_put(clk_np); + return; + +err_free: + kfree(clk_data->hws); +err_unmap: + iounmap(clk_base); + of_node_put(clk_np); +} + +CLK_OF_DECLARE(wpcm450_clk_init, "nuvoton,wpcm450-clk", wpcm450_clk_init); diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index b496028b6bfaf..50a3c1403c335 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -201,7 +201,7 @@ config RESET_SCMI config RESET_SIMPLE bool "Simple Reset Controller Driver" if COMPILE_TEST - default ARCH_ASPEED || ARCH_BCM4908 || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC + default ARCH_ASPEED || ARCH_BCM4908 || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC || ARCH_NPCM help This enables a simple reset controller driver for reset lines that that can be asserted and deasserted by toggling bits in a contiguous, From patchwork Fri Apr 22 18:30:12 2022 Content-Type: text/plain; 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Sat, 23 Apr 2022 04:32:32 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1650652318; bh=6YuxGgl4dOw9oAtmXhuC816ahBzK2oYrigEc+RKljBI=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=Go7zofTF6VMJRn7qW+oJommJYwhjfFcXJzv5LakxOCslLGDutZ6HaggT8fztUwkXn qAjfRNfUQqiAY/quf7Zvm4kHmvmolRVq211U4H14tfh88R4GzupuLV13PIZUinAkVY S1HeXSRtjgLKj1YKMKrkgRU8o8EoBt/U0Y2KsV2w= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([87.78.190.74]) by mail.gmx.net (mrgmx105 [212.227.17.168]) with ESMTPSA (Nemesis) id 1N7iCg-1nuMSS1S6M-014olk; Fri, 22 Apr 2022 20:31:58 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Subject: [PATCH 7/7] ARM: dts: wpcm450: Switch clocks to clock controller Date: Fri, 22 Apr 2022 20:30:12 +0200 Message-Id: <20220422183012.444674-8-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220422183012.444674-1-j.neuschaefer@gmx.net> References: <20220422183012.444674-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:I67tF9Nlj04Phq6/V+ryuFf0Cliytuu3Zmf4FI2sPERSmiXM3XH R2sSgG7ktBlSjy9OdFQrd6Ec/8zwv1ZLrWy6vGPGRzJYTJArz+9bFEhqtpLtcF+CTwEUHq6 BpWfwBxU2AxUAF5JBamEAauV775wUODEbE6nCW1yOWZPbsvznU4uZmjcPzjJRpLIujUNFFB ooGmDpfMZ9LxJkCORbk5A== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1;V03:K0:8c54XHSt3ac=:psA86FAB40KotvKaXr6W0Y wCL17K1pimNjF5dquW7DU2tt03i/m3ex/mnWKTxeiSFqDogjnxeTMf4lJPtoaqdxBTMdbZYBY tZPZg7l/jzHhniSnCujCZ7XhdrjubncnSzGdwVXtUJjG8hVrUTWpddtPPR0en0a+OCUWgH/ML QKeKyN1CNH4O4VzpQEKoMeMb6U2XfD4NiaZ93AZrNR3YxhMD76AVY3jxOLFyuCk1vDulLgBY8 1jklPSJNj/ZSea39mdgMU5e0WTc8CqmMTT3ICyYtU6PK7lmin3JvkjKJ3hnwhJmOrLq6WNt6w giYfzIUKUQDmdKF9S7vMpDHnd8DASR+SKtF/zGGeKxhpwHYosp7tVV6iClUjTG4IAXAhPd2dP pmV+V/cV00ha/fZ1/HEcwvXRChok8HNMV+epsnlIbw9lZWj32QMcpwQoKnEzG5QbxY6QIOnUr pFlB1FaNGcS9PyetgcLTrrLOAWWeireG035G/kW3KHnQR0an9wG9lpiISQKMhP1GqqIYpFBGt e61jm4+TIGFftMf5UwMjLyK/Sjw/GRP7dPTKUztWVKGgQ5Pi491C5kxhPyNVl9UwKuZqrAvJu /TR2//if06otGpwJpfhWnENL62+CwuWmvJDxwyqZW7NtDpcVm1XXRdM0tZykAAkCKDbfIRvtl ffDN8JUztcs4bqnNGZHXVo1uk6S6oiE9NFe7hzB3K5gkcSz61zgNQnysD2sMocZ7Oqbf8C+Fc NDFcwh/McjhFmZ9fqjus4YGICtiXGHVx2vVXBaI2CBMpDGHgokMXwHHrqLblp5q4xF0Ae7MIf hImxk3BsuZGViYNlrB2++iHEkxLBkzrAun3DSk9QnWq15ZmUAnJpxmGneAzYpoTFrgfXRgtlt 8SW33KDhlympKpRNygP7UMX/P10W209j0GBZaBWeH5mtam55RcwRtY6QEFIKsbrTrghKOMuFx 0lRYRimBM2TUIeLEz3ebCb+X7B/FRO7jN0Gv3I8DdVecSUzKqeDpVGIZzfwYv1jY6mYYdDwx5 Ws1eFN1cHtt3A5/rn8y/FmibRGGzMAPz1asfL5N7Ujl7gCDDXR4Zh5TchoK2Og2Y7GYfLTIfn Etbdy8JIwXiS/c= X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Wim Van Sebroeck , linux-watchdog@vger.kernel.org, Stephen Boyd , Patrick Venture , Michael Turquette , Daniel Lezcano , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Avi Fishman , Rob Herring , Benjamin Fair , Philipp Zabel , Krzysztof Kozlowski , Tali Perry , Thomas Gleixner , Guenter Roeck , Tomer Maimon Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" This change is incompatible with older kernels because it requires the clock controller driver, but I think that's acceptable because WPCM450 support is generally still in an early phase. Signed-off-by: Jonathan Neuschäfer --- arch/arm/boot/dts/nuvoton-wpcm450.dtsi | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) -- 2.35.1 diff --git a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi index 62d70fda7b520..f868bd7db009a 100644 --- a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi +++ b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi @@ -2,6 +2,7 @@ // Copyright 2021 Jonathan Neuschäfer #include +#include / { compatible = "nuvoton,wpcm450"; @@ -32,13 +33,6 @@ cpu@0 { }; }; - clk24m: clock-24mhz { - /* 24 MHz dummy clock */ - compatible = "fixed-clock"; - clock-frequency = <24000000>; - #clock-cells = <0>; - }; - refclk: clock-48mhz { /* 48 MHz reference oscillator */ compatible = "fixed-clock"; @@ -73,7 +67,7 @@ serial0: serial@b8000000 { reg = <0xb8000000 0x20>; reg-shift = <2>; interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk24m>; + clocks = <&clk WPCM450_CLK_UART0>; pinctrl-names = "default"; pinctrl-0 = <&bsp_pins>; status = "disabled"; @@ -84,7 +78,7 @@ serial1: serial@b8000100 { reg = <0xb8000100 0x20>; reg-shift = <2>; interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk24m>; + clocks = <&clk WPCM450_CLK_UART1>; status = "disabled"; }; @@ -92,14 +86,18 @@ timer0: timer@b8001000 { compatible = "nuvoton,wpcm450-timer"; interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; reg = <0xb8001000 0x1c>; - clocks = <&clk24m>; + clocks = <&clk WPCM450_CLK_TIMER0>, + <&clk WPCM450_CLK_TIMER1>, + <&clk WPCM450_CLK_TIMER2>, + <&clk WPCM450_CLK_TIMER3>, + <&clk WPCM450_CLK_TIMER4>; }; watchdog0: watchdog@b800101c { compatible = "nuvoton,wpcm450-wdt"; interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; reg = <0xb800101c 0x4>; - clocks = <&clk24m>; + clocks = <&clk WPCM450_CLK_WDT>; }; aic: interrupt-controller@b8002000 {