From patchwork Thu Apr 14 01:18:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hongyu Wang X-Patchwork-Id: 1617005 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=X/60G+8c; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4Kf1nC0LR2z9sFr for ; Thu, 14 Apr 2022 11:18:37 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CFC883858C83 for ; Thu, 14 Apr 2022 01:18:35 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org CFC883858C83 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1649899115; bh=FQjtC6vTzInmYB5b5MUPfNV5j6ZExsmbaMOgBnRqpsw=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=X/60G+8cVyVyBQe3qq/InGifkJkw2HNzq4lu3zuUQn+O+WquKtX/E92L97Uq42X4b RPhmVdNdw0tRi+VvAmbpW5hI/0HihwSOtk7Q7TErxsacYXYEaTe11rM9sV4bL1I73m UscVGCZqMD3j3jaxhSa6anKYveA/38bDnkaIzekY= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by sourceware.org (Postfix) with ESMTPS id 3E64F3858D3C for ; Thu, 14 Apr 2022 01:18:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 3E64F3858D3C X-IronPort-AV: E=McAfee;i="6400,9594,10316"; a="244703221" X-IronPort-AV: E=Sophos;i="5.90,258,1643702400"; d="scan'208";a="244703221" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2022 18:18:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,258,1643702400"; d="scan'208";a="552438727" Received: from scymds01.sc.intel.com ([10.148.94.138]) by orsmga007.jf.intel.com with ESMTP; 13 Apr 2022 18:18:13 -0700 Received: from shliclel320.sh.intel.com (shliclel320.sh.intel.com [10.239.236.50]) by scymds01.sc.intel.com with ESMTP id 23E1IChR026178; Wed, 13 Apr 2022 18:18:12 -0700 To: ubizjak@gmail.com Subject: [PATCH] i386: Disable stv under optimize_size [PR 105034] Date: Thu, 14 Apr 2022 09:18:11 +0800 Message-Id: <20220414011811.62291-1-hongyu.wang@intel.com> X-Mailer: git-send-email 2.18.1 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_SHORT, SPF_HELO_NONE, SPF_SOFTFAIL, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Hongyu Wang via Gcc-patches From: Hongyu Wang Reply-To: Hongyu Wang Cc: gcc-patches@gcc.gnu.org Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Hi, From -Os point of view, stv converts scalar register to vector mode which introduces extra reg conversion and increase instruction size. Disabling stv under optimize_size would avoid such code size increment and no need to touch ix86_size_cost that has not been tuned for long time. Bootstrapped/regtested on x86_64-pc-linux-gnu{-m32,}, Ok for master? gcc/ChangeLog: PR target/105034 * config/i386/i386-features.cc (pass_stv::gate()): Block out optimize_size. gcc/testsuite/ChangeLog: PR target/105034 * gcc.target/i386/pr105034.c: New test. --- gcc/config/i386/i386-features.cc | 3 ++- gcc/testsuite/gcc.target/i386/pr105034.c | 23 +++++++++++++++++++++++ 2 files changed, 25 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr105034.c diff --git a/gcc/config/i386/i386-features.cc b/gcc/config/i386/i386-features.cc index 6fe41c3c24f..f57281e672f 100644 --- a/gcc/config/i386/i386-features.cc +++ b/gcc/config/i386/i386-features.cc @@ -1911,7 +1911,8 @@ public: virtual bool gate (function *) { return ((!timode_p || TARGET_64BIT) - && TARGET_STV && TARGET_SSE2 && optimize > 1); + && TARGET_STV && TARGET_SSE2 && optimize > 1 + && !optimize_size); } virtual unsigned int execute (function *) diff --git a/gcc/testsuite/gcc.target/i386/pr105034.c b/gcc/testsuite/gcc.target/i386/pr105034.c new file mode 100644 index 00000000000..d997e26e9ed --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr105034.c @@ -0,0 +1,23 @@ +/* PR target/105034 */ +/* { dg-do compile } */ +/* { dg-options "-Os -msse4.1" } */ + +#define max(a,b) (((a) > (b))? (a) : (b)) +#define min(a,b) (((a) < (b))? (a) : (b)) + +int foo(int x) +{ + return max(x,0); +} + +int bar(int x) +{ + return min(x,0); +} + +unsigned int baz(unsigned int x) +{ + return min(x,1); +} + +/* { dg-final { scan-assembler-not "xmm" } } */