From patchwork Wed Apr 13 05:34:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Billy Tsai X-Patchwork-Id: 1616723 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4Kdh2W1cZrz9s3q for ; Wed, 13 Apr 2022 21:58:56 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 224EF83B4D; Wed, 13 Apr 2022 13:58:48 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=aspeedtech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 8246383BE4; Wed, 13 Apr 2022 07:35:21 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from twspam01.aspeedtech.com (twspam01.aspeedtech.com [211.20.114.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id AA45683ABE for ; Wed, 13 Apr 2022 07:35:14 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=aspeedtech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=billy_tsai@aspeedtech.com Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 23D5NCB0076601; Wed, 13 Apr 2022 13:23:12 +0800 (GMT-8) (envelope-from billy_tsai@aspeedtech.com) Received: from BillyTsai-pc.aspeed.com (192.168.2.149) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 13 Apr 2022 13:34:55 +0800 From: Billy Tsai To: , , , , , Subject: [PATCH] gpio: aspeed: Fix incorrect offset of read back register. Date: Wed, 13 Apr 2022 13:34:51 +0800 Message-ID: <20220413053451.2975-1-billy_tsai@aspeedtech.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Originating-IP: [192.168.2.149] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 23D5NCB0076601 X-Mailman-Approved-At: Wed, 13 Apr 2022 13:58:46 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean The offset of the current read back register is the value of the gpio pin, not the value written for the gpio output. This patch fix it to avoid the other gpio output value controlled by the same register being set incorrectly. Fixes: 7ad889b0f37a ("gpio: Add Aspeed GPIO driver") Signed-off-by: Billy Tsai --- drivers/gpio/gpio-aspeed.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c index a8a2afcb5c..2c5415c671 100644 --- a/drivers/gpio/gpio-aspeed.c +++ b/drivers/gpio/gpio-aspeed.c @@ -211,7 +211,7 @@ static int aspeed_gpio_direction_output(struct udevice *dev, unsigned int offset struct aspeed_gpio_priv *priv = dev_get_priv(dev); const struct aspeed_gpio_bank *bank = to_bank(offset); u32 dir = readl(bank_reg(priv, bank, reg_dir)); - u32 output = readl(bank_reg(priv, bank, reg_val)); + u32 output = readl(bank_reg(priv, bank, reg_rdata)); dir |= GPIO_BIT(offset); writel(dir, bank_reg(priv, bank, reg_dir)); @@ -239,7 +239,7 @@ aspeed_gpio_set_value(struct udevice *dev, unsigned int offset, int value) { struct aspeed_gpio_priv *priv = dev_get_priv(dev); const struct aspeed_gpio_bank *bank = to_bank(offset); - u32 data = readl(bank_reg(priv, bank, reg_val)); + u32 data = readl(bank_reg(priv, bank, reg_rdata)); if (value) data |= GPIO_BIT(offset);