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[73.63.24.84]) by smtp.gmail.com with ESMTPSA id j24-20020aa78d18000000b0050564584660sm12731191pfe.32.2022.04.10.20.06.23 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 10 Apr 2022 20:06:23 -0700 (PDT) Message-ID: <4387ce74-8d8c-9716-b489-e5d2ceace268@gmail.com> Date: Sun, 10 Apr 2022 21:06:22 -0600 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Content-Language: en-US To: 'GCC Patches' Subject: [committed] Minor bfin codegen bugfix X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00, BODY_8BITS, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jeff Law via Gcc-patches From: Jeff Law Reply-To: Jeff Law Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" builtin-arith-overflow-3 has been failing on bfin-elf for a while. I've had a workaround installed on the tester for a few months and I finally got some time to dig into it over the weekend. Ultimately I was able to nail the problem down to the representation of the rotate left by one position instruction.  I'm actually quite happy with that result as I was briefly worried it was a deeper problem in combine. Essentially we're trying to synthesize a DImode shift using an SImode rotates through CC.  The key backend insn looks like: > (define_insn "rol_one" >   [(set (match_operand:SI 0 "register_operand" "+d") >         (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d") > (const_int 1)) >                 (zero_extend:SI (reg:BI REG_CC)))) >    (set (reg:BI REG_CC) >         (zero_extract:BI (match_dup 1) (const_int 31) (const_int 0)))] >   "" >   "%0 = ROT %1 BY 1%!" >   [(set_attr "type" "dsp32shiftimm")]) What the 2nd set in the pattern wants to do is indicate that CC is set to the high bit from operand 1.  But the RTL pattern is completely bogus as it's asking for a 31 bit wide field starting at offset 0, which is just silly for BImode.  That bogus representation led combine to do some "unexpected" transformations. The obvious fix is to use (const_int 1) (const_int 31) in the 2nd set.  That indicates we want one bit starting at position 31. With that pattern fixed, bfin returns to a normal state without needing my workaround. Installed on the trunk, Jeff commit 8d331aab65488b3998bd106205bbe6cab5df31b5 Author: Jeff Law Date: Sun Apr 10 23:02:48 2022 -0400 [committed] Minor bfin codegen bugfix gcc/ * config/bfin/bfin.md (rol_one): Fix pattern to indicate the sign bit of the source ends up in CC. diff --git a/gcc/config/bfin/bfin.md b/gcc/config/bfin/bfin.md index 0e44653d7cb..56b24726bc2 100644 --- a/gcc/config/bfin/bfin.md +++ b/gcc/config/bfin/bfin.md @@ -1741,7 +1741,7 @@ (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "d") (const_int 1)) (zero_extend:SI (reg:BI REG_CC)))) (set (reg:BI REG_CC) - (zero_extract:BI (match_dup 1) (const_int 31) (const_int 0)))] + (zero_extract:BI (match_dup 1) (const_int 1) (const_int 31)))] "" "%0 = ROT %1 BY 1%!" [(set_attr "type" "dsp32shiftimm")])