From patchwork Tue Feb 20 01:43:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 875367 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="NIZ/FT96"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zlk1t6GYhz9s08 for ; Tue, 20 Feb 2018 12:44:34 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932339AbeBTBnw (ORCPT ); Mon, 19 Feb 2018 20:43:52 -0500 Received: from mail-pg0-f66.google.com ([74.125.83.66]:35715 "EHLO mail-pg0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932294AbeBTBnu (ORCPT ); Mon, 19 Feb 2018 20:43:50 -0500 Received: by mail-pg0-f66.google.com with SMTP id l131so6557013pga.2; Mon, 19 Feb 2018 17:43:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=hRnbzntjcoWVIVTIk176wK/iiI+i0X5c3lUi8VEj4Wk=; b=NIZ/FT96OnexTB2QP+mryNspyo0Yi9O6w0n/Zv1nsKTXv5JPVaWZoWLxyxMa71Up14 2LSVVLHXnIDViEritksce2Cct6HhshNeBu7XAjs+cLqjpZYpVegcE03rh5O3ZpzcHrLx KfdFyXQ8vzPQ54kXXT+f++lBoP7E4dbGuv1nCAeBV5m9DHEG5L4DE0iBNnXJUPEfmEnd vrz15W8uJYQMZj5Uj11EfhpyLiPVLYKy/UjqYjMAcE/JoV+UlnicAoXWmh1eWVhusqR8 hMHRprom+L7STHnyNMyb9CF6+jsVXd/cDPtTvqtqe2ozcMYhu/ktV9RcEpjq5JVnp4NE 4Cuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=hRnbzntjcoWVIVTIk176wK/iiI+i0X5c3lUi8VEj4Wk=; b=D96CfhIA4C+Nq8uE8Ym1yoI/pv8fty63M1r1w7qcrm9giKmEmbudUlmh3K4Q2eJEQW YXllRN3of9/exsTocTM8JhKLcC4G2P6IaLLUUig9F4LADz+Cw4PdbPrzwA4pkuGVo8OQ XtU0TO6STId5rV9ztNAdsXWyeibypZGMJnUxXRb538hoYj8yepkRfDu7VxXu0fGZ/w2t cspptU8vgnR65UK3m6+83qkHeWU9ZZ4/3f+GmX4i8Cd8X7VCcqN/9B+FUHkGO+KD21de Zy/ww0lHAfxByZUbMhwe95oLo9zqNDfPNkBPsdW+VXrJKlU4ICfrYuexBywa5au9qgCX 1ABA== X-Gm-Message-State: APf1xPBNKdvxesH+R4i+582YOaBUfIl0vgPsR6tftk1SEc9yMeXUebns nTNffKcgK+yG6RPOOsm3tbU= X-Google-Smtp-Source: AH8x225R6sZeYcIQzCQ6WEez1TQJuzcfHOzM4+pN/MPlpACR0n+go+0m7xbNS51I4Za7TdATctLYyg== X-Received: by 10.99.107.198 with SMTP id g189mr13363150pgc.299.1519091029561; Mon, 19 Feb 2018 17:43:49 -0800 (PST) Received: from aurora.jms.id.au ([45.124.203.14]) by smtp.gmail.com with ESMTPSA id w22sm1517066pge.65.2018.02.19.17.43.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 19 Feb 2018 17:43:48 -0800 (PST) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Tue, 20 Feb 2018 12:13:41 +1030 From: Joel Stanley To: Rob Herring , Mark Rutland , Philipp Zabel , Andrew Jeffery Cc: Lee Jones , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-aspeed@lists.ozlabs.org Subject: [PATCH v2 1/3] dt-bindings: aspeed-lpc: Add reset controller Date: Tue, 20 Feb 2018 12:13:28 +1030 Message-Id: <20180220014330.23425-2-joel@jms.id.au> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180220014330.23425-1-joel@jms.id.au> References: <20180220014330.23425-1-joel@jms.id.au> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This describes the reset controller present in the LPC address space. Reviewed-by: Rob Herring Signed-off-by: Joel Stanley --- V2: Fix spelling mistakes --- .../devicetree/bindings/mfd/aspeed-lpc.txt | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt index 514d82ced95b..9bdd3e8c91ec 100644 --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt @@ -135,3 +135,24 @@ lhc: lhc@20 { compatible = "aspeed,ast2500-lhc"; reg = <0x20 0x24 0x48 0x8>; }; + +LPC reset control +----------------- + +The UARTs present in the ASPEED SoC can have their resets tied to the reset +state of the LPC bus. Some systems may chose to modify this configuration. + +Required properties: + + - compatible: "aspeed,ast2500-lpc-reset" or + "aspeed,ast2400-lpc-reset" + - reg: offset and length of the IP in the LHC memory region + - #reset-controller indicates the number of reset cells expected + +Example: + +lpc_reset: reset-controller@18 { + compatible = "aspeed,ast2500-lpc-reset"; + reg = <0x18 0x4>; + #reset-cells = <1>; +};