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[220.235.208.104]) by smtp.gmail.com with ESMTPSA id q10-20020a056a00088a00b004f7ceff389esm27941819pfj.152.2022.04.08.08.52.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 08:52:04 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sat, 9 Apr 2022 01:51:59 +1000 Message-Id: <20220408155159.1002906-1-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 MIME-Version: 1.0 Subject: [Skiboot] [PATCH] core: detect LPAR-per-core mode and report in dt X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Some firmware configurations boot in LPAR-per-core mode, which is not compatible with KVM on POWER9 and later machines. Detect which LPAR mode the boot core is in (all others will be set the same way), and if booted in LPAR-per-core mode then print a warning and add a device-tree entry that the OS can test for. Signed-off-by: Nicholas Piggin --- core/init.c | 38 ++++++++++++++++++++++++++++++++++++++ hdata/cpu-common.c | 2 ++ include/skiboot.h | 2 ++ 3 files changed, 42 insertions(+) diff --git a/core/init.c b/core/init.c index a1fd5f2b9..005ecf319 100644 --- a/core/init.c +++ b/core/init.c @@ -48,6 +48,7 @@ #include #include #include +#include #include enum proc_gen proc_gen; @@ -1026,6 +1027,40 @@ static void mask_pc_system_xstop(void) } } +bool lpar_per_core = false; + +static void probe_lpar_per_core(void) +{ + struct cpu_thread *cpu = this_cpu(); + uint32_t chip_id = pir_to_chip_id(cpu->pir); + uint32_t core_id = pir_to_core_id(cpu->pir); + uint64_t addr; + uint64_t core_thread_state; + int rc; + + if (chip_quirk(QUIRK_MAMBO_CALLOUTS) || chip_quirk(QUIRK_AWAN)) + return; + + if (proc_gen == proc_gen_p9) + addr = XSCOM_ADDR_P9_EC(core_id, P9_CORE_THREAD_STATE); + else if (proc_gen == proc_gen_p10) + addr = XSCOM_ADDR_P10_EC(core_id, P10_EC_CORE_THREAD_STATE); + else + return; + + rc = xscom_read(chip_id, addr, &core_thread_state); + if (rc) { + prerror("Error reading CORE_THREAD_STATE rc:%d on PIR:%x\n", + rc, cpu->pir); + return; + } + + if (core_thread_state & PPC_BIT(62)) { + lpar_per_core = true; + prlog(PR_WARNING, "LPAR-per-core mode detected. KVM may not be usable."); + } +} + /* Called from head.S, thus no prototype. */ void __noreturn __nomcount main_cpu_entry(const void *fdt); @@ -1211,6 +1246,9 @@ void __noreturn __nomcount main_cpu_entry(const void *fdt) /* Once all CPU are up apply this workaround */ mask_pc_system_xstop(); + /* P9/10 may be in LPAR-per-core mode, which is incompatible with KVM */ + probe_lpar_per_core(); + /* Add the /opal node to the device-tree */ add_opal_node(); diff --git a/hdata/cpu-common.c b/hdata/cpu-common.c index 2248f9b61..4ba1430b2 100644 --- a/hdata/cpu-common.c +++ b/hdata/cpu-common.c @@ -127,6 +127,8 @@ struct dt_node * add_core_common(struct dt_node *cpus, dt_add_property_cells(cpu, "ibm,mmu-pid-bits", 20); dt_add_property_cells(cpu, "ibm,mmu-lpid-bits", 12); } + if (lpar_per_core) + dt_add_property(cpu, "ibm,mmu-lpar-per-core", NULL, 0); /* HPT segment page size encodings, common to all supported CPUs */ dt_add_property_cells(cpu, "ibm,segment-page-sizes", diff --git a/include/skiboot.h b/include/skiboot.h index db08f45f4..b0b75a42c 100644 --- a/include/skiboot.h +++ b/include/skiboot.h @@ -103,6 +103,8 @@ enum proc_gen { }; extern enum proc_gen proc_gen; +extern bool lpar_per_core; + extern unsigned int pcie_max_link_speed; /* Convert a 4-bit number to a hex char */