From patchwork Thu Apr 7 17:23:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Andre Vieira (lists)" X-Patchwork-Id: 1614582 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=gjfHHPoO; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4KZ7X35tWzz9sFt for ; Fri, 8 Apr 2022 03:23:46 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 221EC3858405 for ; Thu, 7 Apr 2022 17:23:44 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 221EC3858405 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1649352224; bh=eZS7yk5md0eELYX35KoJ/OZcNvOzuh3AUuW7Hq9RPug=; h=Date:Subject:To:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=gjfHHPoOLIkcOWxQZ6l/J+sVAC2V5wZfWRVcTx8tcaF69aFT19KthEIdfRUe9aLt6 RHMTZPtCoBc1prZ9D/bSi0mPSK2s+5gxt1Ux9Eka3Kz9874dn8asJAnGJRbNGcp6Z5 pi93agwlk17iY8YOcb4UjnCPBfD8pVWvemYMj2oI= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 8F2EA3858D28 for ; Thu, 7 Apr 2022 17:23:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 8F2EA3858D28 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3620812FC; Thu, 7 Apr 2022 10:23:03 -0700 (PDT) Received: from [10.57.10.253] (unknown [10.57.10.253]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 59EDF3F718; Thu, 7 Apr 2022 10:23:02 -0700 (PDT) Message-ID: <181ffc5f-94d6-85dd-dd60-825e618cbd99@arm.com> Date: Thu, 7 Apr 2022 18:23:01 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Content-Language: en-US Subject: [AArch64] PR target/105157 Increase number of cores TARGET_CPU_DEFAULT can encode To: "gcc-patches@gcc.gnu.org" X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, BODY_8BITS, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_LOTSOFHASH, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "Andre Vieira \(lists\) via Gcc-patches" From: "Andre Vieira (lists)" Reply-To: "Andre Vieira \(lists\)" Cc: Richard Sandiford Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Hi, This addresses the compile-time increase seen in the PR target/105157. This was being caused by selecting the wrong core tuning, as when we added the latest AArch64 the TARGET_CPU_generic tuning was pushed beyond the 0x3f mask we used to encode both target cpu and attributes into TARGET_CPU_DEFAULT. This is a quick fix to increase the number of allowed cores for now late in stage 4, but for next GCC we plan to fix this in a more suitable and maintainable manner. gcc/ChangeLog:         PR target/105157         * config.gcc: Shift ext_mask by TARGET_CPU_NBITS.         * config/aarch64/aarch64.h (TARGET_CPU_NBITS): New macro.         (TARGET_CPU_MASK): Likewise.         (TARGET_CPU_DEFAULT): Use TARGET_CPU_NBITS.         * config/aarch64/aarch64.cc (aarch64_get_tune_cpu): Use TARGET_CPU_MASK.         (aarch64_get_arch): Likewise.         (aarch64_override_options): Use TARGET_CPU_NBITS.         (aarch64_run_selftests): Add test to guarantee TARGET_CPU_NBITS is big enough. diff --git a/gcc/config.gcc b/gcc/config.gcc index 2cc5aeec9e46aacc46e4e509d01f57f9f6585169..8946984f5e93cd6fe5364b44e74c64e714ba1d6a 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -4239,7 +4239,7 @@ case "${target}" in ext_val=`echo $ext_val | sed -e 's/[a-z0-9]\+//'` done - ext_mask="(("$ext_mask") << 6)" + ext_mask="(("$ext_mask") << TARGET_CPU_NBITS)" if [ x"$base_id" != x ]; then target_cpu_cname="TARGET_CPU_$base_id | $ext_mask" fi diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index efa46ac0b8799b5849b609d591186e26e5cb37ff..97b2d38dac9f13717e90f4f6996ab94814922950 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -813,10 +813,17 @@ enum target_cpus TARGET_CPU_generic }; + +/* Define how many bits are used to represent the CPU in TARGET_CPU_DEFAULT. + This needs to be big enough to fit the value of TARGET_CPU_generic. + All bits after this are used to represent the AARCH64_CPU_DEFAULT_FLAGS. */ +#define TARGET_CPU_NBITS 8 +#define TARGET_CPU_MASK ((1 << TARGET_CPU_NBITS) - 1) + /* If there is no CPU defined at configure, use generic as default. */ #ifndef TARGET_CPU_DEFAULT #define TARGET_CPU_DEFAULT \ - (TARGET_CPU_generic | (AARCH64_CPU_DEFAULT_FLAGS << 6)) + (TARGET_CPU_generic | (AARCH64_CPU_DEFAULT_FLAGS << TARGET_CPU_NBITS)) #endif /* If inserting NOP before a mult-accumulate insn remember to adjust the diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index d66626748e5edc46e46edf10e243114a9f74be97..9d83e007d7a31455c167bf21124cf9fbc0d31788 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -18062,12 +18062,12 @@ aarch64_get_tune_cpu (enum aarch64_processor cpu) if (cpu != aarch64_none) return &all_cores[cpu]; - /* The & 0x3f is to extract the bottom 6 bits that encode the - default cpu as selected by the --with-cpu GCC configure option + /* The & TARGET_CPU_MASK is to extract the bottom TARGET_CPU_NBITS bits that + encode the default cpu as selected by the --with-cpu GCC configure option in config.gcc. ???: The whole TARGET_CPU_DEFAULT and AARCH64_CPU_DEFAULT_FLAGS flags mechanism should be reworked to make it more sane. */ - return &all_cores[TARGET_CPU_DEFAULT & 0x3f]; + return &all_cores[TARGET_CPU_DEFAULT & TARGET_CPU_MASK]; } /* Return the architecture corresponding to the enum ARCH. @@ -18079,7 +18079,8 @@ aarch64_get_arch (enum aarch64_arch arch) if (arch != aarch64_no_arch) return &all_architectures[arch]; - const struct processor *cpu = &all_cores[TARGET_CPU_DEFAULT & 0x3f]; + const struct processor *cpu + = &all_cores[TARGET_CPU_DEFAULT & TARGET_CPU_MASK]; return &all_architectures[cpu->arch]; } @@ -18166,7 +18167,7 @@ aarch64_override_options (void) { /* Get default configure-time CPU. */ selected_cpu = aarch64_get_tune_cpu (aarch64_none); - aarch64_isa_flags = TARGET_CPU_DEFAULT >> 6; + aarch64_isa_flags = TARGET_CPU_DEFAULT >> TARGET_CPU_NBITS; } if (selected_tune) @@ -27260,6 +27261,9 @@ aarch64_run_selftests (void) { aarch64_test_loading_full_dump (); aarch64_test_fractional_cost (); + /* Check whether the TARGET_CPU_MASK is big enough to fit all of the definded + CPUs. */ + ASSERT_TRUE (TARGET_CPU_generic < TARGET_CPU_MASK); } } // namespace selftest