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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Apr 2022 05:25:22.9246 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ba0faf3b-90e2-444b-fdfb-08da178dd95f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.236];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT067.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW2PR12MB2377 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From tegra186 onwards, memory controller support multiple channels. Add support for mapping address spaces of these channels. Make sure that number of channels are as expected on each SOC. During error interrupts from memory controller, appropriate registers from these channels need to be accessed for logging error info. Signed-off-by: Ashish Mhetre --- drivers/memory/tegra/mc.c | 6 ++++ drivers/memory/tegra/tegra186.c | 54 +++++++++++++++++++++++++++++++++ drivers/memory/tegra/tegra194.c | 1 + drivers/memory/tegra/tegra234.c | 1 + include/soc/tegra/mc.h | 7 +++++ 5 files changed, 69 insertions(+) diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index bf3abb6d8354..3cda1d9ad32a 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -749,6 +749,12 @@ static int tegra_mc_probe(struct platform_device *pdev) if (IS_ERR(mc->regs)) return PTR_ERR(mc->regs); + if (mc->soc->ops && mc->soc->ops->map_regs) { + err = mc->soc->ops->map_regs(mc, pdev); + if (err < 0) + return err; + } + mc->debugfs.root = debugfs_create_dir("mc", NULL); if (mc->soc->ops && mc->soc->ops->probe) { diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c index 3d153881abc1..2ca8ce349188 100644 --- a/drivers/memory/tegra/tegra186.c +++ b/drivers/memory/tegra/tegra186.c @@ -139,11 +139,64 @@ static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev) return 0; } +static int tegra186_mc_map_regs(struct tegra_mc *mc, + struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.parent->of_node; + int num_dt_channels, reg_cells = 0; + int i, ret; + u32 val; + + ret = of_property_read_u32(np, "#address-cells", &val); + if (ret) { + dev_err(&pdev->dev, "missing #address-cells property\n"); + return ret; + } + + reg_cells = val; + + ret = of_property_read_u32(np, "#size-cells", &val); + if (ret) { + dev_err(&pdev->dev, "missing #size-cells property\n"); + return ret; + } + + reg_cells += val; + + num_dt_channels = of_property_count_elems_of_size(pdev->dev.of_node, "reg", + reg_cells * sizeof(u32)); + /* + * On tegra186 onwards, memory controller support multiple channels. + * Apart from regular memory controller channels, there is one broadcast + * channel and one for stream-id registers. + */ + if (num_dt_channels < mc->soc->num_channels + 2) { + dev_warn(&pdev->dev, "MC channels are missing, please update memory controller DT node with MC channels\n"); + return 0; + } + + mc->bcast_ch_regs = devm_platform_ioremap_resource_byname(pdev, "mc-broadcast"); + if (IS_ERR(mc->bcast_ch_regs)) + return PTR_ERR(mc->bcast_ch_regs); + + for (i = 0; i < mc->soc->num_channels; i++) { + char name[4]; + + sprintf(name, "mc%u", i); + mc->ch_regs[i] = devm_platform_ioremap_resource_byname(pdev, name); + if (IS_ERR(mc->ch_regs[i])) + return PTR_ERR(mc->ch_regs[i]); + } + + return 0; +} + const struct tegra_mc_ops tegra186_mc_ops = { .probe = tegra186_mc_probe, .remove = tegra186_mc_remove, .resume = tegra186_mc_resume, .probe_device = tegra186_mc_probe_device, + .map_regs = tegra186_mc_map_regs, }; #if defined(CONFIG_ARCH_TEGRA_186_SOC) @@ -875,6 +928,7 @@ const struct tegra_mc_soc tegra186_mc_soc = { .num_clients = ARRAY_SIZE(tegra186_mc_clients), .clients = tegra186_mc_clients, .num_address_bits = 40, + .num_channels = 4, .ops = &tegra186_mc_ops, }; #endif diff --git a/drivers/memory/tegra/tegra194.c b/drivers/memory/tegra/tegra194.c index cab998b8bd5c..94001174deaf 100644 --- a/drivers/memory/tegra/tegra194.c +++ b/drivers/memory/tegra/tegra194.c @@ -1347,5 +1347,6 @@ const struct tegra_mc_soc tegra194_mc_soc = { .num_clients = ARRAY_SIZE(tegra194_mc_clients), .clients = tegra194_mc_clients, .num_address_bits = 40, + .num_channels = 16, .ops = &tegra186_mc_ops, }; diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra234.c index e22824a79f45..6335a132be2d 100644 --- a/drivers/memory/tegra/tegra234.c +++ b/drivers/memory/tegra/tegra234.c @@ -97,5 +97,6 @@ const struct tegra_mc_soc tegra234_mc_soc = { .num_clients = ARRAY_SIZE(tegra234_mc_clients), .clients = tegra234_mc_clients, .num_address_bits = 40, + .num_channels = 16, .ops = &tegra186_mc_ops, }; diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index 1066b1194a5a..c3c121fbfbb7 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -13,6 +13,9 @@ #include #include #include +#include + +#define MC_MAX_CHANNELS 16 struct clk; struct device; @@ -181,6 +184,7 @@ struct tegra_mc_ops { int (*resume)(struct tegra_mc *mc); irqreturn_t (*handle_irq)(int irq, void *data); int (*probe_device)(struct tegra_mc *mc, struct device *dev); + int (*map_regs)(struct tegra_mc *mc, struct platform_device *pdev); }; struct tegra_mc_soc { @@ -194,6 +198,7 @@ struct tegra_mc_soc { unsigned int atom_size; u8 client_id_mask; + u8 num_channels; const struct tegra_smmu_soc *smmu; @@ -212,6 +217,8 @@ struct tegra_mc { struct tegra_smmu *smmu; struct gart_device *gart; void __iomem *regs; + void __iomem *bcast_ch_regs; + void __iomem *ch_regs[MC_MAX_CHANNELS]; struct clk *clk; int irq; From patchwork Wed Apr 6 05:24:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashish Mhetre X-Patchwork-Id: 1613806 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=t/hZMVoV; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4KYGVH1Vlxz9sCD for ; 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Tue, 5 Apr 2022 22:25:16 -0700 From: Ashish Mhetre To: , , , , , , , , CC: , , Ashish Mhetre Subject: [Patch v6 2/4] memory: tegra: Add MC error logging on tegra186 onward Date: Wed, 6 Apr 2022 10:54:57 +0530 Message-ID: <20220406052459.10438-3-amhetre@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220406052459.10438-1-amhetre@nvidia.com> References: <20220406052459.10438-1-amhetre@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 227ce230-11d1-4197-5596-08da178dd866 X-MS-TrafficTypeDiagnostic: MWHPR12MB1215:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: PFieehUKTFna0l4njagbYmNF6MZg5wQQXc3sZQu3yKvHZrPz6DUnq/4uHGAPoeCNpIe8voZR/YwWUFAMCOpybg8oxCua9M+i/2BSR9mnmzsxTxWV2TO1tBUuAjCDqt1Gj+1rvmTUQpbL8dFVmY+Kfhv0TGTh4IMD4c5YfdgVNSbkr6S8udn6cnpMGAd0XptneVe/kHjuIFPPkv1o0eBwHswlvXZoKiRtHrsosHeWx5eWXZ9QYL2P4+oM4tvZ+LvzXS0l5zaY9zdlLyGSFy2oeBPJRS4Eo7h5ljZMb7TixDX2xXjZwpWkOTHXJwX7KdIelbTsaz6ltSVsQ81d06xq4QB+xdkj/mh4SxbfMnJKBuzyAkN/W1bbd27qexR8S6LU8UGBno6ik+N2aUzh6jjM3LYn2QJMNEt7Z7tctPdemId57DBPEur/To1lDWkMMgoEjes2NGuiq2PjCsVWP8Z+TARdqn8QavcGphKGlOq6uNxGSHxmUft+55AfDPTDF78cvfRPyiqoGPgw+WkW9XqoYU7Ba/ls51ScHlORSvXHBysLB/Xo77U7gELZoX+CI49bYvIlMdzpOfYKBBQATIZO4J/68aVpuOGJYTlVVqUq0TmhMUSbAf6IgknrJpRJAFRwqilJPrUCr8ojzX807ojMf0PibZxzXveqFOwpkKjPDWWDIDeOYD1bQgG7qebEUpjfXAiE/zWk0VV7QvYZEOsBKg== X-Forefront-Antispam-Report: CIP:12.22.5.238;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230001)(4636009)(46966006)(36840700001)(40470700004)(336012)(426003)(86362001)(8936002)(4326008)(2906002)(26005)(47076005)(186003)(8676002)(36860700001)(36756003)(70206006)(70586007)(83380400001)(40460700003)(30864003)(82310400005)(110136005)(81166007)(54906003)(356005)(2616005)(316002)(7696005)(508600001)(5660300002)(1076003)(6666004)(107886003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Apr 2022 05:25:21.3196 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 227ce230-11d1-4197-5596-08da178dd866 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.238];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1215 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add support for reading MC_GLOBAL_INTSTATUS register which points to the memory controller channels on which interrupts have occurred. Add new function 'global_intstatus_to_channel' which returns the channel which should be used to get the information of interrupts. Remove static from tegra30_mc_handle_irq and use it as interrupt handler for MC interrupts on tegra186, tegra194 and tegra234 to log the errors. Add error specific MC status and address register bits and use them on tegra186, tegra194 and tegra234. Add error logging for generalized carveout interrupt on tegra186, tegra194 and tegra234. Add error logging for route sanity interrupt on tegra194 an tegra234. Add register for higher bits of error address which is available on tegra194 and tegra234. Add a boolean variable 'has_addr_hi_reg' in tegra_mc_soc struture which will be true if soc has register for higher bits of memory controller error address. Set it true for tegra194 and tegra234. Clear the global_intstatus bit corresponding to channel of which interrupts are logged. Signed-off-by: Ashish Mhetre --- drivers/memory/tegra/mc.c | 128 ++++++++++++++++++++++++++++---- drivers/memory/tegra/mc.h | 37 ++++++++- drivers/memory/tegra/tegra186.c | 9 +++ drivers/memory/tegra/tegra194.c | 8 ++ drivers/memory/tegra/tegra234.c | 7 ++ include/soc/tegra/mc.h | 3 + 6 files changed, 175 insertions(+), 17 deletions(-) diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index 3cda1d9ad32a..6f4e29d4bd33 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -508,14 +508,48 @@ int tegra30_mc_probe(struct tegra_mc *mc) return 0; } -static irqreturn_t tegra30_mc_handle_irq(int irq, void *data) +const struct tegra_mc_ops tegra30_mc_ops = { + .probe = tegra30_mc_probe, + .handle_irq = tegra30_mc_handle_irq, +}; +#endif + +static int global_intstatus_to_channel(const struct tegra_mc *mc, u32 status, + unsigned int *mc_channel) +{ + if ((status & mc->soc->ch_intmask) == 0) + return -EINVAL; + + *mc_channel = __ffs((status & mc->soc->ch_intmask) >> + mc->soc->status_reg_chan_shift); + + return 0; +} + +irqreturn_t tegra30_mc_handle_irq(int irq, void *data) { struct tegra_mc *mc = data; + unsigned int bit, channel; unsigned long status; - unsigned int bit; - /* mask all interrupts to avoid flooding */ - status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask; + if (mc->soc->num_channels) { + u32 global_status; + int err; + + global_status = mc_ch_readl(mc, MC_BROADCAST_CHANNEL, MC_GLOBAL_INTSTATUS); + err = global_intstatus_to_channel(mc, global_status, &channel); + if (err < 0) { + dev_err_ratelimited(mc->dev, "unknown interrupt channel 0x%08x\n", + global_status); + return IRQ_NONE; + } + + /* mask all interrupts to avoid flooding */ + status = mc_ch_readl(mc, channel, MC_INTSTATUS) & mc->soc->intmask; + } else { + status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask; + } + if (!status) return IRQ_NONE; @@ -523,18 +557,70 @@ static irqreturn_t tegra30_mc_handle_irq(int irq, void *data) const char *error = tegra_mc_status_names[bit] ?: "unknown"; const char *client = "unknown", *desc; const char *direction, *secure; + u32 status_reg, addr_reg; + u32 intmask = BIT(bit); phys_addr_t addr = 0; +#ifdef CONFIG_PHYS_ADDR_T_64BIT + u32 addr_hi_reg = 0; +#endif unsigned int i; char perm[7]; u8 id, type; u32 value; - value = mc_readl(mc, MC_ERR_STATUS); + switch (intmask) { + case MC_INT_DECERR_VPR: + status_reg = MC_ERR_VPR_STATUS; + addr_reg = MC_ERR_VPR_ADR; + break; + + case MC_INT_SECERR_SEC: + status_reg = MC_ERR_SEC_STATUS; + addr_reg = MC_ERR_SEC_ADR; + break; + + case MC_INT_DECERR_MTS: + status_reg = MC_ERR_MTS_STATUS; + addr_reg = MC_ERR_MTS_ADR; + break; + + case MC_INT_DECERR_GENERALIZED_CARVEOUT: + status_reg = MC_ERR_GENERALIZED_CARVEOUT_STATUS; + addr_reg = MC_ERR_GENERALIZED_CARVEOUT_ADR; + break; + + case MC_INT_DECERR_ROUTE_SANITY: + status_reg = MC_ERR_ROUTE_SANITY_STATUS; + addr_reg = MC_ERR_ROUTE_SANITY_ADR; + break; + + default: + status_reg = MC_ERR_STATUS; + addr_reg = MC_ERR_ADR; + +#ifdef CONFIG_PHYS_ADDR_T_64BIT + if (mc->soc->has_addr_hi_reg) + addr_hi_reg = MC_ERR_ADR_HI; +#endif + break; + } + + if (mc->soc->num_channels) + value = mc_ch_readl(mc, channel, status_reg); + else + value = mc_readl(mc, status_reg); #ifdef CONFIG_PHYS_ADDR_T_64BIT if (mc->soc->num_address_bits > 32) { - addr = ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) & - MC_ERR_STATUS_ADR_HI_MASK); + if (addr_hi_reg) { + if (mc->soc->num_channels) + addr = mc_ch_readl(mc, channel, addr_hi_reg); + else + addr = mc_readl(mc, addr_hi_reg); + } else { + addr = ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) & + MC_ERR_STATUS_ADR_HI_MASK); + } addr <<= 32; } #endif @@ -591,7 +677,10 @@ static irqreturn_t tegra30_mc_handle_irq(int irq, void *data) break; } - value = mc_readl(mc, MC_ERR_ADR); + if (mc->soc->num_channels) + value = mc_ch_readl(mc, channel, addr_reg); + else + value = mc_readl(mc, addr_reg); addr |= value; dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s%s)\n", @@ -600,17 +689,18 @@ static irqreturn_t tegra30_mc_handle_irq(int irq, void *data) } /* clear interrupts */ - mc_writel(mc, status, MC_INTSTATUS); + if (mc->soc->num_channels) { + u32 status_chan_bit; + + mc_ch_writel(mc, channel, status, MC_INTSTATUS); + status_chan_bit = BIT(channel) << mc->soc->status_reg_chan_shift; + mc_ch_writel(mc, MC_BROADCAST_CHANNEL, status_chan_bit, MC_GLOBAL_INTSTATUS); + } else + mc_writel(mc, status, MC_INTSTATUS); return IRQ_HANDLED; } -const struct tegra_mc_ops tegra30_mc_ops = { - .probe = tegra30_mc_probe, - .handle_irq = tegra30_mc_handle_irq, -}; -#endif - const char *const tegra_mc_status_names[32] = { [ 1] = "External interrupt", [ 6] = "EMEM address decode error", @@ -622,6 +712,8 @@ const char *const tegra_mc_status_names[32] = { [12] = "VPR violation", [13] = "Secure carveout violation", [16] = "MTS carveout violation", + [17] = "Generalized carveout violation", + [20] = "Route Sanity error", }; const char *const tegra_mc_error_names[8] = { @@ -770,7 +862,11 @@ static int tegra_mc_probe(struct platform_device *pdev) WARN(!mc->soc->client_id_mask, "missing client ID mask for this SoC\n"); - mc_writel(mc, mc->soc->intmask, MC_INTMASK); + if (mc->soc->num_channels && mc->bcast_ch_regs) + mc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->intmask, + MC_INTMASK); + else + mc_writel(mc, mc->soc->intmask, MC_INTMASK); err = devm_request_irq(&pdev->dev, mc->irq, mc->soc->ops->handle_irq, 0, dev_name(&pdev->dev), mc); diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h index 062886e94c04..77b3873e245c 100644 --- a/drivers/memory/tegra/mc.h +++ b/drivers/memory/tegra/mc.h @@ -43,7 +43,21 @@ #define MC_EMEM_ARB_OVERRIDE 0xe8 #define MC_TIMING_CONTROL_DBG 0xf8 #define MC_TIMING_CONTROL 0xfc - +#define MC_ERR_VPR_STATUS 0x654 +#define MC_ERR_VPR_ADR 0x658 +#define MC_ERR_SEC_STATUS 0x67c +#define MC_ERR_SEC_ADR 0x680 +#define MC_ERR_MTS_STATUS 0x9b0 +#define MC_ERR_MTS_ADR 0x9b4 +#define MC_ERR_ROUTE_SANITY_STATUS 0x9c0 +#define MC_ERR_ROUTE_SANITY_ADR 0x9c4 +#define MC_ERR_GENERALIZED_CARVEOUT_STATUS 0xc00 +#define MC_ERR_GENERALIZED_CARVEOUT_ADR 0xc04 +#define MC_GLOBAL_INTSTATUS 0xf24 +#define MC_ERR_ADR_HI 0x11fc + +#define MC_INT_DECERR_ROUTE_SANITY BIT(20) +#define MC_INT_DECERR_GENERALIZED_CARVEOUT BIT(17) #define MC_INT_DECERR_MTS BIT(16) #define MC_INT_SECERR_SEC BIT(13) #define MC_INT_DECERR_VPR BIT(12) @@ -78,6 +92,8 @@ #define MC_TIMING_UPDATE BIT(0) +#define MC_BROADCAST_CHANNEL ~0 + static inline u32 tegra_mc_scale_percents(u64 val, unsigned int percents) { val = val * percents; @@ -92,6 +108,24 @@ icc_provider_to_tegra_mc(struct icc_provider *provider) return container_of(provider, struct tegra_mc, provider); } +static inline u32 mc_ch_readl(const struct tegra_mc *mc, int ch, + unsigned long offset) +{ + if (ch == MC_BROADCAST_CHANNEL) + return readl_relaxed(mc->bcast_ch_regs + offset); + + return readl_relaxed(mc->ch_regs[ch] + offset); +} + +static inline void mc_ch_writel(const struct tegra_mc *mc, int ch, + u32 value, unsigned long offset) +{ + if (ch == MC_BROADCAST_CHANNEL) + writel_relaxed(value, mc->bcast_ch_regs + offset); + else + writel_relaxed(value, mc->ch_regs[ch] + offset); +} + static inline u32 mc_readl(const struct tegra_mc *mc, unsigned long offset) { return readl_relaxed(mc->regs + offset); @@ -156,6 +190,7 @@ extern const struct tegra_mc_ops tegra30_mc_ops; extern const struct tegra_mc_ops tegra186_mc_ops; #endif +irqreturn_t tegra30_mc_handle_irq(int irq, void *data); extern const char * const tegra_mc_status_names[32]; extern const char * const tegra_mc_error_names[8]; diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c index 2ca8ce349188..bb2cc405eb20 100644 --- a/drivers/memory/tegra/tegra186.c +++ b/drivers/memory/tegra/tegra186.c @@ -16,6 +16,8 @@ #include #endif +#include "mc.h" + #define MC_SID_STREAMID_OVERRIDE_MASK GENMASK(7, 0) #define MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED BIT(16) #define MC_SID_STREAMID_SECURITY_OVERRIDE BIT(8) @@ -197,6 +199,7 @@ const struct tegra_mc_ops tegra186_mc_ops = { .resume = tegra186_mc_resume, .probe_device = tegra186_mc_probe_device, .map_regs = tegra186_mc_map_regs, + .handle_irq = tegra30_mc_handle_irq, }; #if defined(CONFIG_ARCH_TEGRA_186_SOC) @@ -929,6 +932,12 @@ const struct tegra_mc_soc tegra186_mc_soc = { .clients = tegra186_mc_clients, .num_address_bits = 40, .num_channels = 4, + .client_id_mask = 0xff, + .intmask = MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS | + MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | + MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, .ops = &tegra186_mc_ops, + .ch_intmask = 0x0000000f, + .status_reg_chan_shift = 0, }; #endif diff --git a/drivers/memory/tegra/tegra194.c b/drivers/memory/tegra/tegra194.c index 94001174deaf..963d6085a247 100644 --- a/drivers/memory/tegra/tegra194.c +++ b/drivers/memory/tegra/tegra194.c @@ -1348,5 +1348,13 @@ const struct tegra_mc_soc tegra194_mc_soc = { .clients = tegra194_mc_clients, .num_address_bits = 40, .num_channels = 16, + .client_id_mask = 0xff, + .intmask = MC_INT_DECERR_ROUTE_SANITY | + MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS | + MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | + MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, + .has_addr_hi_reg = true, .ops = &tegra186_mc_ops, + .ch_intmask = 0x00000f00, + .status_reg_chan_shift = 8, }; diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra234.c index 6335a132be2d..44884fb78b5c 100644 --- a/drivers/memory/tegra/tegra234.c +++ b/drivers/memory/tegra/tegra234.c @@ -98,5 +98,12 @@ const struct tegra_mc_soc tegra234_mc_soc = { .clients = tegra234_mc_clients, .num_address_bits = 40, .num_channels = 16, + .intmask = MC_INT_DECERR_ROUTE_SANITY | + MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS | + MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | + MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, + .has_addr_hi_reg = true, .ops = &tegra186_mc_ops, + .ch_intmask = 0x0000ff00, + .status_reg_chan_shift = 8, }; diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index c3c121fbfbb7..284ad5988d10 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -203,6 +203,9 @@ struct tegra_mc_soc { const struct tegra_smmu_soc *smmu; u32 intmask; + u32 ch_intmask; + u32 status_reg_chan_shift; + bool has_addr_hi_reg; const struct tegra_mc_reset_ops *reset_ops; const struct tegra_mc_reset *resets; From patchwork Wed Apr 6 05:24:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashish Mhetre X-Patchwork-Id: 1613803 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=K912k3R/; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; 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Tue, 5 Apr 2022 22:25:21 -0700 From: Ashish Mhetre To: , , , , , , , , CC: , , Ashish Mhetre Subject: [Patch v6 3/4] dt-bindings: memory: Update reg maxitems for tegra186 Date: Wed, 6 Apr 2022 10:54:58 +0530 Message-ID: <20220406052459.10438-4-amhetre@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220406052459.10438-1-amhetre@nvidia.com> References: <20220406052459.10438-1-amhetre@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a91603c5-a2dc-47d7-778c-08da178ddba4 X-MS-TrafficTypeDiagnostic: CH2PR12MB4056:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: sWDaEF0waY3n85E2Emis3DU1rkymGdPjOZjCm1hEJ5HifR9/pY9aDaINEseMiu2KA4FzB8Jl5jWAwH/hAG982iJH5R09fkZ8uHVYYKAi7CNwE68w3pez9zw9AAO/x/4VSSyCj5UPi1eBIeBS3mXviNSbpe+iAsXDRJ4ZCOw4L54J5y9YnuSF+C0pXgGAPLU0KRc3SoyEio36WdO3W5KPjOAyMObogJdVqn9TbXo0UWhXH0mmo4KOOkYEbmEIJnoojKLDvIGJX1rZhkuAf+Z7ehO6FCrj12JerorQ2FOZpmlZZT8skgI0U3axbRjMLpQGmfA62tX0qAtLZePRY4c2ADEclLOCWlYFb3SGyhrwiEwER5zctxHy4de9U/gQhARg9Xq7f8uilwNUEZQjaJsxKa/sFwgwzNeEGJhJQnpzGSyYxraIxGpcmVAVMg5WtWjUiQzqG9uyiqkNS19mrwS6xsYxi2FeseNavrSqfGJGeAEJL79jEjtjZZOGHAt7gsbLHkQN+vFuCA2e2SIT+/7QA5vkt/MYBV3AWpoBIgaIGpUjikrmMTxzzNmUinXQHp3CrPWfjs8uhlAexVaO6yYP65sM5sMwovyQF/aoX2YJTI1H+rUIziZCy9WDtAjVFi1CfDlm/z7s5LOFfBknvvT4nq0sPOUxvcUE4Fh+kFrCpBd5AhX7AF2jTuHWBcLQiq97e6mBHF0hXoavWtwnrykoXw== X-Forefront-Antispam-Report: CIP:12.22.5.234;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230001)(4636009)(36840700001)(40470700004)(46966006)(36860700001)(336012)(356005)(40460700003)(86362001)(4326008)(8676002)(6666004)(7696005)(47076005)(426003)(2906002)(508600001)(15650500001)(81166007)(316002)(5660300002)(82310400005)(83380400001)(2616005)(54906003)(107886003)(70206006)(26005)(70586007)(1076003)(186003)(110136005)(8936002)(36756003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Apr 2022 05:25:26.8069 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a91603c5-a2dc-47d7-778c-08da178ddba4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.234];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT038.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4056 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From tegra186 onwards, memory controller support multiple channels. Reg items are updated with address and size of these channels. Tegra186 has overall 5 memory controller channels. Tegra194 and tegra234 have overall 17 memory controller channels each. There is 1 reg item for memory controller stream-id registers. So update the reg maxItems to 18 in tegra186 devicetree documentation. Signed-off-by: Ashish Mhetre --- .../memory-controllers/nvidia,tegra186-mc.yaml | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml index 13c4c82fd0d3..0fe396a2e162 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml @@ -35,7 +35,7 @@ properties: reg: minItems: 1 - maxItems: 3 + maxItems: 18 interrupts: items: @@ -142,7 +142,8 @@ allOf: then: properties: reg: - maxItems: 1 + maxItems: 6 + description: 5 memory controller channels and 1 for stream-id registers - if: properties: @@ -152,6 +153,7 @@ allOf: properties: reg: minItems: 3 + description: 17 memory controller channels and 1 for stream-id registers - if: properties: @@ -161,6 +163,7 @@ allOf: properties: reg: minItems: 3 + description: 17 memory controller channels and 1 for stream-id registers additionalProperties: false @@ -182,7 +185,13 @@ examples: memory-controller@2c00000 { compatible = "nvidia,tegra186-mc"; - reg = <0x0 0x02c00000 0x0 0xb0000>; + reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ + <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */ + <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ + <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ + <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ + <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ + reg-names = "mc-sid", "mc-broadcast", "mc0", "mc1", "mc2", "mc3"; interrupts = ; #address-cells = <2>; From patchwork Wed Apr 6 05:24:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashish Mhetre X-Patchwork-Id: 1613805 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=I/zoqlxE; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; 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Tue, 5 Apr 2022 22:25:27 -0700 From: Ashish Mhetre To: , , , , , , , , CC: , , Ashish Mhetre Subject: [Patch v6 4/4] arm64: tegra: Add memory controller channels Date: Wed, 6 Apr 2022 10:54:59 +0530 Message-ID: <20220406052459.10438-5-amhetre@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220406052459.10438-1-amhetre@nvidia.com> References: <20220406052459.10438-1-amhetre@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4ce56de8-bfc9-4473-c2e3-08da178ddec3 X-MS-TrafficTypeDiagnostic: SN6PR12MB2638:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: mw7kgCc46+PZcpF1z6lqoHGUGuw0sxNbomf41WovYPuBaOW0rhzH/j87KE76S8x8GEdmnf8hfvbYMCHwxDgEyFSXDCr8DuKxjWuUpl9+sMoWVh4v66Wy4Hb0gc6IWbWODXbjd/sSeDPBdKhAdYn9lbnMf8m33hDqlr0i0jk92aXYa4HbwBpSlEOU56RhXB0DdOLuYPV6QLuvpzCbWcZUN6/YO2jrmFLohU9AEknBqAyiyna/F4tvwiJiNgCzOfhVvEZuuhIWBMYUdjEQaSg4EvSzCYOT/DbGUFNBa9mLUhErl7TBjjZ9hHnGo4Kj69RZK21rX8ZTUsYPaBbVYVUDxVnkFOMvJOTUp4W2hueF0Qm9MHqE5NvXEdiDmgcrQJMDv+Teb2HOG2kuM6c2bzOp/TALnd2YbTYApoo9MrOgZVm6pUMXtq7zYxXv6Y+O8tiMzzmpN0/MZGdHhr/Wf2Uf3AcB2PzvFIEe0bASFeWdS8q2rK3N/Ksop0U13yfPVM2nROaUThltc0d04jnkClISNqnajdMSD9UBQEgENG4llHZTzGYRqTXVpHq5T4eYhzGDfXEpZH/4de+xwnj9zHnjPJAPPJT6lkRD2k01xsBS3tzGsss3HPw9VY4MqC4vGcpJVacwg3jAeMtnsvy2b/UJW7mTbNfV1D8YFDL3UNAFDO9rVtexmYD6XN27vAeNsbfrKXx76hHTY24d2FHSMcWjfg== X-Forefront-Antispam-Report: CIP:12.22.5.236;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230001)(4636009)(46966006)(40470700004)(36840700001)(7696005)(4326008)(8676002)(36860700001)(36756003)(6666004)(86362001)(110136005)(2906002)(508600001)(54906003)(316002)(107886003)(336012)(5660300002)(1076003)(2616005)(82310400005)(70586007)(356005)(426003)(47076005)(40460700003)(186003)(70206006)(26005)(83380400001)(8936002)(81166007)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Apr 2022 05:25:31.9670 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4ce56de8-bfc9-4473-c2e3-08da178ddec3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.236];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT028.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2638 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From tegra186 onwards, memory controller support multiple channels. During the error interrupts from memory controller, corresponding channels need to be accessed for logging error info and clearing the interrupt. So add address and size of these channels in device tree node of tegra186, tegra194 and tegra234 memory controller. Also add reg-names for each of these reg items which are used by driver for mapping. Signed-off-by: Ashish Mhetre --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 8 +++++++- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 24 +++++++++++++++++++++--- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 24 +++++++++++++++++++++--- 3 files changed, 49 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index e9b40f5d79ec..e4499db46339 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -521,7 +521,13 @@ mc: memory-controller@2c00000 { compatible = "nvidia,tegra186-mc"; - reg = <0x0 0x02c00000 0x0 0xb0000>; + reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ + <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */ + <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ + <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ + <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ + <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ + reg-names = "mc-sid", "mc-broadcast", "mc0", "mc1", "mc2", "mc3"; interrupts = ; status = "disabled"; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 751ebe5e9506..88a1a5e426ff 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -604,9 +604,27 @@ mc: memory-controller@2c00000 { compatible = "nvidia,tegra194-mc"; - reg = <0x02c00000 0x100000>, - <0x02b80000 0x040000>, - <0x01700000 0x100000>; + reg = <0x02c00000 0x10000>, /* MC-SID */ + <0x02c10000 0x10000>, /* MC Broadcast*/ + <0x02c20000 0x10000>, /* MC0 */ + <0x02c30000 0x10000>, /* MC1 */ + <0x02c40000 0x10000>, /* MC2 */ + <0x02c50000 0x10000>, /* MC3 */ + <0x02b80000 0x10000>, /* MC4 */ + <0x02b90000 0x10000>, /* MC5 */ + <0x02ba0000 0x10000>, /* MC6 */ + <0x02bb0000 0x10000>, /* MC7 */ + <0x01700000 0x10000>, /* MC8 */ + <0x01710000 0x10000>, /* MC9 */ + <0x01720000 0x10000>, /* MC10 */ + <0x01730000 0x10000>, /* MC11 */ + <0x01740000 0x10000>, /* MC12 */ + <0x01750000 0x10000>, /* MC13 */ + <0x01760000 0x10000>, /* MC14 */ + <0x01770000 0x10000>; /* MC15 */ + reg-names = "mc-sid", "mc-broadcast", "mc0", "mc1", "mc2", "mc3", + "mc4", "mc5", "mc6", "mc7", "mc8", "mc9", "mc10", + "mc11", "mc12", "mc13", "mc14", "mc15"; interrupts = ; #interconnect-cells = <1>; status = "disabled"; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index aaace605bdaa..216a079ba569 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -507,9 +507,27 @@ mc: memory-controller@2c00000 { compatible = "nvidia,tegra234-mc"; - reg = <0x02c00000 0x100000>, - <0x02b80000 0x040000>, - <0x01700000 0x100000>; + reg = <0x02c00000 0x10000>, /* MC-SID */ + <0x02c10000 0x10000>, /* MC Broadcast*/ + <0x02c20000 0x10000>, /* MC0 */ + <0x02c30000 0x10000>, /* MC1 */ + <0x02c40000 0x10000>, /* MC2 */ + <0x02c50000 0x10000>, /* MC3 */ + <0x02b80000 0x10000>, /* MC4 */ + <0x02b90000 0x10000>, /* MC5 */ + <0x02ba0000 0x10000>, /* MC6 */ + <0x02bb0000 0x10000>, /* MC7 */ + <0x01700000 0x10000>, /* MC8 */ + <0x01710000 0x10000>, /* MC9 */ + <0x01720000 0x10000>, /* MC10 */ + <0x01730000 0x10000>, /* MC11 */ + <0x01740000 0x10000>, /* MC12 */ + <0x01750000 0x10000>, /* MC13 */ + <0x01760000 0x10000>, /* MC14 */ + <0x01770000 0x10000>; /* MC15 */ + reg-names = "mc-sid", "mc-broadcast", "mc0", "mc1", "mc2", "mc3", + "mc4", "mc5", "mc6", "mc7", "mc8", "mc9", "mc10", + "mc11", "mc12", "mc13", "mc14", "mc15"; interrupts = ; #interconnect-cells = <1>; status = "okay";