From patchwork Tue Aug 29 03:41:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Meissner X-Patchwork-Id: 806927 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-461058-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="Xq5Qs2rL"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xhDwS66dBz9s7h for ; Tue, 29 Aug 2017 13:42:14 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:mime-version:content-type:message-id; q=dns; s= default; b=x0bXIheXqW+b1LTShVZkQeAQdRHffmNzdudny04UMs2LUsMgAdE27 S9DFCule6QwtSABDiur9jdon1XzyMQUf2M9F13mmnyPG9x4IMjNGGZw7gadhKK47 vrDm5xeXS4oPeBgE1LgO2svNnN8qFc+dgPrgFDkARWKt2G2G+QJkhI= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:mime-version:content-type:message-id; s= default; bh=TQAEXFsI6K617gSg4K9j3UNBqvc=; b=Xq5Qs2rL4wOF2IWZMgo3 EO73mlBXfupuu0AH67oip5ZOqfcL5swRBuUFqerwEL0/ywECseiqOZHwpOylNlXc Kdf6Zlmtka0bIB4GmmeItcphqGIKDCtSNSKjFusAPZGFbHvA9kNIDgYXuFtIWn+b mAZfMcjr+1kQCWSazGSA2g4= Received: (qmail 90795 invoked by alias); 29 Aug 2017 03:42:05 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 90769 invoked by uid 89); 29 Aug 2017 03:42:04 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-9.9 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, KAM_LAZY_DOMAIN_SECURITY, RCVD_IN_DNSWL_LOW autolearn=ham version=3.3.2 spammy=dd, oi X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0a-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.156.1) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 29 Aug 2017 03:41:54 +0000 Received: from pps.filterd (m0098396.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v7T3fiip141805 for ; Mon, 28 Aug 2017 23:41:52 -0400 Received: from e34.co.us.ibm.com (e34.co.us.ibm.com [32.97.110.152]) by mx0a-001b2d01.pphosted.com with ESMTP id 2cmvjevsdy-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Mon, 28 Aug 2017 23:41:51 -0400 Received: from localhost by e34.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Mon, 28 Aug 2017 21:41:49 -0600 Received: from b03ledav001.gho.boulder.ibm.com (b03ledav001.gho.boulder.ibm.com [9.17.130.232]) by b03cxnp08027.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v7T3fnfI65273948; Mon, 28 Aug 2017 20:41:49 -0700 Received: from b03ledav001.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id F32FC6E035; Mon, 28 Aug 2017 21:41:48 -0600 (MDT) Received: from ibm-tiger.the-meissners.org (unknown [9.32.77.111]) by b03ledav001.gho.boulder.ibm.com (Postfix) with ESMTP id C20346E03F; Mon, 28 Aug 2017 21:41:48 -0600 (MDT) Received: by ibm-tiger.the-meissners.org (Postfix, from userid 500) id EC5CF4775E; Mon, 28 Aug 2017 23:41:47 -0400 (EDT) Date: Mon, 28 Aug 2017 23:41:47 -0400 From: Michael Meissner To: GCC Patches , Segher Boessenkool , David Edelsohn , Bill Schmidt Subject: [PATCH], PR target/82015, add PowerPC warning for unpack_vector_int128 with illegal 2nd argument Mail-Followup-To: Michael Meissner , GCC Patches , Segher Boessenkool , David Edelsohn , Bill Schmidt MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.20 (2009-12-10) X-TM-AS-GCONF: 00 x-cbid: 17082903-0016-0000-0000-0000076F0B4D X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00007630; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000226; SDB=6.00909096; UDB=6.00455890; IPR=6.00689347; BA=6.00005557; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00016912; XFM=3.00000015; UTC=2017-08-29 03:41:51 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17082903-0017-0000-0000-00003B3F882B Message-Id: <20170829034147.GA15563@ibm-tiger.the-meissners.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-08-28_13:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000 definitions=main-1708290053 X-IsSubscribed: yes One of the local programmers tried to use the __builtin_unpack_vector_int128 function, but his second argument was not the constant 0 or 1. The compiler put the 2nd argument into a register, but there wasn't a valid insn for this, and raised an insn not found message. GCC should warn about this illegal usage. This patch adds such a warning. While I was mucking about with this built-in function, I fixed the constraints to allow the 64-bit integer for unpack result and pack inputs to be in the traditional Altivec registers as well as the traditional floating point registers. I did a bootstrap of the compiler, and there were no regressions on a little endian power8 system. I verified that the new test is run. Can I apply this patch to the trunk? Can I apply the part of the patch from rs6000.c to the existing GCC 6/7 branches as well after a shake down period? The patch to rs6000.md is not appropriate for GCC 6 (since DImode can't go into Altivec registers). For GCC 7, it would need to be modified to use the 'wi' constraint instead of 'wa', since GCC 7 still had support for the -mno-upper-regs-di option to control access to the traditional Altivec register. [gcc] 2017-08-28 Michael Meissner PR target/82015 * config/rs6000/rs6000.c (rs6000_expand_binop_builtin): Insure that the second argument of the built-in functions to unpack 128-bit scalar types to 64-bit values is 0 or 1. Change to use a switch statement instead a lot of if statements. * config/rs6000/rs6000.md (unpack, FMOVE128_VSX iterator): Allow 64-bit values to be in Altivec registers as well as traditional floating point registers. (pack, FMOVE128_VSX iterator): Likewise. [gcc/testsuite] 2017-08-28 Michael Meissner PR target/82015 * gcc.target/powerpc/pr82015.c: New test. Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c (revision 251390) +++ gcc/config/rs6000/rs6000.c (working copy) @@ -14001,14 +14001,17 @@ rs6000_expand_binop_builtin (enum insn_c if (arg0 == error_mark_node || arg1 == error_mark_node) return const0_rtx; - if (icode == CODE_FOR_altivec_vcfux - || icode == CODE_FOR_altivec_vcfsx - || icode == CODE_FOR_altivec_vctsxs - || icode == CODE_FOR_altivec_vctuxs - || icode == CODE_FOR_altivec_vspltb - || icode == CODE_FOR_altivec_vsplth - || icode == CODE_FOR_altivec_vspltw) + switch (icode) { + default: + break; + case CODE_FOR_altivec_vcfux: + case CODE_FOR_altivec_vcfsx: + case CODE_FOR_altivec_vctsxs: + case CODE_FOR_altivec_vctuxs: + case CODE_FOR_altivec_vspltb: + case CODE_FOR_altivec_vsplth: + case CODE_FOR_altivec_vspltw: /* Only allow 5-bit unsigned literals. */ STRIP_NOPS (arg1); if (TREE_CODE (arg1) != INTEGER_CST @@ -14017,16 +14020,15 @@ rs6000_expand_binop_builtin (enum insn_c error ("argument 2 must be a 5-bit unsigned literal"); return CONST0_RTX (tmode); } - } - else if (icode == CODE_FOR_dfptstsfi_eq_dd - || icode == CODE_FOR_dfptstsfi_lt_dd - || icode == CODE_FOR_dfptstsfi_gt_dd - || icode == CODE_FOR_dfptstsfi_unordered_dd - || icode == CODE_FOR_dfptstsfi_eq_td - || icode == CODE_FOR_dfptstsfi_lt_td - || icode == CODE_FOR_dfptstsfi_gt_td - || icode == CODE_FOR_dfptstsfi_unordered_td) - { + break; + case CODE_FOR_dfptstsfi_eq_dd: + case CODE_FOR_dfptstsfi_lt_dd: + case CODE_FOR_dfptstsfi_gt_dd: + case CODE_FOR_dfptstsfi_unordered_dd: + case CODE_FOR_dfptstsfi_eq_td: + case CODE_FOR_dfptstsfi_lt_td: + case CODE_FOR_dfptstsfi_gt_td: + case CODE_FOR_dfptstsfi_unordered_td: /* Only allow 6-bit unsigned literals. */ STRIP_NOPS (arg0); if (TREE_CODE (arg0) != INTEGER_CST @@ -14035,13 +14037,12 @@ rs6000_expand_binop_builtin (enum insn_c error ("argument 1 must be a 6-bit unsigned literal"); return CONST0_RTX (tmode); } - } - else if (icode == CODE_FOR_xststdcqp - || icode == CODE_FOR_xststdcdp - || icode == CODE_FOR_xststdcsp - || icode == CODE_FOR_xvtstdcdp - || icode == CODE_FOR_xvtstdcsp) - { + break; + case CODE_FOR_xststdcqp: + case CODE_FOR_xststdcdp: + case CODE_FOR_xststdcsp: + case CODE_FOR_xvtstdcdp: + case CODE_FOR_xvtstdcsp: /* Only allow 7-bit unsigned literals. */ STRIP_NOPS (arg1); if (TREE_CODE (arg1) != INTEGER_CST @@ -14050,6 +14051,21 @@ rs6000_expand_binop_builtin (enum insn_c error ("argument 2 must be a 7-bit unsigned literal"); return CONST0_RTX (tmode); } + break; + case CODE_FOR_unpackv1ti: + case CODE_FOR_unpackkf: + case CODE_FOR_unpacktf: + case CODE_FOR_unpackif: + case CODE_FOR_unpacktd: + /* Only allow 1-bit unsigned literals. */ + STRIP_NOPS (arg1); + if (TREE_CODE (arg1) != INTEGER_CST + || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 1)) + { + error ("argument 2 must be 0 or 1"); + return CONST0_RTX (tmode); + } + break; } if (target == 0 Index: gcc/config/rs6000/rs6000.md =================================================================== --- gcc/config/rs6000/rs6000.md (revision 251390) +++ gcc/config/rs6000/rs6000.md (working copy) @@ -14165,7 +14165,7 @@ (define_insn_and_split "pack" (set_attr "length" "4,8")]) (define_insn "unpack" - [(set (match_operand:DI 0 "register_operand" "=d,d") + [(set (match_operand:DI 0 "register_operand" "=wa,wa") (unspec:DI [(match_operand:FMOVE128_VSX 1 "register_operand" "0,wa") (match_operand:QI 2 "const_0_to_1_operand" "O,i")] UNSPEC_UNPACK_128BIT))] @@ -14182,8 +14182,8 @@ (define_insn "unpack" (define_insn "pack" [(set (match_operand:FMOVE128_VSX 0 "register_operand" "=wa") (unspec:FMOVE128_VSX - [(match_operand:DI 1 "register_operand" "d") - (match_operand:DI 2 "register_operand" "d")] + [(match_operand:DI 1 "register_operand" "wa") + (match_operand:DI 2 "register_operand" "wa")] UNSPEC_PACK_128BIT))] "TARGET_VSX" "xxpermdi %x0,%x1,%x2,0" Index: gcc/testsuite/gcc.target/powerpc/pr82015.c =================================================================== --- gcc/testsuite/gcc.target/powerpc/pr82015.c (revision 0) +++ gcc/testsuite/gcc.target/powerpc/pr82015.c (revision 0) @@ -0,0 +1,14 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mvsx" } */ + +unsigned long foo_11(vector __int128_t *p) +{ + return __builtin_unpack_vector_int128(*p, 11); /* { dg-error "argument 2 must be 0 or 1" } */ +} + +unsigned long foo_n(vector __int128_t *p, unsigned long n) +{ + return __builtin_unpack_vector_int128(*p, n); /* { dg-error "argument 2 must be 0 or 1" } */ +}