From patchwork Mon Feb 19 06:54:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 874987 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="A2BUAHVN"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zlDzG20vHz9s0r for ; Mon, 19 Feb 2018 17:55:38 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751744AbeBSGy6 (ORCPT ); Mon, 19 Feb 2018 01:54:58 -0500 Received: from mail-pg0-f65.google.com ([74.125.83.65]:36550 "EHLO mail-pg0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751687AbeBSGy5 (ORCPT ); Mon, 19 Feb 2018 01:54:57 -0500 Received: by mail-pg0-f65.google.com with SMTP id j9so5553715pgv.3; Sun, 18 Feb 2018 22:54:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=Bwa5CEwANlUgy3oJb2jE2a4Wi6ShJyK/drXZOJfukro=; b=A2BUAHVN0ccWiQ/5lw9drMyGeUO72ZjKoSzhHN242HEmIEHrXH0NKH6G79+1HPKQKt /VsmZVOtl1VPCCreBSoBe2O5OeVQNP4QiseMHKqL2mLcO+JFRyCE4b43WoiYHvYwg61y l62qPp/p2zZ9AgTnGxX3Q0pOQeD2747iV5GDTCjo07xzLy/tNuZkHX9QD5LG9EH3BPDI ySxHvEBQTQ9wOVP6oOZ0oeIcLMLEUh8+puslVpLockGIfWfL3hfLN/XT9nT6GW/mMelV HMvzlBHXX5Cn7jo728jVCosak/TH8lLdZWDnMA3FTnhi2kPUR0jTI6nHsUrNaDESf+VW YCeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=Bwa5CEwANlUgy3oJb2jE2a4Wi6ShJyK/drXZOJfukro=; b=JwmW3tNvXgiJ5teY1UES42/XvlFArJ+yFhi1sazEPYd3mdSba3CXZke0DSBD192HnB SuBatgcDzbtMw+mK5VsLTO3mc5FEAHzMr6sZDT2ac71EHhmk8fZN5Xvs4uKSS6W4T3yr Tbap/QqrJxImeuwnDjeXnNsSqlD1c2ViR4w+QFm0tMad/DiJuwNXToUvq0DkupWei7fb ZAOaf5BmAv+jpJV1X4msI+3nIVUrI/Q5i1yedBxlB3ESVy6+UAdb2XrDGqERfung1O4i I20ed42GuU1t5TDAlc/vW37Yf8hFsoGvrswPqDNyf1ZdmDx3iRp2LohAZstVqC+jFKTx uzmg== X-Gm-Message-State: APf1xPD59mamaHFd3hOogBMuH61lBowL+JiZttS2SWCCWmKfVuASUCN3 WOfV7cE2MfZP9IYJTcywDzU= X-Google-Smtp-Source: AH8x226/vuUaSMKP0B/RQ/FJYDZbJ1Y9oGfkHaSIQ3CvDNfKJwn8zWzzLxDVjedwJjDwwla2/SceIw== X-Received: by 10.98.103.136 with SMTP id t8mr8760994pfj.177.1519023296359; Sun, 18 Feb 2018 22:54:56 -0800 (PST) Received: from aurora.jms.id.au ([45.124.203.19]) by smtp.gmail.com with ESMTPSA id l189sm3973807pfl.48.2018.02.18.22.54.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 18 Feb 2018 22:54:55 -0800 (PST) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Mon, 19 Feb 2018 17:24:48 +1030 From: Joel Stanley To: Rob Herring , Mark Rutland , Philipp Zabel , Andrew Jeffery Cc: Lee Jones , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-aspeed@lists.ozlabs.org Subject: [PATCH 1/3] dt-bindings: aspeed-lpc: Add reset controller Date: Mon, 19 Feb 2018 17:24:36 +1030 Message-Id: <20180219065438.19933-2-joel@jms.id.au> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180219065438.19933-1-joel@jms.id.au> References: <20180219065438.19933-1-joel@jms.id.au> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This describes the reset controller present in the LPC address space. Signed-off-by: Joel Stanley Reviewed-by: Rob Herring --- .../devicetree/bindings/mfd/aspeed-lpc.txt | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt index 514d82ced95b..721a2b1eb40f 100644 --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt @@ -135,3 +135,24 @@ lhc: lhc@20 { compatible = "aspeed,ast2500-lhc"; reg = <0x20 0x24 0x48 0x8>; }; + +LPC reset control +----------------- + +The UARTs present in the ASPEED SoC can have their resets tied to the reset +state of the LPC bus. Some systems may chose to modify this configuration. + +Required properties: + + - comaptible: "aspeed,ast2500-lpc-reset" or + "aspeed,ast2400-lpc-reset" + - reg: offset and length of the IP in the LHC memory region + - #reset-controller indacates the number of reset cells excepted + +Example: + +lpc_reset: reset-controller@18 { + compatible = "aspeed,ast2500-lpc-reset"; + reg = <0x18 0x4>; + #reset-cells = <1>; +};