From patchwork Wed Mar 16 08:17:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: liuhongt X-Patchwork-Id: 1606042 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=p5KiBaUu; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4KJNSw5kV8z9sCq for ; Wed, 16 Mar 2022 19:18:23 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5A756385ED4A for ; Wed, 16 Mar 2022 08:18:21 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5A756385ED4A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1647418701; bh=pfepWS1KmMH7ThGjRGuamoFmSQZXHqlBRsdXDNpD6pQ=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=p5KiBaUuKj9r3pGsj3oYacbQ8yvCgCV5TuuSH/DXTeew6cx/FAEJ6wUC0pfqh9YRb oq/X55xhCUwtjJ/K6yeV5CeDCEzONnGOJGvJkNnf2vYtejReMAsf3xpVztwe0Zz0vp LvxWI5MqX3ThePF67ZSnmMKF5447Wgp4ebBXTOEM= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by sourceware.org (Postfix) with ESMTPS id 3F6AE385E83F for ; Wed, 16 Mar 2022 08:17:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 3F6AE385E83F X-IronPort-AV: E=McAfee;i="6200,9189,10286"; a="237129433" X-IronPort-AV: E=Sophos;i="5.90,186,1643702400"; d="scan'208";a="237129433" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Mar 2022 01:17:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,186,1643702400"; d="scan'208";a="516236691" Received: from scymds02.sc.intel.com ([10.82.73.244]) by orsmga006.jf.intel.com with ESMTP; 16 Mar 2022 01:17:36 -0700 Received: from shliclel051.sh.intel.com (shliclel051.sh.intel.com [10.239.236.51]) by scymds02.sc.intel.com with ESMTP id 22G8HZsi020523; Wed, 16 Mar 2022 01:17:35 -0700 To: gcc-patches@gcc.gnu.org Subject: [PATCH] [i386] Don't fold __builtin_ia32_blendvpd w/o sse4.2. Date: Wed, 16 Mar 2022 16:17:34 +0800 Message-Id: <20220316081734.68900-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.18.1 X-Spam-Status: No, score=-13.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: liuhongt via Gcc-patches From: liuhongt Reply-To: liuhongt Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" __builtin_ia32_blendvpd is defined under sse4.1 and gimple folded to ((v2di) c) < 0 ? b : a where vec_cmpv2di is under sse4.2 w/o which it's veclowered to scalar operations and not combined back in rtl. Bootstrap and regtest on x86_64-pc-linux-gnu{-m32,}. Ready push to main trunk. gcc/ChangeLog: PR target/104946 * config/i386/i386-builtin.def (BDESC): Add CODE_FOR_sse4_1_blendvpd for IX86_BUILTIN_BLENDVPD. * config/i386/i386.cc (ix86_gimple_fold_builtin): Don't fold __builtin_ia32_blendvpd w/o sse4.2 gcc/testsuite/ChangeLog: * gcc.target/i386/sse4_1-blendvpd-1.c: New test. --- gcc/config/i386/i386-builtin.def | 2 +- gcc/config/i386/i386.cc | 8 +++++++- gcc/testsuite/gcc.target/i386/sse4_1-blendvpd-1.c | 11 +++++++++++ 3 files changed, 19 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/sse4_1-blendvpd-1.c diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index ea327555639..b410102614d 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -906,7 +906,7 @@ BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_ssse3_palignrdi, /* SSE4.1 */ BDESC (OPTION_MASK_ISA_SSE4_1, 0, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT) BDESC (OPTION_MASK_ISA_SSE4_1, 0, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT) -BDESC (OPTION_MASK_ISA_SSE4_1, 0, CODE_FOR_nothing, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF) +BDESC (OPTION_MASK_ISA_SSE4_1, 0, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF) BDESC (OPTION_MASK_ISA_SSE4_1, 0, CODE_FOR_nothing, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF) BDESC (OPTION_MASK_ISA_SSE4_1, 0, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT) BDESC (OPTION_MASK_ISA_SSE4_1, 0, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT) diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc index d77ad83e437..5a561966eb4 100644 --- a/gcc/config/i386/i386.cc +++ b/gcc/config/i386/i386.cc @@ -18368,10 +18368,16 @@ ix86_gimple_fold_builtin (gimple_stmt_iterator *gsi) } break; + case IX86_BUILTIN_BLENDVPD: + /* blendvpd is under sse4.1 but pcmpgtq is under sse4.2, + w/o sse4.2, it's veclowered to scalar operations and + not combined back. */ + if (!TARGET_SSE4_2) + break; + /* FALLTHRU. */ case IX86_BUILTIN_PBLENDVB128: case IX86_BUILTIN_PBLENDVB256: case IX86_BUILTIN_BLENDVPS: - case IX86_BUILTIN_BLENDVPD: case IX86_BUILTIN_BLENDVPS256: case IX86_BUILTIN_BLENDVPD256: gcc_assert (n_args == 3); diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-blendvpd-1.c b/gcc/testsuite/gcc.target/i386/sse4_1-blendvpd-1.c new file mode 100644 index 00000000000..c25d3fbcbd4 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse4_1-blendvpd-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-msse4.1 -O2 -mno-sse4.2" } */ +/* { dg-final { scan-assembler-times {(?n)blendvpd[ \t]+%xmm[0-9]+} 1 } } */ + +#include + +__m128d +foo (__m128d a, __m128d b, __m128d c) +{ + return _mm_blendv_pd (a, b, c); +}