From patchwork Thu Mar 10 15:50:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Frederic Barrat X-Patchwork-Id: 1603964 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=WIh4x3if; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4KDtxn2fY2z9sGW for ; Fri, 11 Mar 2022 02:57:47 +1100 (AEDT) Received: from localhost ([::1]:55764 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSLAe-0000ak-LJ for incoming@patchwork.ozlabs.org; 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Thu, 10 Mar 2022 15:51:02 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3C2165204F; Thu, 10 Mar 2022 15:51:02 +0000 (GMT) Received: from localhost.ibm.com (unknown [9.101.4.17]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id 0156152052; Thu, 10 Mar 2022 15:51:01 +0000 (GMT) From: Frederic Barrat To: clg@kaod.org, danielhb413@gmail.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 1/3] ppc/pnv: Introduce a pnv-phb5 device to match root port Date: Thu, 10 Mar 2022 16:50:59 +0100 Message-Id: <20220310155101.294568-2-fbarrat@linux.ibm.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220310155101.294568-1-fbarrat@linux.ibm.com> References: <20220310155101.294568-1-fbarrat@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: hSMDrJBq16PCRsgKlAdCuh_AianrRwDj X-Proofpoint-GUID: M_3P55nBCx7yF81K6TdmEz39Gd_1bGEd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-03-10_06,2022-03-09_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 mlxscore=0 clxscore=1015 adultscore=0 mlxlogscore=999 suspectscore=0 spamscore=0 priorityscore=1501 malwarescore=0 phishscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2202240000 definitions=main-2203100084 Received-SPF: pass client-ip=148.163.156.1; envelope-from=fbarrat@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-ppc" We already have the pnv-phb3 and pnv-phb4 devices for POWER8 and POWER9 respectively. POWER10 uses version 5 of the PHB. It is very close to the PHB4 from POWER9, at least in our model and we could almost keep using the PHB4 model. However the matching root port pnv-phb5-root-port is specific to POWER10 so to avoid confusion as well as making it easy to introduce differences later, we create a pnv-phb5 class, which is mostly an alias for pnv-phb4 for now. With this patch, the command line for a user-created PHB on powernv10 becomes: -machine powernv10 -nodefaults -device pnv-phb5 -device pnv-phb5-root-port Fixes: 623575e16cd5 ("ppc/pnv: Add model for POWER10 PHB5 PCIe Host bridge") Signed-off-by: Frederic Barrat Reviewed-by: Cédric Le Goater --- hw/pci-host/pnv_phb4.c | 7 +++++++ hw/pci-host/pnv_phb4_pec.c | 9 +++++---- include/hw/pci-host/pnv_phb4.h | 5 +++++ 3 files changed, 17 insertions(+), 4 deletions(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index b5b384e9ee..d1a911f988 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -1783,6 +1783,12 @@ static const TypeInfo pnv_phb4_type_info = { } }; +static const TypeInfo pnv_phb5_type_info = { + .name = TYPE_PNV_PHB5, + .parent = TYPE_PNV_PHB4, + .instance_size = sizeof(PnvPHB4), +}; + static void pnv_phb4_root_bus_class_init(ObjectClass *klass, void *data) { BusClass *k = BUS_CLASS(klass); @@ -1907,6 +1913,7 @@ static void pnv_phb4_register_types(void) type_register_static(&pnv_phb5_root_port_info); type_register_static(&pnv_phb4_root_port_info); type_register_static(&pnv_phb4_type_info); + type_register_static(&pnv_phb5_type_info); type_register_static(&pnv_phb4_iommu_memory_region_info); } diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index 0ab36e9c8f..a0dfa77c84 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -116,7 +116,8 @@ static void pnv_pec_default_phb_realize(PnvPhb4PecState *pec, int stack_no, Error **errp) { - PnvPHB4 *phb = PNV_PHB4(qdev_new(TYPE_PNV_PHB4)); + PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); + PnvPHB4 *phb = PNV_PHB4(qdev_new(pecc->phb_type)); int phb_id = pnv_phb4_pec_get_phb_id(pec, stack_no); object_property_set_link(OBJECT(phb), "pec", OBJECT(pec), @@ -131,9 +132,7 @@ static void pnv_pec_default_phb_realize(PnvPhb4PecState *pec, } /* Add a single Root port if running with defaults */ - pnv_phb_attach_root_port(PCI_HOST_BRIDGE(phb), - PNV_PHB4_PEC_GET_CLASS(pec)->rp_model); - + pnv_phb_attach_root_port(PCI_HOST_BRIDGE(phb), pecc->rp_model); } static void pnv_pec_realize(DeviceState *dev, Error **errp) @@ -265,6 +264,7 @@ static void pnv_pec_class_init(ObjectClass *klass, void *data) pecc->stk_compat = stk_compat; pecc->stk_compat_size = sizeof(stk_compat); pecc->version = PNV_PHB4_VERSION; + pecc->phb_type = TYPE_PNV_PHB4; pecc->num_phbs = pnv_pec_num_phbs; pecc->rp_model = TYPE_PNV_PHB4_ROOT_PORT; } @@ -317,6 +317,7 @@ static void pnv_phb5_pec_class_init(ObjectClass *klass, void *data) pecc->stk_compat = stk_compat; pecc->stk_compat_size = sizeof(stk_compat); pecc->version = PNV_PHB5_VERSION; + pecc->phb_type = TYPE_PNV_PHB5; pecc->num_phbs = pnv_phb5_pec_num_stacks; pecc->rp_model = TYPE_PNV_PHB5_ROOT_PORT; } diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h index fbcf5bfb55..b02ecdceaa 100644 --- a/include/hw/pci-host/pnv_phb4.h +++ b/include/hw/pci-host/pnv_phb4.h @@ -203,6 +203,7 @@ struct PnvPhb4PecClass { const char *stk_compat; int stk_compat_size; uint64_t version; + const char *phb_type; const uint32_t *num_phbs; const char *rp_model; }; @@ -211,6 +212,10 @@ struct PnvPhb4PecClass { * POWER10 definitions */ +#define TYPE_PNV_PHB5 "pnv-phb5" +#define PNV_PHB5(obj) \ + OBJECT_CHECK(PnvPhb4, (obj), TYPE_PNV_PHB5) + #define PNV_PHB5_VERSION 0x000000a500000001ull #define PNV_PHB5_DEVICE_ID 0x0652 From patchwork Thu Mar 10 15:51:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Frederic Barrat X-Patchwork-Id: 1603957 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=jeKtcGij; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org; 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Thu, 10 Mar 2022 15:51:02 +0000 (GMT) From: Frederic Barrat To: clg@kaod.org, danielhb413@gmail.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 2/3] ppc/pnv: Fixes for user-created pnv-phb5 devices Date: Thu, 10 Mar 2022 16:51:00 +0100 Message-Id: <20220310155101.294568-3-fbarrat@linux.ibm.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220310155101.294568-1-fbarrat@linux.ibm.com> References: <20220310155101.294568-1-fbarrat@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: qFm9z31BBvxGTB3J6sxWr60AKuUhUFWC X-Proofpoint-GUID: D2oGwTBaYqP6rhmwZRPYqPxs6jyg_2x_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-03-10_03,2022-03-09_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1011 suspectscore=0 impostorscore=0 priorityscore=1501 adultscore=0 mlxscore=0 bulkscore=0 spamscore=0 mlxlogscore=999 phishscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2202240000 definitions=main-2203100084 Received-SPF: pass client-ip=148.163.158.5; envelope-from=fbarrat@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-ppc" Two small fixes to fix user-created devices for POWER10: - always create the PECs (PCI Express Controller) for the system. The PECs host the PHBs and we try to find the matching PEC when creating a PHB, so it must exist. It also matches what we do on POWER9 - the machine class must allow dynamically allocated system bus Fixes: 623575e16cd5 ("ppc/pnv: Add model for POWER10 PHB5 PCIe Host bridge") Signed-off-by: Frederic Barrat Reviewed-by: Cédric Le Goater --- hw/ppc/pnv.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 0ac86e104f..df58403a3a 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1600,9 +1600,7 @@ static void pnv_chip_power10_instance_init(Object *obj) object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER); - if (defaults_enabled()) { - chip->num_pecs = pcc->num_pecs; - } + chip->num_pecs = pcc->num_pecs; for (i = 0; i < chip->num_pecs; i++) { object_initialize_child(obj, "pec[*]", &chip10->pecs[i], @@ -2171,6 +2169,8 @@ static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) pmc->dt_power_mgt = pnv_dt_power_mgt; xfc->match_nvt = pnv10_xive_match_nvt; + + machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB5); } static bool pnv_machine_get_hb(Object *obj, Error **errp) From patchwork Thu Mar 10 15:51:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Frederic Barrat X-Patchwork-Id: 1603958 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=Fb0aTmuv; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4KDtpL1CWNz9sGl for ; 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Thu, 10 Mar 2022 15:51:02 +0000 (GMT) From: Frederic Barrat To: clg@kaod.org, danielhb413@gmail.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 3/3] ppc/pnv: Fix PEC lookup function for POWER10 Date: Thu, 10 Mar 2022 16:51:01 +0100 Message-Id: <20220310155101.294568-4-fbarrat@linux.ibm.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220310155101.294568-1-fbarrat@linux.ibm.com> References: <20220310155101.294568-1-fbarrat@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: bIaJu2K69-OAV3JZ7ENI8-w1pGg8fxs3 X-Proofpoint-ORIG-GUID: yo6qOnecQFZWZei5U0lB1ujiShUqPkRZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-03-10_06,2022-03-09_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 impostorscore=0 phishscore=0 adultscore=0 malwarescore=0 suspectscore=0 mlxscore=0 spamscore=0 bulkscore=0 priorityscore=1501 mlxlogscore=856 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2202240000 definitions=main-2203100084 Received-SPF: pass client-ip=148.163.158.5; envelope-from=fbarrat@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-ppc" The PEC array used when looking for the PEC hosting a PHB is stored in the chip structure. The array is at a different offset in Pnv9Chip and Pnv10Chip. The lookup function was therefore not working properly on POWER10. This patch fixes it by introducing a class method to get the correct PEC pointer based on the chip object and PEC index. Fixes: 623575e16cd5 ("ppc/pnv: Add model for POWER10 PHB5 PCIe Host bridge") Signed-off-by: Frederic Barrat Reviewed-by: Cédric Le Goater --- hw/pci-host/pnv_phb4.c | 5 ++--- hw/ppc/pnv.c | 14 ++++++++++++++ include/hw/ppc/pnv.h | 1 + 3 files changed, 17 insertions(+), 3 deletions(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index d1a911f988..4732633833 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -1548,7 +1548,6 @@ static void pnv_phb4_instance_init(Object *obj) static PnvPhb4PecState *pnv_phb4_get_pec(PnvChip *chip, PnvPHB4 *phb, Error **errp) { - Pnv9Chip *chip9 = PNV9_CHIP(chip); int chip_id = phb->chip_id; int index = phb->phb_id; int i, j; @@ -1556,9 +1555,9 @@ static PnvPhb4PecState *pnv_phb4_get_pec(PnvChip *chip, PnvPHB4 *phb, for (i = 0; i < chip->num_pecs; i++) { /* * For each PEC, check the amount of phbs it supports - * and see if the given phb4 index matches an index. + * and see if the given phb index matches an index. */ - PnvPhb4PecState *pec = &chip9->pecs[i]; + PnvPhb4PecState *pec = PNV_CHIP_GET_CLASS(chip)->get_pec(chip, i); for (j = 0; j < pec->num_phbs; j++) { if (index == pnv_phb4_pec_get_phb_id(pec, j)) { diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index df58403a3a..3a676cd570 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1561,6 +1561,12 @@ static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) return addr >> 3; } +static PnvPhb4PecState *pnv_chip_power9_get_pec(PnvChip *chip, uint32_t index) +{ + Pnv9Chip *chip9 = PNV9_CHIP(chip); + return &chip9->pecs[index]; +} + static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -1580,6 +1586,7 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) k->xscom_pcba = pnv_chip_power9_xscom_pcba; dc->desc = "PowerNV Chip POWER9"; k->num_pecs = PNV9_CHIP_MAX_PEC; + k->get_pec = pnv_chip_power9_get_pec; device_class_set_parent_realize(dc, pnv_chip_power9_realize, &k->parent_realize); @@ -1769,6 +1776,12 @@ static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) return addr >> 3; } +static PnvPhb4PecState *pnv_chip_power10_get_pec(PnvChip *chip, uint32_t index) +{ + Pnv10Chip *chip10 = PNV10_CHIP(chip); + return &chip10->pecs[index]; +} + static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -1788,6 +1801,7 @@ static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) k->xscom_pcba = pnv_chip_power10_xscom_pcba; dc->desc = "PowerNV Chip POWER10"; k->num_pecs = PNV10_CHIP_MAX_PEC; + k->get_pec = pnv_chip_power10_get_pec; device_class_set_parent_realize(dc, pnv_chip_power10_realize, &k->parent_realize); diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 1e34ddd502..282f76ba08 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -163,6 +163,7 @@ struct PnvChipClass { void (*pic_print_info)(PnvChip *chip, Monitor *mon); uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id); uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr); + PnvPhb4PecState *(*get_pec)(PnvChip *chip, uint32_t index); }; #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP