From patchwork Tue Mar 8 14:24:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vincent Whitchurch X-Patchwork-Id: 1603043 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=axis.com header.i=@axis.com header.a=rsa-sha256 header.s=axis-central1 header.b=ltNCn1cr; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4KCcz65jyXz9sGC for ; Wed, 9 Mar 2022 01:24:34 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347408AbiCHOZY (ORCPT ); Tue, 8 Mar 2022 09:25:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51236 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347322AbiCHOZX (ORCPT ); Tue, 8 Mar 2022 09:25:23 -0500 Received: from smtp1.axis.com (smtp1.axis.com [195.60.68.17]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 699D249F92; Tue, 8 Mar 2022 06:24:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=axis.com; q=dns/txt; s=axis-central1; t=1646749467; x=1678285467; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tK6Q1jDnBvijOHqCEkvoL00vEaJl4FM8rW1EITUDKrs=; b=ltNCn1criIAwWcvhYb4S7NnaH3fluZAvXzh65Pd3+sMtsNZHFChXA4Ro IypkuG9vitQ6QjH931nPRNR2WNMAhtpWHNWtEMq7zivlDuOTviqIcIvDU 54OXk1IWIYHSQv0i15Fd2fzMNzMpE5qLtJ/BzgWSeOxCEgHlO51wkDtX9 gXQeMQ39X0EAAYAZli70R2DZPC8FjDd8iLJtZMEiUZ2Qrn7eEe5Dl/hOl B79ggAr8nAbtCpbYevD5GfGSv2sOqnUUBM4jHmeWQ40Lg/JODeh/3zU3N rSpy6QSBsBdRVucbluuEmmF2J7FaY/R13PT/oGQpT724BqWk+NFmCretc w==; From: Vincent Whitchurch To: , , CC: , , , , , , , Vincent Whitchurch Subject: [PATCH v2 1/4] dt-bindings: timer: exynos4210-mct: Add ARTPEC-8 MCT Date: Tue, 8 Mar 2022 15:24:07 +0100 Message-ID: <20220308142410.3193729-2-vincent.whitchurch@axis.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220308142410.3193729-1-vincent.whitchurch@axis.com> References: <20220308142410.3193729-1-vincent.whitchurch@axis.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This SoC has an MCT with 4 global and 8 local timer interrupts, add a specific compatible to match it as is done for the other platforms with this hardware block. Signed-off-by: Vincent Whitchurch Reviewed-by: Krzysztof Kozlowski --- Notes: v2: New. Requires Krzysztof's "dt-bindings: timer: exynos4210-mct: describe hardware and its interrupts". .../devicetree/bindings/timer/samsung,exynos4210-mct.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml index 1584944c7ac4..dce42f1f7574 100644 --- a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml +++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml @@ -25,6 +25,7 @@ properties: - samsung,exynos4412-mct - items: - enum: + - axis,artpec8-mct - samsung,exynos3250-mct - samsung,exynos5250-mct - samsung,exynos5260-mct @@ -102,6 +103,7 @@ allOf: compatible: contains: enum: + - axis,artpec8-mct - samsung,exynos5260-mct - samsung,exynos5420-mct - samsung,exynos5433-mct From patchwork Tue Mar 8 14:24:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vincent Whitchurch X-Patchwork-Id: 1603044 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=axis.com header.i=@axis.com header.a=rsa-sha256 header.s=axis-central1 header.b=gKmdEYXw; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4KCcz71gF6z9sFw for ; Wed, 9 Mar 2022 01:24:35 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347429AbiCHOZZ (ORCPT ); Tue, 8 Mar 2022 09:25:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51240 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347353AbiCHOZX (ORCPT ); Tue, 8 Mar 2022 09:25:23 -0500 Received: from smtp1.axis.com (smtp1.axis.com [195.60.68.17]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A236347AF5; Tue, 8 Mar 2022 06:24:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=axis.com; q=dns/txt; s=axis-central1; t=1646749467; x=1678285467; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6KwAXn4jvSph/kkMgeY9egBCzjFV3kNndn+PTRpZ548=; b=gKmdEYXwJY8KE9ZYdnBVVQtB70opXBFB+odyd2FHOGMCIoxFBwUyFEa1 XPgSZNVeLUtEGYmjhhBb625SYjZLOIx7otitfxn5691lBZzcoGl9+Z+0z WpbM0YIphiocp0362ZP4M0yVQtjWzFFpWlqQuE6qDox+Fi32ylZMvfEtD HvwH3vOuHoT9PfWHb5A7N68h7P7QlyRBeKtX7KerqdF3g/KoaBpGMiNk3 4/DMvuaBcbLJWGNA5OymjYGNy8iOG2+QUinBq3Qck+rPZ8Zj6BlPRvzaM Vx+4vhyt3IqIqkOJBOFs3EVozN4Frnjgw7wQ/hV0Jto63X/YMpbTQQlEx g==; From: Vincent Whitchurch To: , , CC: , , , , , , , Vincent Whitchurch Subject: [PATCH v2 2/4] dt-bindings: timer: exynos4210-mct: Support using only local timer Date: Tue, 8 Mar 2022 15:24:08 +0100 Message-ID: <20220308142410.3193729-3-vincent.whitchurch@axis.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220308142410.3193729-1-vincent.whitchurch@axis.com> References: <20220308142410.3193729-1-vincent.whitchurch@axis.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The ARTPEC-8 SoC has a quad-core Cortex-A53 and a single-core Cortex-A5 which share one MCT with one global and eight local timers. The Cortex-A53 and Cortex-A5 do not have cache-coherency between them, and therefore run two separate kernels. The Cortex-A53 boots first and starts the global FRC and also registers a clock events device using the global timer. (This global timer clock events is usually replaced by arch timer clock events for each of the cores.) When the A5 boots, we should not use the global timer interrupts or write to the global timer registers. This is because even if there are four global comparators, the control bits for all four are in the same registers, and we would need to synchronize between the cpus. Instead, the global timer FRC (already started by the A53) should be used as the clock source, and one of the local timers which are not used by the A53 can be used for clock events on the A5. To support this usecase, add a property to the binding to specify the first local timer index to be used. If this parameter is non-zero, the global timer interrupts will also not be used. Signed-off-by: Vincent Whitchurch --- Notes: v2: New. .../bindings/timer/samsung,exynos4210-mct.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml index dce42f1f7574..46f466081836 100644 --- a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml +++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml @@ -47,6 +47,15 @@ properties: reg: maxItems: 1 + local-timer-index: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + maximum: 15 # Last local timer index + description: | + If present, sets the first local timer index to use. If this value is + set to a non-default value, the global timer will not be used for + interrupts. + interrupts: description: | Interrupts should be put in specific order. This is, the local timer