From patchwork Mon Feb 14 13:58:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 1592560 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=1STNxXZB; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4Jy5Nf1cPsz9s8s for ; Tue, 15 Feb 2022 00:56:18 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230271AbiBNN4W (ORCPT ); Mon, 14 Feb 2022 08:56:22 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:35602 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244946AbiBNN4U (ORCPT ); Mon, 14 Feb 2022 08:56:20 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7F3CE65A2; Mon, 14 Feb 2022 05:56:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1644846972; x=1676382972; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EtYuILF7xkob3kdvffJYLceJMqnJTJAXi3Gd2XazbpE=; b=1STNxXZBnDSC7v8adjkRbsWP8j5r9sVDHapu4FmZ6JNB9MzDL4fvp7W1 hTqepHJUrFPEdKVTZQeYAY8uoyOIUT7QB05yAIB5j2Qs5PdyoDcVioWbZ /wKWvzqbOaFOZTSxxBY9oCKxJOnzWF9KYPW06wtwci8puRZibk5I5vQsJ UncNnLO3ZMAIWhyXnSRsFNnFa7qqkY5vKIFKPWJpJg49/j7Epljdv/WTc JWvAnDudR/yieI0UNzWvawNqe7UPO10VgXN9f8whIMtVwoAPMDbwAcFyl gRHaAD/3N9n7pK25Cw3zqQxEVt3w5ZzsfnYvufjbtWUHoGFVTxbykXX8F g==; IronPort-SDR: wPUoDtICV6PAJAk4ja1awlKxD/ZqLzZJFjgolwHdDrhC4161cgo77QaQ6wgGVaRG5W9rXAHVUs +ZrU2jxez/TWiWWUG6zap/+fZGDt92VMK4EqUdGbQ07RFCmqen7iuumeN9Ia1FRcQvv0D6T483 oWnck7ZBSJAPHhk/bqZQtK92rA5DefkzfMjDNlcF5PZn5Xm7HjcAR9cxBw2iR/Vrk7+7L7CJg2 9DPJqfgAz0CoS4lh3ng2eJFSUFUD1x+xrgp/m72IP4oLJlbcoEi3hJcx90f1pXyeoLu7nIp3FE U/H44Zev2Zv7fVu1UVV5pVks X-IronPort-AV: E=Sophos;i="5.88,368,1635231600"; d="scan'208";a="152982569" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 14 Feb 2022 06:56:11 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 14 Feb 2022 06:56:10 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 14 Feb 2022 06:56:05 -0700 From: To: , , , , , , , , , , , , , , , , , , , CC: , , , , , Rob Herring , Palmer Dabbelt Subject: [PATCH v7 01/11] dt-bindings: soc/microchip: update syscontroller compatibles Date: Mon, 14 Feb 2022 13:58:31 +0000 Message-ID: <20220214135840.168236-2-conor.dooley@microchip.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220214135840.168236-1-conor.dooley@microchip.com> References: <20220214135840.168236-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Conor Dooley The Polarfire SoC is currently using two different compatible string prefixes. Fix this by changing "polarfire-soc-*" strings to "mpfs-*" in its system controller in order to match the compatible string used in the soc binding and device tree Reviewed-by: Geert Uytterhoeven Signed-off-by: Conor Dooley Acked-by: Rob Herring Acked-by: Palmer Dabbelt --- ...larfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} | 6 +++--- ...s-controller.yaml => microchip,mpfs-sys-controller.yaml} | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) rename Documentation/devicetree/bindings/mailbox/{microchip,polarfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} (82%) rename Documentation/devicetree/bindings/soc/microchip/{microchip,polarfire-soc-sys-controller.yaml => microchip,mpfs-sys-controller.yaml} (75%) diff --git a/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml similarity index 82% rename from Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml rename to Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml index bbb173ea483c..082d397d3e89 100644 --- a/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/mailbox/microchip,polarfire-soc-mailbox.yaml#" +$id: "http://devicetree.org/schemas/mailbox/microchip,mpfs-mailbox.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) mailbox controller @@ -11,7 +11,7 @@ maintainers: properties: compatible: - const: microchip,polarfire-soc-mailbox + const: microchip,mpfs-mailbox reg: items: @@ -38,7 +38,7 @@ examples: #address-cells = <2>; #size-cells = <2>; mbox: mailbox@37020000 { - compatible = "microchip,polarfire-soc-mailbox"; + compatible = "microchip,mpfs-mailbox"; reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318c 0x0 0x40>; interrupt-parent = <&L1>; interrupts = <96>; diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml similarity index 75% rename from Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml rename to Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml index 2cd3bc6bd8d6..f699772fedf3 100644 --- a/Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/soc/microchip/microchip,polarfire-soc-sys-controller.yaml#" +$id: "http://devicetree.org/schemas/soc/microchip/microchip,mpfs-sys-controller.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) system controller @@ -19,7 +19,7 @@ properties: maxItems: 1 compatible: - const: microchip,polarfire-soc-sys-controller + const: microchip,mpfs-sys-controller required: - compatible @@ -30,6 +30,6 @@ additionalProperties: false examples: - | syscontroller: syscontroller { - compatible = "microchip,polarfire-soc-sys-controller"; + compatible = "microchip,mpfs-sys-controller"; mboxes = <&mbox 0>; }; From patchwork Mon Feb 14 13:58:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 1592564 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=YXMH/b0s; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4Jy5Nh50Wwz9s8s for ; Tue, 15 Feb 2022 00:56:20 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1354646AbiBNN4Z (ORCPT ); Mon, 14 Feb 2022 08:56:25 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:35646 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1354641AbiBNN4Z (ORCPT ); Mon, 14 Feb 2022 08:56:25 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4BAAD65A2; Mon, 14 Feb 2022 05:56:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1644846976; x=1676382976; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=WhgHwToS3AP40rPUHhKv2AxIWSk3spmDUHvAqgB73q8=; b=YXMH/b0sfayS38Rzkx1N0LIqlvnt0+Qbz2G3Ivf8Zhy/b/0aDomCSHMW +x+l8EjaJaaF5TAvyo24rJXc38oPcRPUD2+ag3Jco90acSsQegzZMx8sK QK2fUKe2YIU52yzyzjjdUNYGKpNwiygFL/9ixxaW4wH4s+tx9DxDoy4eW j/sf6cBuJZh+orznrrzhptEfgY7uIRSWvHKlRYwhyekTEe45NY/lcHt7I g85veMxhy+9RTyFi4qeEKe35Un/qJc0GK6/0kPPhGLH17/80JdmrVv0Hp Z4LnVi4oR8Qdy4Kl+be6OQMBklanuA8v+FfAnSHNJ+Ag+tLKJ8CzjbxxS Q==; IronPort-SDR: WfFUMexxhgNR55aNGdLqx16PC4bvZgMP416j7+VwUXR+eL6ohzkCwAWZAfF9o9QQ1F9u2Rj6DC NZ7n/tphc2d2s1rhvsm83KAyIFaLXrzr/Yy+exHCDzhDuNCp/yMa7t25RQnddr/lneOLewJTHT 104GXHqtt2NBbCv5c5dN+IiBGpOMRy6L8DanS91VP4LLSdoJwNwxfmMHssxez6A/Op3F00Ejma 8MQZbAaDxe/hL/pLtLx5IotMZOpkRy/+cNwQVVWbGhnEtSVTMk21nmkEjoBgV6iAkUwvii+seB uNeRPS3ekK8qTph9iSyR1n0Q X-IronPort-AV: E=Sophos;i="5.88,368,1635231600"; d="scan'208";a="153506330" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 14 Feb 2022 06:56:15 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 14 Feb 2022 06:56:15 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 14 Feb 2022 06:56:10 -0700 From: To: , , , , , , , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v7 02/11] dt-bindings: soc/microchip: add info about services to mpfs sysctrl Date: Mon, 14 Feb 2022 13:58:32 +0000 Message-ID: <20220214135840.168236-3-conor.dooley@microchip.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220214135840.168236-1-conor.dooley@microchip.com> References: <20220214135840.168236-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Conor Dooley The services actually provided by the system controller are not documented so add some words about what the system controller can actually do. Add a link to the oneline documentation with the specific details of each individual service. Also, drop the unneeded label from the example. Signed-off-by: Conor Dooley Reviewed-by: Rob Herring --- .../soc/microchip/microchip,mpfs-sys-controller.yaml | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml index f699772fedf3..b0dae51e1d42 100644 --- a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml @@ -10,9 +10,14 @@ maintainers: - Conor Dooley description: | - The PolarFire SoC system controller is communicated with via a mailbox. - This document describes the bindings for the client portion of that mailbox. + PolarFire SoC devices include a microcontroller acting as the system controller, + which provides "services" to the main processor and to the FPGA fabric. These + services include hardware rng, reprogramming of the FPGA and verfification of the + eNVM contents etc. More information on these services can be found online, at + https://onlinedocs.microchip.com/pr/GUID-1409CF11-8EF9-4C24-A94E-70979A688632-en-US-1/index.html + Communication with the system controller is done via a mailbox, of which the client + portion is documented here. properties: mboxes: @@ -29,7 +34,7 @@ additionalProperties: false examples: - | - syscontroller: syscontroller { + syscontroller { compatible = "microchip,mpfs-sys-controller"; mboxes = <&mbox 0>; }; From patchwork Mon Feb 14 13:58:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 1592568 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=EnYj5pzA; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4Jy5Nx5FTfz9s8s for ; Tue, 15 Feb 2022 00:56:33 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1354641AbiBNN4i (ORCPT ); Mon, 14 Feb 2022 08:56:38 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:36058 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1354661AbiBNN4g (ORCPT ); Mon, 14 Feb 2022 08:56:36 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 445A6CFD; Mon, 14 Feb 2022 05:56:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1644846988; x=1676382988; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RaK9SgN0U8rRaE6oOJFFvGb1cgu8ENs7J984QpIB3As=; b=EnYj5pzAYpyh3fAYnj3eVJkW5P/3bAkcwN8NKiIG1CJI0zTmJ4lB5ecr eRQ/qPHdepb6kiFBjigpvnKkjXuF1WFJABC9YzJlVeOzJCkBWrW6e/2sZ RXQD7tK2gbi1d2NrCYUpQXs2KvnZy5hYg6QefpqQkF1dCBGUVhyG3tMZb cupuIw45DlWr+HszxH0upb3yubu6nD1Aox9BWJQsQ871ClutIOchTup8R Q/NKsuIgZHZ2XrIIbrmi5mdUZEw3mnKAqe1JWdSw2amOcI8JQsdOo4KWt vKBp9z5U4dh+QlOHLfGzxkEDComHT+RiTgs0Fu3q9Hb6xTNXLyDyOySf6 g==; IronPort-SDR: UP5KAEpJ3QOcSjMg3QuPd61GIGkyeewE8UHSU9XeSWWk50jsqpHf/7+D7ASRM3R73rdp42cLOW cSAgOuyKQv7pL1h/kgLL6tI4yTWovmE1zetPbdlJ/KlF2IoNhvCqnpyZdOGW9e4thGsOXELtdm NDiyFsGmZ9MpE00JliaQ+y3eCP05giZNtvSG64CrtqxeOswMT6Nzr7zIED+zakBcfkWKCbhicP WLnzqqN6YeAMJZbMUnbQ53gzruvj1boWeyZDU1NNVYBqC2Jm6KK2uZKBTC2V/F9tiYLY+FgiyJ EUzkkukbWLETXAHDIHr08rSC X-IronPort-AV: E=Sophos;i="5.88,368,1635231600"; d="scan'208";a="148618016" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 14 Feb 2022 06:56:22 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 14 Feb 2022 06:56:21 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 14 Feb 2022 06:56:16 -0700 From: To: , , , , , , , , , , , , , , , , , , , CC: , , , , , Palmer Dabbelt , Rob Herring Subject: [PATCH v7 03/11] dt-bindings: rtc: add bindings for microchip mpfs rtc Date: Mon, 14 Feb 2022 13:58:33 +0000 Message-ID: <20220214135840.168236-4-conor.dooley@microchip.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220214135840.168236-1-conor.dooley@microchip.com> References: <20220214135840.168236-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Conor Dooley Add device tree bindings for the real time clock on the Microchip PolarFire SoC. Signed-off-by: Daire McNamara Signed-off-by: Conor Dooley Acked-by: Palmer Dabbelt Reviewed-by: Rob Herring Acked-by: Alexandre Belloni --- .../bindings/rtc/microchip,mfps-rtc.yaml | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml diff --git a/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml new file mode 100644 index 000000000000..a2e984ea3553 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml# + +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PolarFire Soc (MPFS) RTC Device Tree Bindings + +allOf: + - $ref: rtc.yaml# + +maintainers: + - Daire McNamara + - Lewis Hanly + +properties: + compatible: + enum: + - microchip,mpfs-rtc + + reg: + maxItems: 1 + + interrupts: + items: + - description: | + RTC_WAKEUP interrupt + - description: | + RTC_MATCH, asserted when the content of the Alarm register is equal + to that of the RTC's count register. + + clocks: + maxItems: 1 + + clock-names: + items: + - const: rtc + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + rtc@20124000 { + compatible = "microchip,mpfs-rtc"; + reg = <0x20124000 0x1000>; + clocks = <&clkcfg 21>; + clock-names = "rtc"; + interrupts = <80>, <81>; + }; +... From patchwork Mon Feb 14 13:58:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 1592571 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=Ij/BoHTW; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4Jy5Nz0DzYz9sFN for ; Tue, 15 Feb 2022 00:56:35 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1354675AbiBNN4j (ORCPT ); Mon, 14 Feb 2022 08:56:39 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:35988 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1354663AbiBNN4h (ORCPT ); Mon, 14 Feb 2022 08:56:37 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BF24449268; Mon, 14 Feb 2022 05:56:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1644846990; x=1676382990; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=S5yk/nKl+yfqerme9u3V2jXvLX05QLsi07mGzQMyLL4=; b=Ij/BoHTWUh/NF2YNArSCm3d0hpj/euNyyU0dvk9eXvHlujA8cYbx0okF stq9lNav4VjV563lxg1b5hJ8g9UzO/Tk67Ydja11LiaK+8dRvTdxs7G4s 4VDw/bffrXdlL7iRQvyLHzJKWhfQPljAJ41Clfa8Hb3a09amxSPcx2Zb0 5ktRsrXdwq9uhtvhukgS15aLNepS+d8QqoUOIjpQk1AVfQ5mqZx6tfCt5 K5ZyJHd2PeX0jTIHFVwUMKfXzZIhYtWzsc4BbdRb9QtCUZbUa/fPwd8/S 8G/aOy5dMDY4L+3uuavuYZ9odxtH1MCSuj3c9RLyvcTdvKVN5xQRpVPkY Q==; IronPort-SDR: KkYAeW0yo9IFmD1duJbhASl/qyLGdR+m2XwEyzYAGE5Zt8Wrrw7u9LDXQ6r4qqaC7SuF8Qvy/e gQXFLwnNJYIPOp5eQtXqoapnvjbfP+tLxr0PvG3JQCVKzPb3ewIK5IHpGXFI9icseWE3rxpNVG hAQT5cN9WbFf3VFWwl+k0gyzCFQYUbh5bC9tgR8TjZNfdpY/k784CXQC2Cr6gXmZH0FwIfrKX/ YYlCfv4U5TW7/VewMBmip4NqPGjQlHiyPEcsSch8FvhJ1mqHNvMe9WrqpdZ/es6LormGpnGkOv ZX41z4HEegN0ZQ1Y8A56Jtbm X-IronPort-AV: E=Sophos;i="5.88,368,1635231600"; d="scan'208";a="148618035" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 14 Feb 2022 06:56:28 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 14 Feb 2022 06:56:27 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 14 Feb 2022 06:56:21 -0700 From: To: , , , , , , , , , , , , , , , , , , , CC: , , , , , Rob Herring , Palmer Dabbelt Subject: [PATCH v7 04/11] dt-bindings: gpio: add bindings for microchip mpfs gpio Date: Mon, 14 Feb 2022 13:58:34 +0000 Message-ID: <20220214135840.168236-5-conor.dooley@microchip.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220214135840.168236-1-conor.dooley@microchip.com> References: <20220214135840.168236-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Conor Dooley Add device tree bindings for the gpio controller on the Microchip PolarFire SoC. Reviewed-by: Rob Herring Signed-off-by: Conor Dooley Acked-by: Palmer Dabbelt Acked-by: Bartosz Golaszewski --- .../bindings/gpio/microchip,mpfs-gpio.yaml | 79 +++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml diff --git a/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml new file mode 100644 index 000000000000..110651eafa70 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/microchip,mpfs-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip MPFS GPIO Controller Device Tree Bindings + +maintainers: + - Conor Dooley + +properties: + compatible: + items: + - enum: + - microchip,mpfs-gpio + + reg: + maxItems: 1 + + interrupts: + description: + Interrupt mapping, one per GPIO. Maximum 32 GPIOs. + minItems: 1 + maxItems: 32 + + interrupt-controller: true + + clocks: + maxItems: 1 + + "#gpio-cells": + const: 2 + + "#interrupt-cells": + const: 1 + + ngpios: + description: + The number of GPIOs available. + minimum: 1 + maximum: 32 + default: 32 + + gpio-controller: true + +required: + - compatible + - reg + - interrupts + - "#interrupt-cells" + - interrupt-controller + - "#gpio-cells" + - gpio-controller + - clocks + +additionalProperties: false + +examples: + - | + gpio@20122000 { + compatible = "microchip,mpfs-gpio"; + reg = <0x20122000 0x1000>; + clocks = <&clkcfg 25>; + interrupt-parent = <&plic>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts = <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>; + }; +... From patchwork Mon Feb 14 13:58:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 1592576 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=ubO3DwnA; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4Jy5P35d4jz9s8s for ; Tue, 15 Feb 2022 00:56:39 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1354690AbiBNN4n (ORCPT ); Mon, 14 Feb 2022 08:56:43 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:36268 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1354666AbiBNN4l (ORCPT ); Mon, 14 Feb 2022 08:56:41 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 73167B6B; Mon, 14 Feb 2022 05:56:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1644846994; x=1676382994; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UmflVMW1wi6gLsKsd8h3yAY2Rc3GU+Tr+EkBhqS8x6M=; b=ubO3DwnAdNbi3NPn9Gn1Dr+BAPz8gUGbl3dprhMlhxbpcyco4hQIwH6H 98K6bhm8k1u1tPrK9ORcpg8VrttVjJi06LGhAIWnDkRD9VOf2bPlLkx00 DvbgBVW9lYK5r7+nxFwepUeGv5ToEl1Vz1CnyngSqnsmtvLvb3p6G0yIV DKDy869sdaOXfRuqfNA2YUu1fTwWzj4N7MXKcU5kecT28lCizK0RT0raF 6nkFzzNItYsDUAUlkqlitcaFiuTz80pjUk6iIfp2O1S1m1P0jM0/V2pRe 6Zy6iElwdno6HpFD6qVNWEztf2AEjeoB1iYpl2dC1Ky6mtwaeosXQO6h/ g==; IronPort-SDR: wsWP+cXMNk//TH2wOX2suvAZexUeW0dvVf3GsXtzSo2q+XGN071f7gJDbYI0T2ehIbJbp31TOA PZpcqElnrUxoDUVxxBBaaphZGPlUzHI+/iYfuiuvZib4MaDIhogK+J5AWSEKjH6QBVB/W9fAYz bD7xa+hfXun6hk2IcgJf71us3Oktdt3zSrP8PrrS4FjU863DoZ59WEpfr0qtN/5EF/Rv1nL9Rr OSpsIcEog28Ln/CzAMwYjUfBBMkh8H7nNeAUxOxnwoGePVdP7eVBL5R/NA70wYOfyY682p7iVl tJq0JI60hBko+BcFgLPpaFn0 X-IronPort-AV: E=Sophos;i="5.88,368,1635231600"; d="scan'208";a="162154139" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 14 Feb 2022 06:56:33 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 14 Feb 2022 06:56:32 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 14 Feb 2022 06:56:27 -0700 From: To: , , , , , , , , , , , , , , , , , , , CC: , , , , , Rob Herring , Palmer Dabbelt Subject: [PATCH v7 05/11] dt-bindings: pwm: add microchip corepwm binding Date: Mon, 14 Feb 2022 13:58:35 +0000 Message-ID: <20220214135840.168236-6-conor.dooley@microchip.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220214135840.168236-1-conor.dooley@microchip.com> References: <20220214135840.168236-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Conor Dooley Add device tree bindings for the Microchip fpga fabric based "core" PWM controller. Reviewed-by: Rob Herring Signed-off-by: Conor Dooley Acked-by: Palmer Dabbelt Acked-by: Uwe Kleine-König Acked-by: Thierry Reding --- .../bindings/pwm/microchip,corepwm.yaml | 81 +++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml diff --git a/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml new file mode 100644 index 000000000000..a7fae1772a81 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/microchip,corepwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip IP corePWM controller bindings + +maintainers: + - Conor Dooley + +description: | + corePWM is an 16 channel pulse width modulator FPGA IP + + https://www.microsemi.com/existing-parts/parts/152118 + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + items: + - const: microchip,corepwm-rtl-v4 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#pwm-cells": + const: 2 + + microchip,sync-update-mask: + description: | + Depending on how the IP is instantiated, there are two modes of operation. + In synchronous mode, all channels are updated at the beginning of the PWM period, + and in asynchronous mode updates happen as the control registers are written. + A 16 bit wide "SHADOW_REG_EN" parameter of the IP core controls whether synchronous + mode is possible for each channel, and is set by the bitstream programmed to the + FPGA. If the IP core is instantiated with SHADOW_REG_ENx=1, both registers that + control the duty cycle for channel x have a second "shadow"/buffer reg synthesised. + At runtime a bit wide register exposed to APB can be used to toggle on/off + synchronised mode for all channels it has been synthesised for. + Each bit of "microchip,sync-update-mask" corresponds to a PWM channel & represents + whether synchronous mode is possible for the PWM channel. + + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + + microchip,dac-mode-mask: + description: | + Optional, per-channel Low Ripple DAC mode is possible on this IP core. It creates + a minimum period pulse train whose High/Low average is that of the chosen duty + cycle. This "DAC" will have far better bandwidth and ripple performance than the + standard PWM algorithm can achieve. A 16 bit DAC_MODE module parameter of the IP + core, set at instantiation and by the bitstream programmed to the FPGA, determines + whether a given channel operates in regular PWM or DAC mode. + Each bit corresponds to a PWM channel & represents whether DAC mode is enabled + for that channel. + + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + pwm@41000000 { + compatible = "microchip,corepwm-rtl-v4"; + microchip,sync-update-mask = /bits/ 32 <0>; + clocks = <&clkcfg 30>; + reg = <0x41000000 0xF0>; + #pwm-cells = <2>; + }; From patchwork Mon Feb 14 13:58:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 1592580 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=qFePtPuq; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4Jy5PH3vj2z9s8s for ; Tue, 15 Feb 2022 00:56:51 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1354734AbiBNN4z (ORCPT ); Mon, 14 Feb 2022 08:56:55 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:36424 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1354704AbiBNN4r (ORCPT ); Mon, 14 Feb 2022 08:56:47 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D13FD20F55; Mon, 14 Feb 2022 05:56:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1644847000; x=1676383000; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Xp+E8x6cp/+S9XO0xoBl+LMOfRA1V8o491BFrDS7rf8=; b=qFePtPuqxzhqEwKGMzBSlMrcnkqn1z/FwGxtGaUEpAmGNG5dr4RdzDSv lc9akbBULBKI1VBWD/Lj+oQCLnEN+ltHoAs4yQF7sKq1F3fyIgOfdp+5O 1af/TD+QY4PfAJI7VanJOBmTK+Uplq3vUvBiM19rb7XhwirCJ8trEHG38 scfARkByhOZmAofJ9uZdxICdsfnjTOiZ6rYzDmkrGodsE8DQ6gSRCqBhd Qyi9WxnwMlXI2E9bdboOQXTGjo1yLLTDWGa70bFgRvduBX2OrrRRCb/uk yQyw3dqU3U5KONM1Mfy0dTe0pSkEznWJfbPahUY19olH1UO3zOXRa+3Ab g==; IronPort-SDR: wc1mHIUGheJnmBF55xhVIjmMLeLe7Jo4ChNivm6PlS6zDKkbRXnd2S12SRNGw/iKr6GPNfXF9J 8phZow53I0a8Tn0IvABTTsifSjibxpxXR5gkx4cmgUjh0rxKACWAn9o4p53GCf5ZJc6cboIEkq owIxUa+7O132zHmnW/YAXwWasYljFmRFsQ51PVZqF707OHCHuvJbHpQchRU/tiivb9ZDZD+rI8 aJaSQQXdunIVL+KsReQVBOQnku3PmwC9naOg/lkvxNLK4NCjhlnyRVD/rx+bBlce6UoK1pakH8 k+9YHCGLs5zldN1LlOrkrLsK X-IronPort-AV: E=Sophos;i="5.88,368,1635231600"; d="scan'208";a="152982591" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 14 Feb 2022 06:56:39 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 14 Feb 2022 06:56:38 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 14 Feb 2022 06:56:33 -0700 From: To: , , , , , , , , , , , , , , , , , , , CC: , , , , , Palmer Dabbelt Subject: [PATCH v7 06/11] riscv: dts: microchip: use clk defines for icicle kit Date: Mon, 14 Feb 2022 13:58:36 +0000 Message-ID: <20220214135840.168236-7-conor.dooley@microchip.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220214135840.168236-1-conor.dooley@microchip.com> References: <20220214135840.168236-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Conor Dooley Update the Microchip Icicle kit device tree by replacing clock related magic numbers with their defined counterparts. Signed-off-by: Conor Dooley Acked-by: Palmer Dabbelt --- .../microchip/microchip-mpfs-icicle-kit.dts | 2 +- .../boot/dts/microchip/microchip-mpfs.dtsi | 25 ++++++++++--------- 2 files changed, 14 insertions(+), 13 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts index 0c748ae1b006..6d19ba196f12 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts @@ -31,7 +31,7 @@ cpus { memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x40000000>; - clocks = <&clkcfg 26>; + clocks = <&clkcfg CLK_DDRC>; }; }; diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi index 869aaf0d5c06..717e39b30a15 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -2,6 +2,7 @@ /* Copyright (c) 2020 Microchip Technology Inc */ /dts-v1/; +#include "dt-bindings/clock/microchip,mpfs-clock.h" / { #address-cells = <2>; @@ -14,7 +15,6 @@ cpus { #size-cells = <0>; cpu@0 { - clock-frequency = <0>; compatible = "sifive,e51", "sifive,rocket0", "riscv"; device_type = "cpu"; i-cache-block-size = <64>; @@ -22,6 +22,7 @@ cpu@0 { i-cache-size = <16384>; reg = <0>; riscv,isa = "rv64imac"; + clocks = <&clkcfg CLK_CPU>; status = "disabled"; cpu0_intc: interrupt-controller { @@ -32,7 +33,6 @@ cpu0_intc: interrupt-controller { }; cpu@1 { - clock-frequency = <0>; compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; @@ -48,6 +48,7 @@ cpu@1 { mmu-type = "riscv,sv39"; reg = <1>; riscv,isa = "rv64imafdc"; + clocks = <&clkcfg CLK_CPU>; tlb-split; status = "okay"; @@ -59,7 +60,6 @@ cpu1_intc: interrupt-controller { }; cpu@2 { - clock-frequency = <0>; compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; @@ -75,6 +75,7 @@ cpu@2 { mmu-type = "riscv,sv39"; reg = <2>; riscv,isa = "rv64imafdc"; + clocks = <&clkcfg CLK_CPU>; tlb-split; status = "okay"; @@ -86,7 +87,6 @@ cpu2_intc: interrupt-controller { }; cpu@3 { - clock-frequency = <0>; compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; @@ -102,6 +102,7 @@ cpu@3 { mmu-type = "riscv,sv39"; reg = <3>; riscv,isa = "rv64imafdc"; + clocks = <&clkcfg CLK_CPU>; tlb-split; status = "okay"; @@ -113,7 +114,6 @@ cpu3_intc: interrupt-controller { }; cpu@4 { - clock-frequency = <0>; compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; @@ -129,6 +129,7 @@ cpu@4 { mmu-type = "riscv,sv39"; reg = <4>; riscv,isa = "rv64imafdc"; + clocks = <&clkcfg CLK_CPU>; tlb-split; status = "okay"; cpu4_intc: interrupt-controller { @@ -210,7 +211,7 @@ serial0: serial@20000000 { interrupt-parent = <&plic>; interrupts = <90>; current-speed = <115200>; - clocks = <&clkcfg 8>; + clocks = <&clkcfg CLK_MMUART0>; status = "disabled"; }; @@ -222,7 +223,7 @@ serial1: serial@20100000 { interrupt-parent = <&plic>; interrupts = <91>; current-speed = <115200>; - clocks = <&clkcfg 9>; + clocks = <&clkcfg CLK_MMUART1>; status = "disabled"; }; @@ -234,7 +235,7 @@ serial2: serial@20102000 { interrupt-parent = <&plic>; interrupts = <92>; current-speed = <115200>; - clocks = <&clkcfg 10>; + clocks = <&clkcfg CLK_MMUART2>; status = "disabled"; }; @@ -246,7 +247,7 @@ serial3: serial@20104000 { interrupt-parent = <&plic>; interrupts = <93>; current-speed = <115200>; - clocks = <&clkcfg 11>; + clocks = <&clkcfg CLK_MMUART3>; status = "disabled"; }; @@ -256,7 +257,7 @@ mmc: mmc@20008000 { reg = <0x0 0x20008000 0x0 0x1000>; interrupt-parent = <&plic>; interrupts = <88>, <89>; - clocks = <&clkcfg 6>; + clocks = <&clkcfg CLK_MMC>; max-frequency = <200000000>; status = "disabled"; }; @@ -267,7 +268,7 @@ emac0: ethernet@20110000 { interrupt-parent = <&plic>; interrupts = <64>, <65>, <66>, <67>; local-mac-address = [00 00 00 00 00 00]; - clocks = <&clkcfg 4>, <&clkcfg 2>; + clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; clock-names = "pclk", "hclk"; status = "disabled"; #address-cells = <1>; @@ -280,7 +281,7 @@ emac1: ethernet@20112000 { interrupt-parent = <&plic>; interrupts = <70>, <71>, <72>, <73>; local-mac-address = [00 00 00 00 00 00]; - clocks = <&clkcfg 5>, <&clkcfg 2>; + clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; status = "disabled"; clock-names = "pclk", "hclk"; #address-cells = <1>; From patchwork Mon Feb 14 13:58:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 1592582 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=saOkMCzi; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4Jy5PW6bwQz9sCD for ; Tue, 15 Feb 2022 00:57:03 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1354681AbiBNN5H (ORCPT ); Mon, 14 Feb 2022 08:57:07 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:36830 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1354747AbiBNN44 (ORCPT ); Mon, 14 Feb 2022 08:56:56 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E78F44EA0F; Mon, 14 Feb 2022 05:56:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1644847006; x=1676383006; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CuM7K8ToBJ7RKoIFBCQywAvEKq4J6OlP+754BZRgkAU=; b=saOkMCzi7dk+ohFWbPJTmQ5EeP0tmoKhpEeyVZUr74PcxJXsED9pBUpc wOMu3ykI98sJ3kJcLNIPFKKd4TkAe3K0M6M+n3WKOKEsJ4zPkjn7Yqirz uTIF+ddZqVYe7/Xst0FNZQ/1J8JeZwAwAMKp51i4F1p7Rz+IfPPoIDDWT 9cM/OPPgB4w4teeN5v2boYFyth0iMdn4wDPrOpGK8/tdH41uPymwBNVsv KnxSV2lN7IA2urfIgQu079H93+a6fRkpI/XoJlrL4UsO8wyuGwW9pXXUu t0OOclw6/FV/LETYwCn/gj3fJkfyY5LAEjmlqDwrq0JaysuwlciLtCYo+ Q==; IronPort-SDR: B4lG6+0O8Fx8pvTp7P8/ONZSveDcqE57ZBUKdWX9EA6vsq0sDSyTpZotJRZPZgLeVR6rLU5EHG o8HqLk8S45lD/NFgNfjuz+BeVBsFECw7i+3Kg4ItMCRvHlzpJ2/QQ6xW1pDTlUzcX9MNsh9m4I 5+eIJkisejTqeacF+YIbQgrreNXoCoP6RgaCU5dL3Fz4bS6P61zHjKUSsyfI0HZJHKffcBi69r TqyfGdulzKTVsIg7nT9RAUz87sn004wL/9Nn3hDxJws9nayDXJh4/hkQuGWXnoupuDBxGw5pzO Jijcg0wleA6s1poY97SoTQ+T X-IronPort-AV: E=Sophos;i="5.88,368,1635231600"; d="scan'208";a="85633793" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 14 Feb 2022 06:56:44 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 14 Feb 2022 06:56:44 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 14 Feb 2022 06:56:38 -0700 From: To: , , , , , , , , , , , , , , , , , , , CC: , , , , , Palmer Dabbelt Subject: [PATCH v7 07/11] riscv: dts: microchip: add fpga fabric section to icicle kit Date: Mon, 14 Feb 2022 13:58:37 +0000 Message-ID: <20220214135840.168236-8-conor.dooley@microchip.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220214135840.168236-1-conor.dooley@microchip.com> References: <20220214135840.168236-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Conor Dooley Split the device tree for the Microchip MPFS into two sections by adding microchip-mpfs-fabric.dtsi, which contains peripherals contained in the FPGA fabric. Signed-off-by: Conor Dooley Acked-by: Palmer Dabbelt --- .../dts/microchip/microchip-mpfs-fabric.dtsi | 25 +++++++++++++++++++ .../microchip/microchip-mpfs-icicle-kit.dts | 8 ++++++ .../boot/dts/microchip/microchip-mpfs.dtsi | 1 + 3 files changed, 34 insertions(+) create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi new file mode 100644 index 000000000000..854320e17b28 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020-2021 Microchip Technology Inc */ + +/ { + core_pwm0: pwm@41000000 { + compatible = "microchip,corepwm-rtl-v4"; + reg = <0x0 0x41000000 0x0 0xF0>; + microchip,sync-update-mask = /bits/ 32 <0>; + #pwm-cells = <2>; + clocks = <&clkcfg CLK_FIC3>; + status = "disabled"; + }; + + i2c2: i2c@44000000 { + compatible = "microchip,corei2c-rtl-v7"; + reg = <0x0 0x44000000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkcfg CLK_FIC3>; + interrupt-parent = <&plic>; + interrupts = <122>; + clock-frequency = <100000>; + status = "disabled"; + }; +}; diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts index 6d19ba196f12..ab803f71626a 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts @@ -68,6 +68,10 @@ &mmc { sd-uhs-sdr104; }; +&i2c2 { + status = "okay"; +}; + &emac0 { phy-mode = "sgmii"; phy-handle = <&phy0>; @@ -86,3 +90,7 @@ phy1: ethernet-phy@9 { ti,fifo-depth = <0x01>; }; }; + +&core_pwm0 { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi index 717e39b30a15..c7d73756c9b8 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -3,6 +3,7 @@ /dts-v1/; #include "dt-bindings/clock/microchip,mpfs-clock.h" +#include "microchip-mpfs-fabric.dtsi" / { #address-cells = <2>; From patchwork Mon Feb 14 13:58:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 1592585 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=0C598M5P; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4Jy5PY291Hz9s8s for ; Tue, 15 Feb 2022 00:57:05 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1354722AbiBNN5J (ORCPT ); Mon, 14 Feb 2022 08:57:09 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:37078 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1354707AbiBNN5G (ORCPT ); Mon, 14 Feb 2022 08:57:06 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 16C3449F92; Mon, 14 Feb 2022 05:56:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1644847011; x=1676383011; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=v+naBJJ9gW5tTTYZDC+I9qkLd9zec9eUkonkP5epmmQ=; b=0C598M5PVS7BXA93rvw/xjYZZMDbZuqVd9KK+e0tf7S3r0OBRqopwNoI MLEH9An3l8jvsAPeNNQ2prVpFrxuprbz20sA4sIYExBDRoIEP09rh0E4B DNBClqAqCi+CU8bc3QsuK0ty8ITab5lGqkY3o/MFGUAZRSfPzEisbK+DZ RmdtT1/d7ZgppB6XO+bldzshybmSm0k430fF7KuvG4YWfjXblIRUVnndG ANzZNRZURCVuFWvjXN8iDq+CukrJk5SoSGmllPzWev6bEUMaq8RjhfplX 5Gw/m2p1PJqrA+WN/Sr9gQIbn+OIeWHJ5h6PFbutSxbUdXEeMGBsmg8Sv Q==; IronPort-SDR: uFeiYPZ+hc0z2oApyHm0RKhB5Z+5ijOCKb7kqNWjhDXEZDRTL2KqgGFlGqjnDvRHsnJPEu8lvJ NJO9+2QhVNPSYTSCNDNAjBRqy/RZrpGBNEZ8zZ0HRnyM6aURYBvi/r/N8813MJ3PrAMwiJxvzx EzbpNDdAJeEwTXpzChwFA5HO+1wEXhZZXYJdTAq/pxxwkuezgkf9/aIq5VKC0vx59Az2Ypqgi7 priFTFKrDf120iIlKFJA/Z5XWmJZP4nZFCluEZDTiC7P8hEKEZSLkXpqmKKvSgMEmlcH7sYpZl QFQ8fkFaYex0jXYE1yXhlq9W X-IronPort-AV: E=Sophos;i="5.88,368,1635231600"; d="scan'208";a="153506441" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 14 Feb 2022 06:56:50 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 14 Feb 2022 06:56:50 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 14 Feb 2022 06:56:44 -0700 From: To: , , , , , , , , , , , , , , , , , , , CC: , , , , , Palmer Dabbelt Subject: [PATCH v7 08/11] riscv: dts: microchip: refactor icicle kit device tree Date: Mon, 14 Feb 2022 13:58:38 +0000 Message-ID: <20220214135840.168236-9-conor.dooley@microchip.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220214135840.168236-1-conor.dooley@microchip.com> References: <20220214135840.168236-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Conor Dooley Assorted minor changes to the MPFS/Icicle kit device tree: - rename serial to mmuart to match microchip documentation - move phy0 inside mac1 node to match phy configuration - add labels where missing (cpus, cache controller) - add missing address cells & interrupts to MACs Signed-off-by: Conor Dooley Acked-by: Palmer Dabbelt --- .../microchip/microchip-mpfs-icicle-kit.dts | 37 ++++++----- .../boot/dts/microchip/microchip-mpfs.dtsi | 65 +++++++++---------- 2 files changed, 52 insertions(+), 50 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts index ab803f71626a..c51bd7cf500f 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts @@ -1,5 +1,5 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* Copyright (c) 2020 Microchip Technology Inc */ +/* Copyright (c) 2020-2021 Microchip Technology Inc */ /dts-v1/; @@ -13,11 +13,11 @@ / { compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs"; aliases { - ethernet0 = &emac1; - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; + ethernet0 = &mac1; + serial0 = &mmuart0; + serial1 = &mmuart1; + serial2 = &mmuart2; + serial3 = &mmuart3; }; chosen { @@ -39,19 +39,19 @@ &refclk { clock-frequency = <600000000>; }; -&serial0 { +&mmuart0 { status = "okay"; }; -&serial1 { +&mmuart1 { status = "okay"; }; -&serial2 { +&mmuart2 { status = "okay"; }; -&serial3 { +&mmuart3 { status = "okay"; }; @@ -61,7 +61,10 @@ &mmc { bus-width = <4>; disable-wp; cap-sd-highspeed; + cap-mmc-highspeed; card-detect-delay = <200>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; sd-uhs-sdr12; sd-uhs-sdr25; sd-uhs-sdr50; @@ -72,22 +75,22 @@ &i2c2 { status = "okay"; }; -&emac0 { +&mac0 { phy-mode = "sgmii"; phy-handle = <&phy0>; - phy0: ethernet-phy@8 { - reg = <8>; - ti,fifo-depth = <0x01>; - }; }; -&emac1 { +&mac1 { status = "okay"; phy-mode = "sgmii"; phy-handle = <&phy1>; phy1: ethernet-phy@9 { reg = <9>; - ti,fifo-depth = <0x01>; + ti,fifo-depth = <0x1>; + }; + phy0: ethernet-phy@8 { + reg = <8>; + ti,fifo-depth = <0x1>; }; }; diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi index c7d73756c9b8..62bd00092bcc 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -1,5 +1,5 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* Copyright (c) 2020 Microchip Technology Inc */ +/* Copyright (c) 2020-2021 Microchip Technology Inc */ /dts-v1/; #include "dt-bindings/clock/microchip,mpfs-clock.h" @@ -15,7 +15,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { compatible = "sifive,e51", "sifive,rocket0", "riscv"; device_type = "cpu"; i-cache-block-size = <64>; @@ -33,7 +33,7 @@ cpu0_intc: interrupt-controller { }; }; - cpu@1 { + cpu1: cpu@1 { compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; @@ -60,7 +60,7 @@ cpu1_intc: interrupt-controller { }; }; - cpu@2 { + cpu2: cpu@2 { compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; @@ -87,7 +87,7 @@ cpu2_intc: interrupt-controller { }; }; - cpu@3 { + cpu3: cpu@3 { compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; @@ -114,7 +114,7 @@ cpu3_intc: interrupt-controller { }; }; - cpu@4 { + cpu4: cpu@4 { compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; @@ -152,8 +152,9 @@ soc { compatible = "simple-bus"; ranges; - cache-controller@2010000 { + cctrllr: cache-controller@2010000 { compatible = "sifive,fu540-c000-ccache", "cache"; + reg = <0x0 0x2010000 0x0 0x1000>; cache-block-size = <64>; cache-level = <2>; cache-sets = <1024>; @@ -161,10 +162,9 @@ cache-controller@2010000 { cache-unified; interrupt-parent = <&plic>; interrupts = <1>, <2>, <3>; - reg = <0x0 0x2010000 0x0 0x1000>; }; - clint@2000000 { + clint: clint@2000000 { compatible = "sifive,fu540-c000-clint", "sifive,clint0"; reg = <0x0 0x2000000 0x0 0xC000>; interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, @@ -174,6 +174,15 @@ clint@2000000 { <&cpu4_intc 3>, <&cpu4_intc 7>; }; + dma@3000000 { + compatible = "sifive,fu540-c000-pdma"; + reg = <0x0 0x3000000 0x0 0x8000>; + interrupt-parent = <&plic>; + interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, + <30>; + #dma-cells = <1>; + }; + plic: interrupt-controller@c000000 { compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; reg = <0x0 0xc000000 0x0 0x4000000>; @@ -188,15 +197,6 @@ plic: interrupt-controller@c000000 { riscv,ndev = <186>; }; - dma@3000000 { - compatible = "sifive,fu540-c000-pdma"; - reg = <0x0 0x3000000 0x0 0x8000>; - interrupt-parent = <&plic>; - interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, - <30>; - #dma-cells = <1>; - }; - clkcfg: clkcfg@20002000 { compatible = "microchip,mpfs-clkcfg"; reg = <0x0 0x20002000 0x0 0x1000>; @@ -204,7 +204,7 @@ clkcfg: clkcfg@20002000 { #clock-cells = <1>; }; - serial0: serial@20000000 { + mmuart0: serial@20000000 { compatible = "ns16550a"; reg = <0x0 0x20000000 0x0 0x400>; reg-io-width = <4>; @@ -216,7 +216,7 @@ serial0: serial@20000000 { status = "disabled"; }; - serial1: serial@20100000 { + mmuart1: serial@20100000 { compatible = "ns16550a"; reg = <0x0 0x20100000 0x0 0x400>; reg-io-width = <4>; @@ -228,7 +228,7 @@ serial1: serial@20100000 { status = "disabled"; }; - serial2: serial@20102000 { + mmuart2: serial@20102000 { compatible = "ns16550a"; reg = <0x0 0x20102000 0x0 0x400>; reg-io-width = <4>; @@ -240,7 +240,7 @@ serial2: serial@20102000 { status = "disabled"; }; - serial3: serial@20104000 { + mmuart3: serial@20104000 { compatible = "ns16550a"; reg = <0x0 0x20104000 0x0 0x400>; reg-io-width = <4>; @@ -257,37 +257,36 @@ mmc: mmc@20008000 { compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc"; reg = <0x0 0x20008000 0x0 0x1000>; interrupt-parent = <&plic>; - interrupts = <88>, <89>; + interrupts = <88>; clocks = <&clkcfg CLK_MMC>; max-frequency = <200000000>; status = "disabled"; }; - emac0: ethernet@20110000 { + mac0: ethernet@20110000 { compatible = "cdns,macb"; reg = <0x0 0x20110000 0x0 0x2000>; + #address-cells = <1>; + #size-cells = <0>; interrupt-parent = <&plic>; - interrupts = <64>, <65>, <66>, <67>; + interrupts = <64>, <65>, <66>, <67>, <68>, <69>; local-mac-address = [00 00 00 00 00 00]; clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; clock-names = "pclk", "hclk"; status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; }; - emac1: ethernet@20112000 { + mac1: ethernet@20112000 { compatible = "cdns,macb"; reg = <0x0 0x20112000 0x0 0x2000>; + #address-cells = <1>; + #size-cells = <0>; interrupt-parent = <&plic>; - interrupts = <70>, <71>, <72>, <73>; + interrupts = <70>, <71>, <72>, <73>, <74>, <75>; local-mac-address = [00 00 00 00 00 00]; clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; - status = "disabled"; clock-names = "pclk", "hclk"; - #address-cells = <1>; - #size-cells = <0>; + status = "disabled"; }; - }; }; From patchwork Mon Feb 14 13:58:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 1592588 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=m32nKzQN; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4Jy5Pb4KS7z9s8s for ; Tue, 15 Feb 2022 00:57:07 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1354726AbiBNN5K (ORCPT ); Mon, 14 Feb 2022 08:57:10 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:36780 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1354712AbiBNN5H (ORCPT ); Mon, 14 Feb 2022 08:57:07 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 69AB94A901; Mon, 14 Feb 2022 05:56:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1644847017; x=1676383017; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yKN3bDJdSLql1NsGHOBK3P94QqFRIN+6Az1x7qpydu0=; b=m32nKzQNqrOnavJsEb+CTByawa26wBQnEJ1XNPdyJrI5jjPZmCX5TcFt 1ucQKqRwhHe3d9oPoqAronabj0F8eiKSFQwi9Ww3KobubZADUQ2gMwoBD a0v1V+p0LXq74ktjszo8btcXVrKqO/BaYH7lXv74BjgcZaP4rqDccdCsG 7NZ3rmMWoCtjtE1KJu8kDhMlXRH9gZpDKU7nJ9x+SwsQXnJJE4Z2Te/bp wZ/MGtiRtaPKtw0qsY8jRLRjBBPowxlZU5WnJGHEt2ZULXDyl52avCl9L doRyZsHKuObzIaVDlM8PbgNcMEOmT1LSRqzSe7bZQwRfCtMkM4FWJSQbP g==; IronPort-SDR: e+TPGn9ywsN+zYX0p17ZyY3tKI37x+iWUepeyrrmmbN/tq89hp723X0rzXHORkmWQBCT3IV80S Rr2ibLlfyf+2XrgHuWIYs0UKuOjJBolQay3oBiGIkxr8lzVVBAWvtOHThUIdViPmpnlNJSVnDY HnpQxA8M7EmKf4WlXWuzTxi51zgy8HDA35dy4a/zLQ0IuHC3bWrJ4rTnQcSxR8qaajji4lqPV4 N373/alqALUl7IxcYEXlDPXGlp0EqgXi25Pseh7VXDYHQvCkvAadkoj0rwQkHuYrR4TGC+bBqL Wljvv2nX6g/y2L/TlEUQkn1l X-IronPort-AV: E=Sophos;i="5.88,368,1635231600"; d="scan'208";a="85633821" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 14 Feb 2022 06:56:56 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 14 Feb 2022 06:56:56 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 14 Feb 2022 06:56:50 -0700 From: To: , , , , , , , , , , , , , , , , , , , CC: , , , , , Palmer Dabbelt Subject: [PATCH v7 09/11] riscv: dts: microchip: update peripherals in icicle kit device tree Date: Mon, 14 Feb 2022 13:58:39 +0000 Message-ID: <20220214135840.168236-10-conor.dooley@microchip.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220214135840.168236-1-conor.dooley@microchip.com> References: <20220214135840.168236-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Conor Dooley Assorted minor changes to the MPFS/Icicle kit device tree: - enable mmuart4 instead of mmuart0 - remove sifive pdma - split memory node to match updated fpga design - move stdout path to serial1 to avoid collision with bootloader running on the e51 Signed-off-by: Conor Dooley Acked-by: Palmer Dabbelt --- .../microchip/microchip-mpfs-icicle-kit.dts | 23 +++++++++++++------ .../boot/dts/microchip/microchip-mpfs.dtsi | 23 +++++++++++-------- 2 files changed, 29 insertions(+), 17 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts index c51bd7cf500f..dc5f351b10c4 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts @@ -18,20 +18,29 @@ aliases { serial1 = &mmuart1; serial2 = &mmuart2; serial3 = &mmuart3; + serial4 = &mmuart4; }; chosen { - stdout-path = "serial0:115200n8"; + stdout-path = "serial1:115200n8"; }; cpus { timebase-frequency = ; }; - memory@80000000 { + ddrc_cache_lo: memory@80000000 { device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x40000000>; + reg = <0x0 0x80000000 0x0 0x2e000000>; clocks = <&clkcfg CLK_DDRC>; + status = "okay"; + }; + + ddrc_cache_hi: memory@1000000000 { + device_type = "memory"; + reg = <0x10 0x0 0x0 0x40000000>; + clocks = <&clkcfg CLK_DDRC>; + status = "okay"; }; }; @@ -39,10 +48,6 @@ &refclk { clock-frequency = <600000000>; }; -&mmuart0 { - status = "okay"; -}; - &mmuart1 { status = "okay"; }; @@ -55,6 +60,10 @@ &mmuart3 { status = "okay"; }; +&mmuart4 { + status = "okay"; +}; + &mmc { status = "okay"; diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi index 62bd00092bcc..5e7aaaf42cde 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -174,15 +174,6 @@ clint: clint@2000000 { <&cpu4_intc 3>, <&cpu4_intc 7>; }; - dma@3000000 { - compatible = "sifive,fu540-c000-pdma"; - reg = <0x0 0x3000000 0x0 0x8000>; - interrupt-parent = <&plic>; - interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, - <30>; - #dma-cells = <1>; - }; - plic: interrupt-controller@c000000 { compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; reg = <0x0 0xc000000 0x0 0x4000000>; @@ -213,7 +204,7 @@ mmuart0: serial@20000000 { interrupts = <90>; current-speed = <115200>; clocks = <&clkcfg CLK_MMUART0>; - status = "disabled"; + status = "disabled"; /* Reserved for the HSS */ }; mmuart1: serial@20100000 { @@ -252,6 +243,18 @@ mmuart3: serial@20104000 { status = "disabled"; }; + mmuart4: serial@20106000 { + compatible = "ns16550a"; + reg = <0x0 0x20106000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = <94>; + clocks = <&clkcfg CLK_MMUART4>; + current-speed = <115200>; + status = "disabled"; + }; + /* Common node entry for emmc/sd */ mmc: mmc@20008000 { compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc"; From patchwork Mon Feb 14 13:58:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 1592592 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=lET4Qx9I; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4Jy5QK6Gtqz9s0r for ; Tue, 15 Feb 2022 00:57:45 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1354771AbiBNN5q (ORCPT ); Mon, 14 Feb 2022 08:57:46 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:37304 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343764AbiBNN5W (ORCPT ); Mon, 14 Feb 2022 08:57:22 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 951D74A3C7; Mon, 14 Feb 2022 05:57:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1644847025; x=1676383025; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Az3RA6+hovCiv6ooXMrh50hd2AKqnttWpCfcnA51fdM=; b=lET4Qx9IoywGNglsD94TQa/wuilPh7HpGXVEP9EQLYro5JP/1ebez/eZ gP2VE4qxGtLS3qNxgmbTbYiW3oVggeKtOBg5v6ogDN3/T0oDJG1wdfN6g cxjwnk9rHphTLBpxPPjcGSmoziIB56iJxSH4QP+JzPw51jwAXyVgquXas Hab4s7bIjNdEDmU0ipztVzFrk0q6zjOYf+q4Z9QKcU3qtJVky5fivSA2m vG23xU35tW/eM1/PELU0QsrkrjsyGUV5RseokbBFbpROSxHFHNF7gv7EU SWtw7NtjDkrIpDKZ3t0WGqQIfIaanMbXOfXljzAcmrDqJArRZDmi0PpDC g==; IronPort-SDR: 23b8g69cCp39n+M0lXikT0EUvd8/Qv6py1nP9AEmiGo0g5WpZuD/W0uJxr1yM+RdUU+WfDcjFp EC34/lCs730rCTr35fgYNRnx5WDGOYNOxrj+L2kE2WizYB2ytpf/8cd0gKPF4ZnmFT4F/gCNjg gf1c6Y4eDrk598MAlpJ2ehz/wtvSv5qTfocW5p7IDGVvXv28HBX09n3XlyoUFSwPoeVAbBrNGQ UIf60S04A04t68vTUKCrSEc0kACVfUMYOF0Y26Bl67bHOB5Dpq+EEIP800z/DKIq5Dr6L3HrY3 hw7ZqyOPKBOmgq31u4dt2ART X-IronPort-AV: E=Sophos;i="5.88,368,1635231600"; d="scan'208";a="145879847" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 14 Feb 2022 06:57:03 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 14 Feb 2022 06:57:02 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 14 Feb 2022 06:56:56 -0700 From: To: , , , , , , , , , , , , , , , , , , , CC: , , , , , Palmer Dabbelt Subject: [PATCH v7 10/11] riscv: dts: microchip: add new peripherals to icicle kit device tree Date: Mon, 14 Feb 2022 13:58:40 +0000 Message-ID: <20220214135840.168236-11-conor.dooley@microchip.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220214135840.168236-1-conor.dooley@microchip.com> References: <20220214135840.168236-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Conor Dooley Add new peripherals to the MPFS, and enable them in the Icicle kit device tree: 2x SPI, QSPI, 3x GPIO, 2x I2C, Real Time Counter, PCIE controller, USB host & system controller. Signed-off-by: Conor Dooley Acked-by: Palmer Dabbelt --- .../microchip/microchip-mpfs-icicle-kit.dts | 53 ++++++ .../boot/dts/microchip/microchip-mpfs.dtsi | 160 ++++++++++++++++++ 2 files changed, 213 insertions(+) diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts index dc5f351b10c4..cd2fe80fa81a 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts @@ -80,6 +80,26 @@ &mmc { sd-uhs-sdr104; }; +&spi0 { + status = "okay"; +}; + +&spi1 { + status = "okay"; +}; + +&qspi { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + &i2c2 { status = "okay"; }; @@ -103,6 +123,39 @@ phy0: ethernet-phy@8 { }; }; +&gpio2 { + interrupts = <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>; + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&usb { + status = "okay"; + dr_mode = "host"; +}; + +&mbox { + status = "okay"; +}; + +&syscontroller { + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + &core_pwm0 { status = "okay"; }; diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi index 5e7aaaf42cde..c5c9d1360de0 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -266,6 +266,66 @@ mmc: mmc@20008000 { status = "disabled"; }; + spi0: spi@20108000 { + compatible = "microchip,mpfs-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x20108000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <54>; + clocks = <&clkcfg CLK_SPI0>; + spi-max-frequency = <25000000>; + status = "disabled"; + }; + + spi1: spi@20109000 { + compatible = "microchip,mpfs-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x20109000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <55>; + clocks = <&clkcfg CLK_SPI1>; + spi-max-frequency = <25000000>; + status = "disabled"; + }; + + qspi: spi@21000000 { + compatible = "microchip,mpfs-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x21000000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <85>; + clocks = <&clkcfg CLK_QSPI>; + spi-max-frequency = <25000000>; + status = "disabled"; + }; + + i2c0: i2c@2010a000 { + compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7"; + reg = <0x0 0x2010a000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&plic>; + interrupts = <58>; + clocks = <&clkcfg CLK_I2C0>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c1: i2c@2010b000 { + compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7"; + reg = <0x0 0x2010b000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&plic>; + interrupts = <61>; + clocks = <&clkcfg CLK_I2C1>; + clock-frequency = <100000>; + status = "disabled"; + }; + mac0: ethernet@20110000 { compatible = "cdns,macb"; reg = <0x0 0x20110000 0x0 0x2000>; @@ -291,5 +351,105 @@ mac1: ethernet@20112000 { clock-names = "pclk", "hclk"; status = "disabled"; }; + + gpio0: gpio@20120000 { + compatible = "microchip,mpfs-gpio"; + reg = <0x0 0x20120000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupt-controller; + #interrupt-cells = <1>; + clocks = <&clkcfg CLK_GPIO0>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + gpio1: gpio@20121000 { + compatible = "microchip,mpfs-gpio"; + reg = <000 0x20121000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupt-controller; + #interrupt-cells = <1>; + clocks = <&clkcfg CLK_GPIO1>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + gpio2: gpio@20122000 { + compatible = "microchip,mpfs-gpio"; + reg = <0x0 0x20122000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupt-controller; + #interrupt-cells = <1>; + clocks = <&clkcfg CLK_GPIO2>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + rtc: rtc@20124000 { + compatible = "microchip,mpfs-rtc"; + reg = <0x0 0x20124000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <80>, <81>; + clocks = <&clkcfg CLK_RTC>; + clock-names = "rtc"; + status = "disabled"; + }; + + usb: usb@20201000 { + compatible = "microchip,mpfs-musb"; + reg = <0x0 0x20201000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <86>, <87>; + clocks = <&clkcfg CLK_USB>; + interrupt-names = "dma","mc"; + status = "disabled"; + }; + + pcie: pcie@2000000000 { + compatible = "microchip,pcie-host-1.0"; + #address-cells = <0x3>; + #interrupt-cells = <0x1>; + #size-cells = <0x2>; + device_type = "pci"; + reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; + reg-names = "cfg", "apb"; + bus-range = <0x0 0x7f>; + interrupt-parent = <&plic>; + interrupts = <119>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + interrupt-map-mask = <0 0 0 7>; + clocks = <&clkcfg CLK_FIC0>, <&clkcfg CLK_FIC1>, <&clkcfg CLK_FIC3>; + clock-names = "fic0", "fic1", "fic3"; + ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; + msi-parent = <&pcie>; + msi-controller; + microchip,axi-m-atr0 = <0x10 0x0>; + status = "disabled"; + pcie_intc: legacy-interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + mbox: mailbox@37020000 { + compatible = "microchip,mpfs-mailbox"; + reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>; + interrupt-parent = <&plic>; + interrupts = <96>; + #mbox-cells = <1>; + status = "disabled"; + }; + + syscontroller: syscontroller { + compatible = "microchip,mpfs-sys-controller"; + mboxes = <&mbox 0>; + }; }; }; From patchwork Mon Feb 14 13:58:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 1592595 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=WmQHAx+C; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4Jy5QN3kq3z9s0r for ; Tue, 15 Feb 2022 00:57:48 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1354796AbiBNN5v (ORCPT ); Mon, 14 Feb 2022 08:57:51 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:37588 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1354666AbiBNN5W (ORCPT ); Mon, 14 Feb 2022 08:57:22 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3197C4A90B; Mon, 14 Feb 2022 05:57:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1644847029; x=1676383029; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MUwu9Fdq/MRDAHV6UL3afCTA6/6dxR2I/gfuI0/01w0=; b=WmQHAx+COFzzHioV+l5+6P6XvNaC9cb1e+KnDS4oQyJC40mWGONOPhkn 4ut2Np2fRbmr/UIFS1uLbX6unAn8gbebD7quu+AxXdqvnXSQFmA4G3l/r 9JqeJlFAB2RM/NEGIgDvbNeXVNyfALBWQOgo+uz41Fwr1HZWRJY14Sq9O 4+P3yUwV1x1sA7RYN1wrj8zAquvt3SZIPXrL0TcsB7aJ1QXZNCGvZiApc l5gxAaQt7BLtJ8Ch2YzgJ5r0LL1sV/blTTpj7uvzD72NyXifXYgCnFKUZ LCpc8nURzSV0EmrrndMsuIY/ou9GEXnWhGjvcH2p4pahZ9GrxJk3v3NzS Q==; IronPort-SDR: kdqWLspQOOwf9G7rdt6GXhstA0tSrtetAQSQuUrB+kVWOTXjZ1u4sreZnGJiur6ujtgNfNlRWO ylnJnPTm8+Rj8P/JZ+VrZlCPwryivA9NBVMi17O/ZDaXZCssECByaiB/KhUb+wydCiekXzb1fh oR6zXRx1+NdZrvDMfCqXTb6g8s+ApLr8e5PloqnFMvlC7fKHXZLKqRm6vC1EpKqgHH7rJWSjPP wLmS46L8/NtCIzQHPeFEIp/BnLi/Gs4OzsUzuTuPnGA7b4gDgmnrtPVYNb/hKxFsqLwu23eTXt kpN2CztfMqj/piID4UfB5nY4 X-IronPort-AV: E=Sophos;i="5.88,368,1635231600"; d="scan'208";a="152982610" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 14 Feb 2022 06:57:08 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 14 Feb 2022 06:57:07 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 14 Feb 2022 06:57:02 -0700 From: To: , , , , , , , , , , , , , , , , , , , CC: , , , , , Palmer Dabbelt Subject: [PATCH v7 11/11] MAINTAINERS: update riscv/microchip entry Date: Mon, 14 Feb 2022 13:58:41 +0000 Message-ID: <20220214135840.168236-12-conor.dooley@microchip.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220214135840.168236-1-conor.dooley@microchip.com> References: <20220214135840.168236-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Conor Dooley Update the RISC-V/Microchip entry by adding the microchip dts directory and myself as maintainer Reviewed-by: Lewis Hanly Signed-off-by: Conor Dooley Acked-by: Palmer Dabbelt --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index ea3e6c914384..779a550dc95b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16575,8 +16575,10 @@ K: riscv RISC-V/MICROCHIP POLARFIRE SOC SUPPORT M: Lewis Hanly +M: Conor Dooley L: linux-riscv@lists.infradead.org S: Supported +F: arch/riscv/boot/dts/microchip/ F: drivers/mailbox/mailbox-mpfs.c F: drivers/soc/microchip/ F: include/soc/microchip/mpfs.h