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[73.63.24.84]) by smtp.gmail.com with ESMTPSA id k12sm21467138pfc.107.2022.02.09.11.14.22 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 09 Feb 2022 11:14:23 -0800 (PST) Message-ID: <9429e5eb-086a-baaf-f984-594cba8cc3c4@gmail.com> Date: Wed, 9 Feb 2022 12:14:21 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.5.1 Content-Language: en-US Subject: [committed][target/97040] Avoid using predefined insn name for instruction with different semantics To: GCC Patches X-Spam-Status: No, score=-8.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jeff Law via Gcc-patches From: Jeff Law Reply-To: Jeff Law Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" This isn't technically a regression, but it only impacts the v850 target and fixes a long standing code correctness issue. As outlined in slightly more detail in the PR, the v850 is using the pattern name "fnmasf4" and "fnmssf4" to generate fnmaf.s and fnmsf.s instructions respectively. Unfortunately fnmasf4 is expected to produce (-a * b) + c and fnmssf4 (-a * b) - c.  Those v850 instructions actually negate the entire result. The fix is trivial.  Use a different pattern name so that the combiner can still generate those instructions, but prevent those instructions from being used to implement GCC's notion of what fnmas and fnmss should be. This fixes pr97040 as well as a handful of testsuite failures for the v3e5 multilib. Committed to the trunk. Jeff commit eefec38c992e3622a69de9667e91f0cafbff03cc Author: Jeff Law Date: Wed Feb 9 14:10:53 2022 -0500 Avoid using predefined insn name for instruction with different semantics This isn't technically a regression, but it only impacts the v850 target and fixes a long standing code correctness issue. As outlined in slightly more detail in the PR, the v850 is using the pattern name "fnmasf4" and "fnmssf4" to generate fnmaf.s and fnmsf.s instructions respectively. Unfortunately fnmasf4 is expected to produce (-a * b) + c and fnmssf4 (-a * b) - c. Those v850 instructions actually negate the entire result. The fix is trivial. Use a different pattern name so that the combiner can still generate those instructions, but prevent those instructions from being used to implement GCC's notion of what fnmas and fnmss should be. This fixes pr97040 as well as a handful of testsuite failures for the v3e5 multilib. gcc/ PR target/97040 * config/v850/v850.md (*v850_fnmasf4): Renamed from fnmasf4. (*v850_fnmssf4): Renamed from fnmssf4 diff --git a/gcc/config/v850/v850.md b/gcc/config/v850/v850.md index ed51157691b..6ca31e3f43f 100644 --- a/gcc/config/v850/v850.md +++ b/gcc/config/v850/v850.md @@ -2601,7 +2601,12 @@ (set_attr "type" "fpu")]) ;;; negative-multiply-add -(define_insn "fnmasf4" +;; Note the name on this and the following insn were previously fnmasf4 +;; and fnmssf4. Those names are known to the gimple->rtl expanders and +;; must implement specific semantics (negating one of the inputs to the +;; multiplication). The v850 instructions actually negate the entire +;; result. Thus the names have been changed and hidden. +(define_insn "*v850_fnmasf4" [(set (match_operand:SF 0 "register_operand" "=r") (neg:SF (fma:SF (match_operand:SF 1 "register_operand" "r") (match_operand:SF 2 "register_operand" "r") @@ -2612,7 +2617,7 @@ (set_attr "type" "fpu")]) ;; negative-multiply-subtract -(define_insn "fnmssf4" +(define_insn "*v850_fnmssf4" [(set (match_operand:SF 0 "register_operand" "=r") (neg:SF (fma:SF (match_operand:SF 1 "register_operand" "r") (match_operand:SF 2 "register_operand" "r")