From patchwork Wed Feb 2 18:22:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hari Nagalla X-Patchwork-Id: 1587756 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=UZVq0JTd; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4Jpqt81VpVz9sCD for ; Thu, 3 Feb 2022 05:23:12 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id D40CA839F1; Wed, 2 Feb 2022 19:22:36 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="UZVq0JTd"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 461D68390B; Wed, 2 Feb 2022 19:22:33 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.2 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 2E2E0838FC for ; Wed, 2 Feb 2022 19:22:26 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=hnagalla@ti.com Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 212IMOCm044270 for ; Wed, 2 Feb 2022 12:22:24 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1643826144; bh=KvJq3Pmg5dKO7u2YVl1hWCpFjgemSCCHLGEqRKUWA6k=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=UZVq0JTd6oqLcWbkqbhfL9MpSiR/P2dWNoLkL5Txvwsi6gYiNnHx1uRka3ybY2byo b8nO7d/hb+C7dXdJ6yndHQdsFiyset84H6UOfK4S/1m/kICZ/K1qdOyNlG+5kiZCX1 dGv+xUApzvdG1SrmhD3z/xfhhSeID2/6GBMNmobk= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 212IMOwD013280 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL) for ; Wed, 2 Feb 2022 12:22:24 -0600 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Wed, 2 Feb 2022 12:22:24 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Wed, 2 Feb 2022 12:22:24 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 212IMOEJ110828; Wed, 2 Feb 2022 12:22:24 -0600 From: Hari Nagalla To: CC: Subject: [PATCH v1 1/4] misc: k3_esm: Add functionality to set and route error events within K3SoC Date: Wed, 2 Feb 2022 12:22:20 -0600 Message-ID: <20220202182223.16521-2-hnagalla@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220202182223.16521-1-hnagalla@ti.com> References: <20220202182223.16521-1-hnagalla@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Add functionality to enable, set priority to the input events and to route to MCU ESM. On AM64x/AM62x devices, it is possible to route Main ESM0 error events to MCU ESM. When these error events are routed to MCU ESM high output, it can trigger the reset logic to reset the device, when CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RESET_EN_Z is set to '0'. Signed-off-by: Hari Nagalla --- drivers/misc/k3_esm.c | 53 ++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 50 insertions(+), 3 deletions(-) diff --git a/drivers/misc/k3_esm.c b/drivers/misc/k3_esm.c index cc2a23dd66..41faeb3d85 100644 --- a/drivers/misc/k3_esm.c +++ b/drivers/misc/k3_esm.c @@ -16,17 +16,57 @@ #define ESM_SFT_RST 0x0c #define ESM_SFT_RST_KEY 0x0f +#define ESM_EN 0x08 +#define ESM_EN_KEY 0x0f #define ESM_STS(i) (0x404 + (i) / 32 * 0x20) +#define ESM_STS_MASK(i) (1 << ((i) % 32)) #define ESM_PIN_EN_SET_OFFSET(i) (0x414 + (i) / 32 * 0x20) -#define ESM_PIN_MASK(i) BIT((i) & 0x1f) +#define ESM_PIN_MASK(i) (1 << ((i) % 32)) +#define ESM_INTR_EN_SET_OFFSET(i) (0x408 + (i) / 32 * 0x20) +#define ESM_INTR_MASK(i) (1 << ((i) % 32)) +#define ESM_INTR_PRIO_SET_OFFSET(i) (0x410 + (i) / 32 * 0x20) +#define ESM_INTR_PRIO_MASK(i) (1 << ((i) % 32)) static void esm_pin_enable(void __iomem *base, int pin) { + u32 value; + + value = readl(base + ESM_PIN_EN_SET_OFFSET(pin)); + value |= ESM_PIN_MASK(pin); /* Enable event */ - writel(ESM_PIN_MASK(pin), base + ESM_PIN_EN_SET_OFFSET(pin)); + writel(value, base + ESM_PIN_EN_SET_OFFSET(pin)); +} + +static void esm_intr_enable(void __iomem *base, int pin) +{ + u32 value; + + value = readl(base + ESM_INTR_EN_SET_OFFSET(pin)); + value |= ESM_INTR_MASK(pin); + /* Enable Interrupt event */ + writel(value, base + ESM_INTR_EN_SET_OFFSET(pin)); +} + +static void esm_intr_prio_set(void __iomem *base, int pin) +{ + u32 value; + + value = readl(base + ESM_INTR_PRIO_SET_OFFSET(pin)); + value |= ESM_INTR_PRIO_MASK(pin); + /* Set to priority */ + writel(value, base + ESM_INTR_PRIO_SET_OFFSET(pin)); } +static void esm_clear_raw_status(void __iomem *base, int pin) +{ + u32 value; + + value = readl(base + ESM_STS(pin)); + value |= ESM_STS_MASK(pin); + /* Clear Event status */ + writel(value, base + ESM_STS(pin)); +} /** * k3_esm_probe: configures ESM based on DT data * @@ -67,8 +107,15 @@ static int k3_esm_probe(struct udevice *dev) /* Clear any pending events */ writel(ESM_SFT_RST_KEY, base + ESM_SFT_RST); - for (i = 0; i < num_pins; i++) + for (i = 0; i < num_pins; i++) { + esm_intr_prio_set(base, pins[i]); + esm_clear_raw_status(base, pins[i]); esm_pin_enable(base, pins[i]); + esm_intr_enable(base, pins[i]); + } + + /* Enable ESM */ + writel(ESM_EN_KEY, base + ESM_EN); free_pins: kfree(pins); From patchwork Wed Feb 2 18:22:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hari Nagalla X-Patchwork-Id: 1587753 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=n+SneCRH; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; 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Wed, 2 Feb 2022 12:22:24 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Wed, 2 Feb 2022 12:22:24 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 212IMOQq072836; Wed, 2 Feb 2022 12:22:24 -0600 From: Hari Nagalla To: CC: Subject: [PATCH v1 2/4] arm: dts: k3-am64: Add support for ESM device nodes Date: Wed, 2 Feb 2022 12:22:21 -0600 Message-ID: <20220202182223.16521-3-hnagalla@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220202182223.16521-1-hnagalla@ti.com> References: <20220202182223.16521-1-hnagalla@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Enable acces to ESM0 configuration space and add Main ESM0 and MCU ESM nodes to the AM64 device tree. Signed-off-by: Hari Nagalla Reviewed-by: Christian Gmeiner --- arch/arm/dts/k3-am64.dtsi | 1 + arch/arm/dts/k3-am642-r5-evm.dts | 19 +++++++++++++++++++ arch/arm/dts/k3-am642-r5-sk.dts | 19 +++++++++++++++++++ 3 files changed, 39 insertions(+) diff --git a/arch/arm/dts/k3-am64.dtsi b/arch/arm/dts/k3-am64.dtsi index de6805b0c7..7aa94d5a6e 100644 --- a/arch/arm/dts/k3-am64.dtsi +++ b/arch/arm/dts/k3-am64.dtsi @@ -64,6 +64,7 @@ #address-cells = <2>; #size-cells = <2>; ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */ + <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */ <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */ diff --git a/arch/arm/dts/k3-am642-r5-evm.dts b/arch/arm/dts/k3-am642-r5-evm.dts index cc48fd4cb6..3ea6471e94 100644 --- a/arch/arm/dts/k3-am642-r5-evm.dts +++ b/arch/arm/dts/k3-am642-r5-evm.dts @@ -82,6 +82,25 @@ }; }; +&cbass_main { + main_esm: esm@420000 { + compatible = "ti,j721e-esm"; + reg = <0x0 0x420000 0x0 0x1000>; + ti,esm-pins = <160>, <161>; + u-boot,dm-spl; + }; +}; + +&cbass_mcu { + u-boot,dm-spl; + mcu_esm: esm@4100000 { + compatible = "ti,j721e-esm"; + reg = <0x0 0x4100000 0x0 0x1000>; + ti,esm-pins = <0>, <1>; + u-boot,dm-spl; + }; +}; + &main_pmx0 { u-boot,dm-spl; main_uart0_pins_default: main-uart0-pins-default { diff --git a/arch/arm/dts/k3-am642-r5-sk.dts b/arch/arm/dts/k3-am642-r5-sk.dts index 7d1cb85615..1f96e3fcac 100644 --- a/arch/arm/dts/k3-am642-r5-sk.dts +++ b/arch/arm/dts/k3-am642-r5-sk.dts @@ -75,6 +75,25 @@ }; }; +&cbass_main { + main_esm: esm@420000 { + compatible = "ti,j721e-esm"; + reg = <0x0 0x420000 0x0 0x1000>; + ti,esm-pins = <160>, <161>; + u-boot,dm-spl; + }; +}; + +&cbass_mcu { + u-boot,dm-spl; + mcu_esm: esm@4100000 { + compatible = "ti,j721e-esm"; + reg = <0x0 0x4100000 0x0 0x1000>; + ti,esm-pins = <0>, <1>; + u-boot,dm-spl; + }; +}; + &main_pmx0 { u-boot,dm-spl; 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Wed, 2 Feb 2022 12:22:25 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Wed, 2 Feb 2022 12:22:25 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 212IMPH5072858; Wed, 2 Feb 2022 12:22:25 -0600 From: Hari Nagalla To: CC: Subject: [PATCH v1 3/4] arch: arm: mach-k3: am642_init: Probe ESM nodes Date: Wed, 2 Feb 2022 12:22:22 -0600 Message-ID: <20220202182223.16521-4-hnagalla@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220202182223.16521-1-hnagalla@ti.com> References: <20220202182223.16521-1-hnagalla@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean On AM64x devices, it is possible to route Main ESM0 error events to MCU ESM. MCU ESM high error output can trigger the reset logic to reset the device. So, for these devices we expect two ESM device nodes in the device tree, one for Main ESM and the another MCU ESM in the device tree. When these ESM device nodes are properly configired it is possible to route the Main RTI0 WWDT output to the MCU ESM high ouput through Main ESM and trigger a device reset when CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RESET_EN_Z is set to '0'. On K3 AM64x devices, the R5 SPL u-boot handles the ESM device node configurations. Signed-off-by: Hari Nagalla --- arch/arm/mach-k3/am642_init.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c index 543dea02bc..cb9495e525 100644 --- a/arch/arm/mach-k3/am642_init.c +++ b/arch/arm/mach-k3/am642_init.c @@ -24,6 +24,8 @@ #include #if defined(CONFIG_SPL_BUILD) +#define MCU_CTRL_MMR0_BASE 0x04500000 +#define CTRLMMR_MCU_RST_CTRL 0x04518170 static void ctrl_mmr_unlock(void) { @@ -42,6 +44,17 @@ static void ctrl_mmr_unlock(void) mmr_unlock(MCU_PADCFG_MMR1_BASE, 1); } +static void mcu_ctrl_mmr_unlock(void) +{ + /* Unlock all MCU_CTRL_MMR0 module registers */ + mmr_unlock(MCU_CTRL_MMR0_BASE, 0); + mmr_unlock(MCU_CTRL_MMR0_BASE, 1); + mmr_unlock(MCU_CTRL_MMR0_BASE, 2); + mmr_unlock(MCU_CTRL_MMR0_BASE, 3); + mmr_unlock(MCU_CTRL_MMR0_BASE, 4); + mmr_unlock(MCU_CTRL_MMR0_BASE, 6); +} + /* * This uninitialized global variable would normal end up in the .bss section, * but the .bss is cleared between writing and reading this variable, so move @@ -160,6 +173,9 @@ void board_init_f(ulong dummy) store_boot_info_from_rom(); ctrl_mmr_unlock(); + mcu_ctrl_mmr_unlock(); + + enable_mcu_esm_reset(); /* Init DM early */ spl_early_init(); @@ -194,6 +210,18 @@ void board_init_f(ulong dummy) /* Output System Firmware version info */ k3_sysfw_print_ver(); +#ifdef CONFIG_ESM_K3 + /* Probe/configure ESM0 */ + ret = uclass_get_device_by_name(UCLASS_MISC, "esm@420000", &dev); + if (ret) + printf("esm main init failed: %d\n", ret); + + /* Probe/configure MCUESM */ + ret = uclass_get_device_by_name(UCLASS_MISC, "esm@4100000", &dev); + if (ret) + printf("esm mcu init failed: %d\n", ret); +#endif + #if defined(CONFIG_K3_AM64_DDRSS) ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) From patchwork Wed Feb 2 18:22:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hari Nagalla X-Patchwork-Id: 1587754 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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Wed, 2 Feb 2022 12:22:25 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 212IMPCr019571; Wed, 2 Feb 2022 12:22:25 -0600 From: Hari Nagalla To: CC: Subject: [PATCH v1 4/4] configs: am64x_evm_r5_defconfig: Add support for ESM Date: Wed, 2 Feb 2022 12:22:23 -0600 Message-ID: <20220202182223.16521-5-hnagalla@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220202182223.16521-1-hnagalla@ti.com> References: <20220202182223.16521-1-hnagalla@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Enable ESM driver for AM64x R5 SPL/u-boot builds. Signed-off-by: Hari Nagalla Reviewed-by: Christian Gmeiner --- configs/am64x_evm_r5_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig index 61138dd1a9..e29e99c2d1 100644 --- a/configs/am64x_evm_r5_defconfig +++ b/configs/am64x_evm_r5_defconfig @@ -103,6 +103,7 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_OMAP24XX=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y +CONFIG_ESM_K3=y CONFIG_SPL_MISC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y