From patchwork Sat Jan 29 11:52:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 1586100 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.a=rsa-sha256 header.s=badeba3b8450 header.b=gJ4oIxK9; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4JmCW53tqMz9sRR for ; Sat, 29 Jan 2022 22:57:37 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241529AbiA2L5e (ORCPT ); Sat, 29 Jan 2022 06:57:34 -0500 Received: from mout.gmx.net ([212.227.15.18]:60127 "EHLO mout.gmx.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240332AbiA2L5e (ORCPT ); Sat, 29 Jan 2022 06:57:34 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1643457446; bh=jI07oj6ZQKZI4SXgpi5iludWDQoXodJQyaeDRlTbCts=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=gJ4oIxK9rVzKDBcpkf+20Gj+/iYCpB/Atx1VVrPPCh0zNg8+2PWj3sJm0GWsDfC0F KnV4sUE5BSoY56q3M+Mv4OI5BuciU1dK7tA9mG6fBRhxEcpJxFALsWf+667GcXWQPb HbUA/HwuIonalH/7VlhxghqZZv3N7PWcHPO1LZGU= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([5.146.194.160]) by mail.gmx.net (mrgmx005 [212.227.17.190]) with ESMTPSA (Nemesis) id 1MxUnz-1mKilj2IyP-00xwKK; Sat, 29 Jan 2022 12:57:26 +0100 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Cc: Linus Walleij , Rob Herring , openbmc@lists.ozlabs.org, Tomer Maimon , Joel Stanley , linux-kernel@vger.kernel.org, Andy Shevchenko , Avi Fishman , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Rob Herring Subject: [PATCH v5 1/9] dt-bindings: arm/npcm: Add binding for global control registers (GCR) Date: Sat, 29 Jan 2022 12:52:20 +0100 Message-Id: <20220129115228.2257310-2-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220129115228.2257310-1-j.neuschaefer@gmx.net> References: <20220129115228.2257310-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:02EDbgw1aWo9wwZ2hCE2GRIiaSUQ04z/cHtTktAVudX4/RIbZry 8loU3I8s1IpTPaA9Bdi/N54iuGnis79b6JO1dQnH72ZoUzjfR5si+pRrzmLMhBUtsY+OYiz fE+/yXtezAgzBT+X/TyFeB1m4BszI1ZySOZwX5p8iG70geceiobxhDsOTbze9uyJE5NZ/ca ZRI6toxGGQzhcBTM6Rs7A== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1;V03:K0:jPAjAyxpmtE=:eOzq2mUyQpGbvQ6lsLzcMV Qaa4Bna/j9J78/ULZoZTWi5CrIkp2i9V3O3JH2M6irxclEQImaFTYmrG68xSfJ35n5qCCyf0K zFhlsMTj3Jm0g2eGMcOLDZjWlTjDcqqQTKdvcxRn+fXfVJDWg1t8DHt1eU8RdDoLdqAflPcvS RSjlHyguKQrgqx20iicgt7UYScyToCsJozDXN38mwAvzR73e7Tc5cxbqQL60aK3TmEEmxLVHQ PNYHYUuBdT1AbBznXVBy2bUljS7M0l+i23huysvcLGE9RACiC6McclQVd7Jfb6BFC08lMUhU1 mfSW/6bg6oyOr5MvbFCP8nauTEj+nhISe3BedaiwMDbse16zKdZen1JHPYZYq3BfLqMIjculO 8jIcwER5gVr36xgJkDw1CjUfZfWiZL0TijtHilxK3tkJ2rjre1QrUa34V8Hk1+WE465OoNYQG UVEiH3BiWqX2e01AQWTLnzTJAGgdPiZFyJZinnFztwR7Uk/iYb5hAytY5mmu6okSavEufTx2W D3r7fmXL1amkYndQFeNQwCw8/92NeT/rZihpLZteCnbEbD0Onb5HNnuscT/OU7meVbrQC7Z41 vg/6iM+aq9SpVo5ItL34RkosFyTeaaKsEZLyq6jnLuxUcRYExbRZzsaCsc3dccxP0XEeE4nvq 9elrmI/kyOdfDBj1urT3rVVe9L57pA7c0OD4qW9vXZRkKY0n6ot0kxCF5guZIaIMDmNoffNFt U9ZPPYnx1kquCzjLz4yzQ9deXkkF0nOvzybumJ3Df5I8gl3+YbSUuYLEIvci7UCmECvQLaXMR RH9gFC1QrHygDi2dH33bxoZjITRV+4uUnvmpNzm3/Cq0xB2JxHt0g/b/1KFFEhnkwgn72/3e0 +CSknAqVrqvP9QK5K+3glj/s/rC98EM9xSXsU2hu8jNFSotVY0bxK/oz0CS7BV9AGe4LsjQHa RdQs5rJemIIG1C0Hd7ErsGSKwNlJs6jYiw7TF1yabOaboEND/CJu06xVgkdxLvp5sbv1PGxQ4 4VSWon1mnW0yHeSdoWnjHoMdoHsXb0LqdCvRfgjRmFWejQsbWBufK3FhyVNU1yzFKDhHNHPnJ uh/V+v0ids5Qw4= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org A nuvoton,*-gcr node is present in nuvoton-common-npcm7xx.dtsi and will be added to nuvoton-wpcm450.dtsi. It is necessary for the NPCM7xx and WPCM450 pinctrl drivers, and may later be used to retrieve SoC model and version information. This patch adds a binding to describe this node. Signed-off-by: Jonathan Neuschäfer Reviewed-by: Rob Herring --- v5: - no changes v4: - Add Rob's R-b v3: - Make a few changes suggested by Rob Herring - Change name of mux-controller node to appease the linter v2: - https://lore.kernel.org/lkml/20211207210823.1975632-2-j.neuschaefer@gmx.net/ - Rename node in example to syscon@800000 - Add subnode to example v1: - https://lore.kernel.org/lkml/20210602120329.2444672-2-j.neuschaefer@gmx.net/ --- .../bindings/arm/npcm/nuvoton,gcr.yaml | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml -- 2.34.1 diff --git a/Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml b/Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml new file mode 100644 index 0000000000000..fcb211add7d37 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/npcm/nuvoton,gcr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Global Control Registers block in Nuvoton SoCs + +maintainers: + - Jonathan Neuschäfer + +description: + The Global Control Registers (GCR) are a block of registers in Nuvoton SoCs + that expose misc functionality such as chip model and version information or + pinmux settings. + +properties: + compatible: + items: + - enum: + - nuvoton,wpcm450-gcr + - nuvoton,npcm750-gcr + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: + type: object + +examples: + - | + gcr: syscon@800000 { + compatible = "nuvoton,npcm750-gcr", "syscon", "simple-mfd"; + reg = <0x800000 0x1000>; + + mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x38 0x07>; + idle-states = <2>; + }; + }; From patchwork Sat Jan 29 11:52:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 1586115 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.a=rsa-sha256 header.s=badeba3b8450 header.b=dTZjRS9j; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4JmCYS0m0kz9t25 for ; Sat, 29 Jan 2022 22:59:40 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235740AbiA2L7h (ORCPT ); Sat, 29 Jan 2022 06:59:37 -0500 Received: from mout.gmx.net ([212.227.17.20]:40903 "EHLO mout.gmx.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242175AbiA2L5m (ORCPT ); Sat, 29 Jan 2022 06:57:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1643457452; bh=cntpS7zEiYV12x5rJXS1Tqn/MpedloZ0hFjM6XbqZjc=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=dTZjRS9jGMzUqQkt6fCEuz13y/GR8MDy5Y5RXzrE+1QKpqXv8H0QG/kvI1Zr+NNg2 lSbezfTHlLPJpN0CWfY7GS1eMSlSZSM2g7eNuF9kqZOcKj6PFF/VMS/S/82Qm2G5qt a9HmWf2U5PfPb7jA0CLJpKuo8udO+rDJaSf/c9Bs= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([5.146.194.160]) by mail.gmx.net (mrgmx104 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MK3Rm-1mxtOk1Ije-00LV8A; Sat, 29 Jan 2022 12:57:32 +0100 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Cc: Linus Walleij , Rob Herring , openbmc@lists.ozlabs.org, Tomer Maimon , Joel Stanley , linux-kernel@vger.kernel.org, Andy Shevchenko , Avi Fishman , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Rob Herring Subject: [PATCH v5 4/9] dt-bindings: pinctrl: Add Nuvoton WPCM450 Date: Sat, 29 Jan 2022 12:52:23 +0100 Message-Id: <20220129115228.2257310-5-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220129115228.2257310-1-j.neuschaefer@gmx.net> References: <20220129115228.2257310-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:p75bAfhHHO/ZoMkprc2CaL9y/Zr4Y6hs++9rbb9iO3vcLQS9GmP rP3Hb3xmhBO21+vI3kGKij+1YgHzGOObU73JUGXILdUr6JdNXTzU8ws2s91ZReJ84xNbehw /WhPvlzRDoxLLle5W6cSiml1K/4W+TKdfukaC+Aqp8XKyg8a49A5hleH/Lqv5mpR4qmjyZw eKK/YzrGNxuJttXCXu4DQ== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1;V03:K0:Aot7sBbBbq0=:JpsX5ikzTK0uhVb74xfrU7 +IbBA8sp1nfD8j+dTnBg0Xg5y5sLlw/N06baPTxxWm4HnLSRiMYSgNraps5DQm68nsJpCMvlp +coQNxOva3AncmYubXs/XXoyygymR6p8FZ+FmIkSB/E2OADcp/p+VWU1TwUiPydbAOwxWbRKX pYQweyww+Dy1O7Q3j4L9FUM72qL5/Y4Wv59Y96KFzatSav1wBGQxQIsBOF5gH4ENakJhRfirx qfcR3O/oP9adIrwNUuMchYqdYXA28nlDqKMHay57epWi+XhMUXgtMHqEcg+2hgfAn4YeT29M9 Z7zDXYoeN+lOL9H+9+rifDKYs4kUkaX8tBhfoqpEAv4RD9mI0vgrF6h+ter1S8asKulAWBw6B biDXfYXpfOzQrK0Dp36Y0Q8WAt0yjuULVf7agxQOail0Pr1Gp5MDuLAI38zKK8zu/vTZ2ZmSo 6mvLhIs4mQA1kVn4A+FGJ7wfNs3+zg3560PB3BelItWg3VkbXXd6vuxGpxaC8lvAiM7tRle23 9RHmyWbc5/OwzIFlVQg5E2ze2uLnNQGdwaRguL6z/PGGkpdOMBMil+a9Soa2jlki3CP/gJuVr O986NmVNwzryH8F+jG5NmsJQxWDuuM4LQo9Ki2nrACW/9h38pgr7a8iW9rerMdx1JGlokXtEj 1h7w/mHWrhOSbhPJb5mtKbSCF8VBRdcn0+nST797837GFicsxbu8WhKNwIq5rltGal78cyYSZ yRfuzkz0eBcD791lfQrJPOkhaUxvTKQR2DcqCjI9DGq4nY95gSR9ZSdopyrJ17z6iVLHWB3vE 8FoV+UVkdeEfy8xgZRgYOLdJ1pM3ZbfZSPVtekSNItF+IfkmwKB+ZjO+Cdb3iFYRbDNNToe4l wVleF1SFMwKXOxjDAf9V7oMQZzMhJInTN4JlI61UdTSGh8pO01R6MslTf38vSa3TVhHz8Na45 XoUxArQ7uktpn7QZycCdkr1r+YoWMF48JpTrb4XupTruQ5V+hnxTE/ZWRxMj9UhPs3iHxK7oH gPew8r2KsfpeF+QHHbDUM6xjrnY4FgVpf/cqK4gnqAegflnT19m9RebJJ08WWzpQlUHxaoSI5 GBUVNZCiVhW3Lc= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This binding is heavily based on the one for NPCM7xx, because the hardware is similar. There are some notable differences, however: - The addresses of GPIO banks are not physical addresses but simple indices (0 to 7), because the GPIO registers are not laid out in convenient blocks. - Pinmux settings can explicitly specify that the GPIO mode is used. Certain pins support blink patterns in hardware. This is currently not modelled in the DT binding. Signed-off-by: Jonathan Neuschäfer Reviewed-by: Rob Herring --- v5: - Add Rob's R-b v4: - Small improvements around gpio node addresses, suggested by Rob Herring v3: - https://lore.kernel.org/lkml/20211224200935.93817-5-j.neuschaefer@gmx.net/ - Make changes suggested by Rob Herring - Fix lint errors - Simplify child node patterns - Remove if/type=object/then trick - Reduce interrupts.maxItems to 3: 4 aren't necessary - Replace list of gpio0/1/2/etc. with pattern - Remove nuvoton,interrupt-map again, to simplify the binding - Make tuples clearer v2: - https://lore.kernel.org/lkml/20211207210823.1975632-5-j.neuschaefer@gmx.net/ - Move GPIO into subnodes - Improve use of quotes - Remove unnecessary minItems/maxItems lines - Remove "phandle: true" - Use separate prefixes for pinmux and pincfg nodes - Add nuvoton,interrupt-map property - Make it possible to set pinmux to GPIO explicitly v1: - https://lore.kernel.org/lkml/20210602120329.2444672-5-j.neuschaefer@gmx.net/ --- .../pinctrl/nuvoton,wpcm450-pinctrl.yaml | 160 ++++++++++++++++++ 1 file changed, 160 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml -- 2.34.1 diff --git a/Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml new file mode 100644 index 0000000000000..47a56b83a610d --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml @@ -0,0 +1,160 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nuvoton,wpcm450-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton WPCM450 pin control and GPIO + +maintainers: + - Jonathan Neuschäfer + +properties: + compatible: + const: nuvoton,wpcm450-pinctrl + + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + # There are three kinds of subnodes: + # 1. a GPIO controller node for each GPIO bank + # 2. a pinmux node configures pin muxing for a group of pins (e.g. rmii2) + # 3. a pinconf node configures properties of a single pin + + "^gpio@[0-7]$": + type: object + + description: + Eight GPIO banks (gpio@0 to gpio@7), that each contain between 14 and 18 + GPIOs. Some GPIOs support interrupts. + + properties: + reg: + minimum: 0 + maximum: 7 + + gpio-controller: true + + "#gpio-cells": + const: 2 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + interrupts: + maxItems: 3 + description: + The interrupts associated with this GPIO bank + + required: + - reg + - gpio-controller + - '#gpio-cells' + + "^mux-": + $ref: pinmux-node.yaml# + + properties: + groups: + description: + One or more groups of pins to mux to a certain function + items: + enum: [ smb3, smb4, smb5, scs1, scs2, scs3, smb0, smb1, smb2, bsp, + hsp1, hsp2, r1err, r1md, rmii2, r2err, r2md, kbcc, dvo, + clko, smi, uinc, gspi, mben, xcs2, xcs1, sdio, sspi, fi0, + fi1, fi2, fi3, fi4, fi5, fi6, fi7, fi8, fi9, fi10, fi11, + fi12, fi13, fi14, fi15, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, + pwm6, pwm7, hg0, hg1, hg2, hg3, hg4, hg5, hg6, hg7 ] + function: + description: + The function that a group of pins is muxed to + enum: [ smb3, smb4, smb5, scs1, scs2, scs3, smb0, smb1, smb2, bsp, + hsp1, hsp2, r1err, r1md, rmii2, r2err, r2md, kbcc, dvo0, + dvo1, dvo2, dvo3, dvo4, dvo5, dvo6, dvo7, clko, smi, uinc, + gspi, mben, xcs2, xcs1, sdio, sspi, fi0, fi1, fi2, fi3, fi4, + fi5, fi6, fi7, fi8, fi9, fi10, fi11, fi12, fi13, fi14, fi15, + pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, pwm6, pwm7, hg0, hg1, + hg2, hg3, hg4, hg5, hg6, hg7, gpio ] + + dependencies: + groups: [ function ] + function: [ groups ] + + additionalProperties: false + + "^cfg-": + $ref: pincfg-node.yaml# + + properties: + pins: + description: + A list of pins to configure in certain ways, such as enabling + debouncing + items: + pattern: "^gpio1?[0-9]{1,2}$" + + input-debounce: true + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + #include + pinctrl: pinctrl@b8003000 { + compatible = "nuvoton,wpcm450-pinctrl"; + reg = <0xb8003000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + gpio0: gpio@0 { + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, + <3 IRQ_TYPE_LEVEL_HIGH>, + <4 IRQ_TYPE_LEVEL_HIGH>; + }; + + mux-rmii2 { + groups = "rmii2"; + function = "rmii2"; + }; + + pinmux_uid: mux-uid { + groups = "gspi", "sspi"; + function = "gpio"; + }; + + pinctrl_uid: cfg-uid { + pins = "gpio14"; + input-debounce = <1>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uid>, <&pinmux_uid>; + + uid { + label = "UID"; + linux,code = <102>; + gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + }; + };