From patchwork Fri Jan 21 14:29:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 1582606 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=l/NynUrR; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4JgMGm5ShTz9t2p for ; Sat, 22 Jan 2022 01:30:08 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1381202AbiAUOaF (ORCPT ); Fri, 21 Jan 2022 09:30:05 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:51370 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1381211AbiAUOaA (ORCPT ); Fri, 21 Jan 2022 09:30:00 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 20LETtJN090898; Fri, 21 Jan 2022 08:29:55 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1642775395; bh=PQjUeYI6SZb55ZnWteQFG/YxDujWZZKX3/zsTbo6InI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=l/NynUrRapNBNKD76r2iGaOPBdgN5arVhehw4sytWJTlLmMf9ORCTSWJY5ndEvzax OPW1ePw9bB2QeXztAG7PwJ330jwiJIUGF6sEcd2RsdQeVVLwcd0fmUBIfgzsQrI7gD 8c97FCm372K3jslCl0XGcXlg9dP2/JORUaFWhakU= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 20LETtmw065261 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 21 Jan 2022 08:29:55 -0600 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Fri, 21 Jan 2022 08:29:55 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Fri, 21 Jan 2022 08:29:55 -0600 Received: from pratyush-4F-325.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 20LET4Hx072129; Fri, 21 Jan 2022 08:29:51 -0600 From: Pratyush Yadav To: Mauro Carvalho Chehab CC: Pratyush Yadav , Laurent Pinchart , Nikhil Devshatwar , Tomi Valkeinen , Benoit Parrot , Maxime Ripard , Rob Herring , Sakari Ailus , =?utf-8?q?Niklas_S=C3=B6derlun?= =?utf-8?q?d?= , , , Subject: [PATCH v6 12/14] media: dt-bindings: Make sure items in data-lanes are unique Date: Fri, 21 Jan 2022 19:59:02 +0530 Message-ID: <20220121142904.4091481-13-p.yadav@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220121142904.4091481-1-p.yadav@ti.com> References: <20220121142904.4091481-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The data-lanes property maps the logical lane numbers to the physical lane numbers. The position of an entry is the logical lane number and its value is the physical lane number. Since one physical lane can only map to one logical lane, no number in the list should repeat. Add the uniqueItems constraint on the property to enforce this. Signed-off-by: Pratyush Yadav Reviewed-by: Laurent Pinchart Acked-by: Rob Herring --- (no changes since v5) Changes in v5: - Add Laurent's R-by and Rob's Ack. Changes in v4: - New in v4. Documentation/devicetree/bindings/media/video-interfaces.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/media/video-interfaces.yaml b/Documentation/devicetree/bindings/media/video-interfaces.yaml index 4391dce2caee..4bce93efae5f 100644 --- a/Documentation/devicetree/bindings/media/video-interfaces.yaml +++ b/Documentation/devicetree/bindings/media/video-interfaces.yaml @@ -158,6 +158,7 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32-array minItems: 1 maxItems: 8 + uniqueItems: true items: # Assume up to 9 physical lane indices maximum: 8 From patchwork Fri Jan 21 14:29:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 1582607 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=AGRyqqYB; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4JgMHF3h5bz9t2p for ; Sat, 22 Jan 2022 01:30:33 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1381365AbiAUOac (ORCPT ); Fri, 21 Jan 2022 09:30:32 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:58956 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1381247AbiAUOaE (ORCPT ); Fri, 21 Jan 2022 09:30:04 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 20LETxn8076318; Fri, 21 Jan 2022 08:29:59 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1642775399; bh=d9Dt0ojfeazX7PI/VA+8aM9lrW/y00i/SAVfapvLLhc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=AGRyqqYBYkmEYVgYqyeFAu9T0X6cBbu/6MRm3/ZVuFLQMUwhnuQzhvnoVZ/Kh+klU 1fL/J7nLtwVgG/+2kyntgjU2ExmaM7ywMFAerlQYiof3w3m5L1pNKFDp2UcakYVMNn sHMrtJ0vp1YVqwnAwdsJcNDkw6uzOuWzxegoDZ2s= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 20LETxnn019174 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 21 Jan 2022 08:29:59 -0600 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Fri, 21 Jan 2022 08:29:59 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Fri, 21 Jan 2022 08:29:59 -0600 Received: from pratyush-4F-325.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 20LET4I0072129; Fri, 21 Jan 2022 08:29:55 -0600 From: Pratyush Yadav To: Mauro Carvalho Chehab CC: Pratyush Yadav , Laurent Pinchart , Nikhil Devshatwar , Tomi Valkeinen , Benoit Parrot , Maxime Ripard , Rob Herring , Sakari Ailus , =?utf-8?q?Niklas_S=C3=B6derlun?= =?utf-8?q?d?= , , , Subject: [PATCH v6 13/14] media: dt-bindings: Add DT bindings for TI J721E CSI2RX driver Date: Fri, 21 Jan 2022 19:59:03 +0530 Message-ID: <20220121142904.4091481-14-p.yadav@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220121142904.4091481-1-p.yadav@ti.com> References: <20220121142904.4091481-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org TI's J721E uses the Cadence CSI2RX and DPHY peripherals to facilitate capture over a CSI-2 bus. The TI CSI2RX platform driver glues all the parts together. Signed-off-by: Pratyush Yadav Reviewed-by: Laurent Pinchart Reviewed-by: Rob Herring --- (no changes since v5) Changes in v5: - Add Laurent's and Rob's R-by. Changes in v2: - Rename to ti,j721e-csi2rx.yaml - Add an entry in MAINTAINERS. - Add a description for the binding. - Change compatible to ti,j721e-csi2rx to make it SoC specific. - Remove description from dmas, reg, power-domains. - Remove a limit of 2 from #address-cells and #size-cells. - Fix add ^ to csi-bridge subnode regex. - Make ranges mandatory. - Add unit address in example. - Add a reference to cdns,csi2rx in csi-bridge subnode. - Expand the example to include the csi-bridge subnode as well. - Re-order subject prefixes. .../bindings/media/ti,j721e-csi2rx.yaml | 101 ++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 102 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/ti,j721e-csi2rx.yaml diff --git a/Documentation/devicetree/bindings/media/ti,j721e-csi2rx.yaml b/Documentation/devicetree/bindings/media/ti,j721e-csi2rx.yaml new file mode 100644 index 000000000000..db87cfd65bed --- /dev/null +++ b/Documentation/devicetree/bindings/media/ti,j721e-csi2rx.yaml @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/ti,j721e-csi2rx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI J721E CSI2RX Wrapper Device Tree Bindings + +description: | + The TI J721E CSI2RX Wrapper is a wrapper around Cadence CSI2RX bridge that + enables sending captured frames to memory over PSI-L DMA. In the J721E + Technical Reference Manual (SPRUIL1B) it is referred to as "SHIM" under the + CSI_RX_IF section. + +maintainers: + - Pratyush Yadav + +properties: + compatible: + items: + - const: ti,j721e-csi2rx + + dmas: + maxItems: 1 + + dma-names: + items: + - const: rx0 + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + ranges: true + + "#address-cells": true + + "#size-cells": true + +patternProperties: + "^csi-bridge@": + type: object + description: CSI2 bridge node. + $ref: cdns,csi2rx.yaml# + +required: + - compatible + - reg + - dmas + - dma-names + - power-domains + - ranges + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + #include + + ti_csi2rx0: ticsi2rx@4500000 { + compatible = "ti,j721e-csi2rx"; + dmas = <&main_udmap 0x4940>; + dma-names = "rx0"; + reg = <0x4500000 0x1000>; + power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + cdns_csi2rx: csi-bridge@4504000 { + compatible = "cdns,csi2rx"; + reg = <0x4504000 0x1000>; + clocks = <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>, + <&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy0>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi2_0: port@0 { + + reg = <0>; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 2a8ebf17462e..446bc3146093 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19185,6 +19185,7 @@ TI J721E CSI2RX DRIVER M: Pratyush Yadav L: linux-media@vger.kernel.org S: Supported +F: Documentation/devicetree/bindings/media/ti,j721e-csi2rx.yaml F: drivers/media/platform/ti/j721e-csi2rx/ TI DAVINCI MACHINE SUPPORT From patchwork Fri Jan 21 14:29:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 1582608 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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Fri, 21 Jan 2022 08:30:03 -0600 Received: from pratyush-4F-325.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 20LET4I1072129; Fri, 21 Jan 2022 08:29:59 -0600 From: Pratyush Yadav To: Mauro Carvalho Chehab CC: Pratyush Yadav , Laurent Pinchart , Nikhil Devshatwar , Tomi Valkeinen , Benoit Parrot , Maxime Ripard , Rob Herring , Sakari Ailus , =?utf-8?q?Niklas_S=C3=B6derlun?= =?utf-8?q?d?= , , , Subject: [PATCH v6 14/14] media: dt-bindings: Convert Cadence CSI2RX binding to YAML Date: Fri, 21 Jan 2022 19:59:04 +0530 Message-ID: <20220121142904.4091481-15-p.yadav@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220121142904.4091481-1-p.yadav@ti.com> References: <20220121142904.4091481-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Cadence CSI2RX binding to use YAML schema. Signed-off-by: Pratyush Yadav Reviewed-by: Rob Herring Reviewed-by: Laurent Pinchart --- (no changes since v5) Changes in v5: - Move clock description in comments under the clocks property. - Make ports required. - Add Rob's and Laurent's R-by. Changes in v4: - Add power-domains property. - Drop maxItems from clock-names. - Drop the type for data-lanes. - Drop uniqueItems from data-lanes. Move it to video-interfaces.yaml instead. Changes in v3: - Add compatible: contains: const: cdns,csi2rx to allow SoC specific compatible. - Add more constraints for data-lanes property. Changes in v2: - New in v2. .../devicetree/bindings/media/cdns,csi2rx.txt | 100 ---------- .../bindings/media/cdns,csi2rx.yaml | 176 ++++++++++++++++++ 2 files changed, 176 insertions(+), 100 deletions(-) delete mode 100644 Documentation/devicetree/bindings/media/cdns,csi2rx.txt create mode 100644 Documentation/devicetree/bindings/media/cdns,csi2rx.yaml diff --git a/Documentation/devicetree/bindings/media/cdns,csi2rx.txt b/Documentation/devicetree/bindings/media/cdns,csi2rx.txt deleted file mode 100644 index 6b02a0657ad9..000000000000 --- a/Documentation/devicetree/bindings/media/cdns,csi2rx.txt +++ /dev/null @@ -1,100 +0,0 @@ -Cadence MIPI-CSI2 RX controller -=============================== - -The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI -lanes in input, and 4 different pixel streams in output. - -Required properties: - - compatible: must be set to "cdns,csi2rx" and an SoC-specific compatible - - reg: base address and size of the memory mapped region - - clocks: phandles to the clocks driving the controller - - clock-names: must contain: - * sys_clk: main clock - * p_clk: register bank clock - * pixel_if[0-3]_clk: pixel stream output clock, one for each stream - implemented in hardware, between 0 and 3 - -Optional properties: - - phys: phandle to the external D-PHY, phy-names must be provided - - phy-names: must contain "dphy", if the implementation uses an - external D-PHY - -Required subnodes: - - ports: A ports node with one port child node per device input and output - port, in accordance with the video interface bindings defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. The - port nodes are numbered as follows: - - Port Description - ----------------------------- - 0 CSI-2 input - 1 Stream 0 output - 2 Stream 1 output - 3 Stream 2 output - 4 Stream 3 output - - The stream output port nodes are optional if they are not - connected to anything at the hardware level or implemented - in the design.Since there is only one endpoint per port, - the endpoints are not numbered. - - -Example: - -csi2rx: csi-bridge@0d060000 { - compatible = "cdns,csi2rx"; - reg = <0x0d060000 0x1000>; - clocks = <&byteclock>, <&byteclock> - <&coreclock>, <&coreclock>, - <&coreclock>, <&coreclock>; - clock-names = "sys_clk", "p_clk", - "pixel_if0_clk", "pixel_if1_clk", - "pixel_if2_clk", "pixel_if3_clk"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - csi2rx_in_sensor: endpoint { - remote-endpoint = <&sensor_out_csi2rx>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - - port@1 { - reg = <1>; - - csi2rx_out_grabber0: endpoint { - remote-endpoint = <&grabber0_in_csi2rx>; - }; - }; - - port@2 { - reg = <2>; - - csi2rx_out_grabber1: endpoint { - remote-endpoint = <&grabber1_in_csi2rx>; - }; - }; - - port@3 { - reg = <3>; - - csi2rx_out_grabber2: endpoint { - remote-endpoint = <&grabber2_in_csi2rx>; - }; - }; - - port@4 { - reg = <4>; - - csi2rx_out_grabber3: endpoint { - remote-endpoint = <&grabber3_in_csi2rx>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/media/cdns,csi2rx.yaml b/Documentation/devicetree/bindings/media/cdns,csi2rx.yaml new file mode 100644 index 000000000000..399fe619377d --- /dev/null +++ b/Documentation/devicetree/bindings/media/cdns,csi2rx.yaml @@ -0,0 +1,176 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/cdns,csi2rx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence MIPI-CSI2 RX controller + +description: | + The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI + lanes in input, and 4 different pixel streams in output. + +maintainers: + - Pratyush Yadav + +properties: + compatible: + contains: + const: cdns,csi2rx + + reg: + maxItems: 1 + + clocks: + minItems: 3 + items: + - description: Main clock + - description: Register bank clock + - description: Pixel stream 0 output clock + - description: Pixel stream 1 output clock + - description: Pixel stream 2 output clock + - description: Pixel stream 3 output clock + + clock-names: + minItems: 3 + items: + - const: sys_clk + - const: p_clk + - const: pixel_if0_clk + - const: pixel_if1_clk + - const: pixel_if2_clk + - const: pixel_if3_clk + + phys: + maxItems: 1 + description: phandle to the external D-PHY + + phy-names: + items: + - const: dphy + + power-domains: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: CSI-2 input + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + items: + maximum: 4 + + required: + - clock-lanes + - data-lanes + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Stream 0 output + + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: Stream 1 output + + port@3: + $ref: /schemas/graph.yaml#/properties/port + description: Stream 2 output + + port@4: + $ref: /schemas/graph.yaml#/properties/port + description: Stream 3 output + + required: + - port@0 + + +dependencies: + phys: [ 'phy-names' ] + phy-names: [ 'phys' ] + +required: + - compatible + - reg + - clocks + - clock-names + - ports + +additionalProperties: false + +examples: + - | + csi2rx: csi-bridge@d060000 { + compatible = "cdns,csi2rx"; + reg = <0x0d060000 0x1000>; + clocks = <&byteclock>, <&byteclock>, + <&coreclock>, <&coreclock>, + <&coreclock>, <&coreclock>; + clock-names = "sys_clk", "p_clk", + "pixel_if0_clk", "pixel_if1_clk", + "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy0>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csi2rx_in_sensor: endpoint { + remote-endpoint = <&sensor_out_csi2rx>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + + csi2rx_out_grabber0: endpoint { + remote-endpoint = <&grabber0_in_csi2rx>; + }; + }; + + port@2 { + reg = <2>; + + csi2rx_out_grabber1: endpoint { + remote-endpoint = <&grabber1_in_csi2rx>; + }; + }; + + port@3 { + reg = <3>; + + csi2rx_out_grabber2: endpoint { + remote-endpoint = <&grabber2_in_csi2rx>; + }; + }; + + port@4 { + reg = <4>; + + csi2rx_out_grabber3: endpoint { + remote-endpoint = <&grabber3_in_csi2rx>; + }; + }; + }; + };