From patchwork Wed Jan 12 08:11:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Jiang, Haochen" X-Patchwork-Id: 1578894 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=MDmbuXJ8; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4JYgK15WWzz9sRR for ; Wed, 12 Jan 2022 19:12:20 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id DB0F0393A41B for ; Wed, 12 Jan 2022 08:12:17 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org DB0F0393A41B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1641975137; bh=uKFxatarIW6fBubiP1A7UfmeU1PTyZz9l/VOvykrQno=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=MDmbuXJ8pzLQkSzZnnh3SWFYAbebMzTYI9O0g8BXMvevz69URCcsQUcU2n9+mHSEe QX32C//3CTEqQ8N8zREGsnFA3dgd3n0jcp4BM4O0HiDSFV2GanSbmN7HDkt/0IkgJ1 qO16KwafP2R8XxsRHoNF4w/Q9TFXjPbp8AOv/+Ag= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by sourceware.org (Postfix) with ESMTPS id 0DB3C3858416 for ; Wed, 12 Jan 2022 08:11:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 0DB3C3858416 X-IronPort-AV: E=McAfee;i="6200,9189,10224"; a="304422615" X-IronPort-AV: E=Sophos;i="5.88,282,1635231600"; d="scan'208";a="304422615" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jan 2022 00:11:54 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,282,1635231600"; d="scan'208";a="623361199" Received: from scymds01.sc.intel.com ([10.148.94.138]) by orsmga004.jf.intel.com with ESMTP; 12 Jan 2022 00:11:54 -0800 Received: from shliclel320.sh.intel.com (shliclel320.sh.intel.com [10.239.236.50]) by scymds01.sc.intel.com with ESMTP id 20C8BqLo017484; Wed, 12 Jan 2022 00:11:53 -0800 To: gcc-patches@gcc.gnu.org Subject: [PATCH] [i386] Optimize a ^ ((a ^ b) & mask) to (~mask & a) | (b & mask). Date: Wed, 12 Jan 2022 16:11:52 +0800 Message-Id: <20220112081152.64776-1-haochen.jiang@intel.com> X-Mailer: git-send-email 2.18.1 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Haochen Jiang via Gcc-patches From: "Jiang, Haochen" Reply-To: Haochen Jiang Cc: hongtao.liu@intel.com Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Hi all, This patch targets PR94790, which change the instruction selection under the following circumstance. Regtested on x86_64-pc-linux-gnu. Ok for trunk? BRs, Haochen From the perspective of the pipeline, `andn + and + ior` version take 2 cycles(AND and ANDN doesn't have dependence), but xor + and + xor will take 3 cycles. - xorl %edi, %esi andl %edx, %esi - movl %esi, %eax - xorl %edi, %eax + andn %edi, %edx, %eax + orl %esi, %eax gcc/ChangeLog: PR taeget/94790 * config/i386/i386.md (*xor2andn): New define_insn_and_split. gcc/testsuite/ChangeLog: PR taeget/94790 * gcc.target/i386/pr94790-1.c: New test. * gcc.target/i386/pr94790-2.c: Ditto. --- gcc/config/i386/i386.md | 39 +++++++++++++++++++++++ gcc/testsuite/gcc.target/i386/pr94790-1.c | 14 ++++++++ gcc/testsuite/gcc.target/i386/pr94790-2.c | 9 ++++++ 3 files changed, 62 insertions(+) create mode 100755 gcc/testsuite/gcc.target/i386/pr94790-1.c create mode 100755 gcc/testsuite/gcc.target/i386/pr94790-2.c diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 9b424a3935b..38efc6d5837 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -10452,6 +10452,45 @@ (set_attr "znver1_decode" "double") (set_attr "mode" "DI")]) +;; PR target/94790: Optimize a ^ ((a ^ b) & mask) to (~mask & a) | (b & mask) +(define_insn_and_split "*xor2andn" + [(set (match_operand:SWI248 0 "nonimmediate_operand") + (xor:SWI248 + (and:SWI248 + (xor:SWI248 + (match_operand:SWI248 1 "nonimmediate_operand") + (match_operand:SWI248 2 "nonimmediate_operand")) + (match_operand:SWI248 3 "nonimmediate_operand")) + (match_dup 1))) + (clobber (reg:CC FLAGS_REG))] + "(TARGET_BMI || TARGET_AVX512BW) + && ix86_pre_reload_split ()" + "#" + "&& 1" + [(parallel [(set (match_dup 4) + (and:SWI248 + (not:SWI248 + (match_dup 3)) + (match_dup 1))) + (clobber (reg:CC FLAGS_REG))]) + (parallel [(set (match_dup 5) + (and:SWI248 + (match_dup 2) + (match_dup 3))) + (clobber (reg:CC FLAGS_REG))]) + (parallel [(set (match_dup 0) + (ior:SWI248 + (match_dup 4) + (match_dup 5))) + (clobber (reg:CC FLAGS_REG))])] + { + operands[1] = force_reg (mode, operands[1]); + operands[3] = force_reg (mode, operands[3]); + operands[4] = gen_reg_rtx (mode); + operands[5] = gen_reg_rtx (mode); + } +) + ;; See comment for addsi_1_zext why we do use nonimmediate_operand (define_insn "*si_1_zext" [(set (match_operand:DI 0 "register_operand" "=r") diff --git a/gcc/testsuite/gcc.target/i386/pr94790-1.c b/gcc/testsuite/gcc.target/i386/pr94790-1.c new file mode 100755 index 00000000000..6ebbec15cfd --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr94790-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbmi" } */ +/* { dg-final { scan-assembler-times "andn\[ \\t\]" 2 } } */ +/* { dg-final { scan-assembler-not "xorl\[ \\t\]" } } */ + +unsigned r1(unsigned a, unsigned b, unsigned mask) +{ + return a ^ ((a ^ b) & mask); +} + +unsigned r2(unsigned a, unsigned b, unsigned mask) +{ + return (~mask & a) | (b & mask); +} diff --git a/gcc/testsuite/gcc.target/i386/pr94790-2.c b/gcc/testsuite/gcc.target/i386/pr94790-2.c new file mode 100755 index 00000000000..d7b0eec5bef --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr94790-2.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbmi" } */ +/* { dg-final { scan-assembler-not "andn\[ \\t\]" } } */ +/* { dg-final { scan-assembler-times "xorl\[ \\t\]" 2 } } */ + +unsigned r1(unsigned a, unsigned b, unsigned mask) +{ + return a ^ ((a ^ b) & mask) + (a ^ b); +}