From patchwork Tue Jan 11 18:45:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashish Mhetre X-Patchwork-Id: 1578649 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=c6sAWCia; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4JYKQl02b6z9s9c for ; Wed, 12 Jan 2022 05:46:06 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241456AbiAKSqG (ORCPT ); Tue, 11 Jan 2022 13:46:06 -0500 Received: from mail-mw2nam08on2045.outbound.protection.outlook.com ([40.107.101.45]:11691 "EHLO NAM04-MW2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1346159AbiAKSqF (ORCPT ); Tue, 11 Jan 2022 13:46:05 -0500 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=UTaX2uql9+/Ass4p0tkhhqgi5QjpnhLsRllogzsd8ibdAqfFmzgfzCOA9NE9g9JnYUe/FjIENU0hlFkmGptRcCbZEuur1ei4vmw0jhvUf+fDpJknJ5UHlLX7Ekc3X6RtESv9JTTKrjU3f6xUWzQHKAiVjDxbo2QGVw2JdaKEDUkiGU6hz37EAQ1xaOwZXHDaZAYVMHqgnK56fVinXVhmoxhFJUQbaVR/e8Rt2xTuYiSZ/C/NrilrHnxEyGhSHMtoEzHhrhnpFWzaDLYZTU4O6eYl1+o3vaMlDptA5eG5MVAh3ss9dW9i5ZDOMybVMhjG6xnp/Sj9Sfkfz/hu9uYDqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=uBiHA3im8jTzhDAGMDtYFO2m+bw+5wull6p8c+CuuzM=; b=JMAP4yJ+uS38al+9pqOZV+yANuHBP+Px8AxhBOtBHm69D6sRS6+643t1NnxdJIz58ApVsZ3an14EaebuS6H47HzNwtxWtf4eg9Qvc6zV8RqjbuqOLlJJ4qfV7R8bDcEg54HrrehQqkUWrLb4XkDPEsUPbNvcOCosdCmAv+LaDG223scMrbhJYUIsoDBgQVti0kjAb6EQXVyTN5a5ahWg6vVIBf2xYltJwc/iV7lCSIoBzGiiGCeK244qIpwFkBZ8D59l8J+ctdcWJW5UkNTlvTC8KyUbXXbZ+q9JoneDBvSITiXZ+PfQAKSnR/Pmx4iBs9JjSIKcZ77QdpN+EJhHeQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.236) smtp.rcpttodomain=gmail.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=uBiHA3im8jTzhDAGMDtYFO2m+bw+5wull6p8c+CuuzM=; b=c6sAWCiaAGes+OHDhZCG8m64EF9bn1jDKQTAdFq5WgQ5G6qWcwGyrUNqLwmtPor3ZYm/WphSJ8pvcpWM+mkIdhePHwbq95hy+0WbrZhBXr/9/rfUPfNSiyy2/avsEG2n64ZkEiwU6AT3klNLfEVA6x0zoOvWJQvUrtD53sYSTm1Cxt8NIz89AKCe6/np3Hx/nH1durZht0jondt89u9cyGB7OOhbQNjucNoHYWdlmM8R+pw0HXFvgAps/XzpRyxQvyWVtj5TNRHvx+cDyX+Zn98g1veevBUPnDmfw2DQbB17u6DLD1ruGXuFdSansz1KS13Qc5S5ZEaXnOzQR6adQA== Received: from DM6PR11CA0055.namprd11.prod.outlook.com (2603:10b6:5:14c::32) by BN6PR12MB1876.namprd12.prod.outlook.com (2603:10b6:404:104::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4867.7; Tue, 11 Jan 2022 18:46:01 +0000 Received: from DM6NAM11FT022.eop-nam11.prod.protection.outlook.com (2603:10b6:5:14c:cafe::d7) by DM6PR11CA0055.outlook.office365.com (2603:10b6:5:14c::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4888.9 via Frontend Transport; Tue, 11 Jan 2022 18:46:01 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.236) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.236 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.236; helo=mail.nvidia.com; Received: from mail.nvidia.com (12.22.5.236) by DM6NAM11FT022.mail.protection.outlook.com (10.13.172.210) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4867.9 via Frontend Transport; Tue, 11 Jan 2022 18:46:01 +0000 Received: from HQMAIL111.nvidia.com (172.20.187.18) by DRHQMAIL109.nvidia.com (10.27.9.19) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 11 Jan 2022 18:46:00 +0000 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 11 Jan 2022 18:46:00 +0000 Received: from amhetre.nvidia.com (10.127.8.9) by mail.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 11 Jan 2022 18:45:57 +0000 From: Ashish Mhetre To: , , , , , CC: , Subject: [Patch V1 1/4] memory: tegra: Add support for mc interrupts Date: Wed, 12 Jan 2022 00:15:47 +0530 Message-ID: <1641926750-27544-2-git-send-email-amhetre@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1641926750-27544-1-git-send-email-amhetre@nvidia.com> References: <1641926750-27544-1-git-send-email-amhetre@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ebb67651-cfae-4c01-813e-08d9d5329d77 X-MS-TrafficTypeDiagnostic: BN6PR12MB1876:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:208; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: +fdT9LroEk5Hjt5rou2yxrkQz/m199EH+troHgcGgCHwq/MXTV8o2cQRHDVdCE7F+oBP1LiNc13ln8PfVpGVQ/DjLqcJewS3tw1gZ30Jrsr/exCN3ENFIdIpecxt9w/6t8shvSG1QApoBgdsafA+xWhbis1ygeSrd1gLb39+4o5BI9cIRfrHGcJjI69xeAlkjW2P+1BGLLptOcvdX2C1RXlmw2ZIbMIh6pJyOi/YcmS9jNAHKe8on5wPrp7CbCJblVCKEoR5OMGyeX+jm65jc7sk2HPIZNGil1SaGHwMlisatNHMZm0T6MLOpl46RUuFRBRQzc4oa1jgjwaNC1w0xWIvRz0jzz+hhlD60cMzkEhxT53xcTWnF6JgeSMvIx0Dzzg8kjD/8JfFSgYSqqoipeX8+YShKS0cmUyDBCGFEU0k94EKB0UgPWAr6EY9lDaXO0PB/qn1mIcKfA0jGHmSFt2zd+VXfTLvBI9rQKWRiBpIVIHj80M8plz6VS15ZfzqoNPEejq7i0U2JjgWXYKc0h7zTx/LNbGsyqhHoULoQOp0KIE53/mfft/HfJuzK5kGTAodILkNya1ay+3vdfoHrWRbNEEq6+BSeCFEoHwfhE1SBVGRRzWrxTQnSagTByLLLKdFYGkAaloo+Pr56gDbgPrdbCHucXB0pMBTn394BnaLTfaNUJynD/LZoQ/tfU3BEepXnNahcfLHy7rAyLdoRUTnWwgj0IzkUpX7BXeF8x3/OuCCJjCCT5JNyOQC/MLmZTWFUc0xXsl/nysQ0vce9wAlUVff7NAQUKDVRRkrSMA= X-Forefront-Antispam-Report: CIP:12.22.5.236;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(40470700002)(7696005)(26005)(508600001)(336012)(186003)(107886003)(356005)(2616005)(83380400001)(6666004)(86362001)(47076005)(40460700001)(82310400004)(4326008)(36860700001)(316002)(8936002)(36756003)(110136005)(54906003)(81166007)(5660300002)(8676002)(70206006)(426003)(2906002)(70586007)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jan 2022 18:46:01.5165 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ebb67651-cfae-4c01-813e-08d9d5329d77 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.236];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT022.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1876 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Implement new structure for function related to mc interrupts. Move handle_irq into this structure. Add support for clearing interrupts. Signed-off-by: Ashish Mhetre --- drivers/memory/tegra/mc.c | 14 +++++++++++--- drivers/memory/tegra/mc.h | 1 + drivers/memory/tegra/tegra114.c | 1 + drivers/memory/tegra/tegra124.c | 2 ++ drivers/memory/tegra/tegra186.c | 14 ++++++++++++++ drivers/memory/tegra/tegra194.c | 12 ++++++++++++ drivers/memory/tegra/tegra20.c | 6 +++++- drivers/memory/tegra/tegra210.c | 1 + drivers/memory/tegra/tegra30.c | 1 + include/soc/tegra/mc.h | 7 ++++++- 10 files changed, 54 insertions(+), 5 deletions(-) diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index 3c5aae7..3b3f052 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -604,9 +604,12 @@ static irqreturn_t tegra30_mc_handle_irq(int irq, void *data) return IRQ_HANDLED; } +const struct tegra_mc_interrupt_ops tegra30_mc_interrupt_ops = { + .handle_irq = tegra30_mc_handle_irq, +}; + const struct tegra_mc_ops tegra30_mc_ops = { .probe = tegra30_mc_probe, - .handle_irq = tegra30_mc_handle_irq, }; #endif @@ -765,16 +768,21 @@ static int tegra_mc_probe(struct platform_device *pdev) return err; } - if (mc->soc->ops && mc->soc->ops->handle_irq) { + if (mc->soc->interrupt_ops && mc->soc->interrupt_ops->handle_irq) { mc->irq = platform_get_irq(pdev, 0); if (mc->irq < 0) return mc->irq; WARN(!mc->soc->client_id_mask, "missing client ID mask for this SoC\n"); + /* clear any mc-errs that occurred before. */ + if (mc->soc->interrupt_ops->clear_interrupt) + mc->soc->interrupt_ops->clear_interrupt(mc); + mc_writel(mc, mc->soc->intmask, MC_INTMASK); - err = devm_request_irq(&pdev->dev, mc->irq, mc->soc->ops->handle_irq, 0, + err = devm_request_irq(&pdev->dev, mc->irq, + mc->soc->interrupt_ops->handle_irq, 0, dev_name(&pdev->dev), mc); if (err < 0) { dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq, diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h index 1e49298..f1fd457 100644 --- a/drivers/memory/tegra/mc.h +++ b/drivers/memory/tegra/mc.h @@ -144,6 +144,7 @@ extern const struct tegra_mc_soc tegra194_mc_soc; defined(CONFIG_ARCH_TEGRA_210_SOC) int tegra30_mc_probe(struct tegra_mc *mc); extern const struct tegra_mc_ops tegra30_mc_ops; +extern const struct tegra_mc_interrupt_ops tegra30_mc_interrupt_ops; #endif #if defined(CONFIG_ARCH_TEGRA_186_SOC) || \ diff --git a/drivers/memory/tegra/tegra114.c b/drivers/memory/tegra/tegra114.c index 4135057..f7b8dd9 100644 --- a/drivers/memory/tegra/tegra114.c +++ b/drivers/memory/tegra/tegra114.c @@ -1114,4 +1114,5 @@ const struct tegra_mc_soc tegra114_mc_soc = { .resets = tegra114_mc_resets, .num_resets = ARRAY_SIZE(tegra114_mc_resets), .ops = &tegra30_mc_ops, + .interrupt_ops = &tegra30_mc_interrupt_ops, }; diff --git a/drivers/memory/tegra/tegra124.c b/drivers/memory/tegra/tegra124.c index d780a84..8b704c1 100644 --- a/drivers/memory/tegra/tegra124.c +++ b/drivers/memory/tegra/tegra124.c @@ -1275,6 +1275,7 @@ const struct tegra_mc_soc tegra124_mc_soc = { .num_resets = ARRAY_SIZE(tegra124_mc_resets), .icc_ops = &tegra124_mc_icc_ops, .ops = &tegra30_mc_ops, + .interrupt_ops = &tegra30_mc_interrupt_ops, }; #endif /* CONFIG_ARCH_TEGRA_124_SOC */ @@ -1307,5 +1308,6 @@ const struct tegra_mc_soc tegra132_mc_soc = { .num_resets = ARRAY_SIZE(tegra124_mc_resets), .icc_ops = &tegra124_mc_icc_ops, .ops = &tegra30_mc_ops, + .interrupt_ops = &tegra30_mc_interrupt_ops, }; #endif /* CONFIG_ARCH_TEGRA_132_SOC */ diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c index e65eac5..b548b6a 100644 --- a/drivers/memory/tegra/tegra186.c +++ b/drivers/memory/tegra/tegra186.c @@ -12,6 +12,8 @@ #include +#include "mc.h" + #if defined(CONFIG_ARCH_TEGRA_186_SOC) #include #endif @@ -20,6 +22,8 @@ #define MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED BIT(16) #define MC_SID_STREAMID_SECURITY_OVERRIDE BIT(8) +#define MC_INTSTATUS_CLEAR 0x00033340 + static void tegra186_mc_program_sid(struct tegra_mc *mc) { unsigned int i; @@ -137,6 +141,15 @@ static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev) return 0; } +static void tegra186_mc_clear_interrupt(struct tegra_mc *mc) +{ + mc_writel(mc, MC_INTSTATUS_CLEAR, MC_INTSTATUS); +} + +const struct tegra_mc_interrupt_ops tegra186_mc_interrupt_ops = { + .clear_interrupt = tegra186_mc_clear_interrupt, +}; + const struct tegra_mc_ops tegra186_mc_ops = { .probe = tegra186_mc_probe, .remove = tegra186_mc_remove, @@ -874,5 +887,6 @@ const struct tegra_mc_soc tegra186_mc_soc = { .clients = tegra186_mc_clients, .num_address_bits = 40, .ops = &tegra186_mc_ops, + .interrupt_ops = &tegra186_mc_interrupt_ops, }; #endif diff --git a/drivers/memory/tegra/tegra194.c b/drivers/memory/tegra/tegra194.c index cab998b..19f135f 100644 --- a/drivers/memory/tegra/tegra194.c +++ b/drivers/memory/tegra/tegra194.c @@ -9,6 +9,17 @@ #include "mc.h" +#define MC_INTSTATUS_CLEAR 0x00133340 + +static void tegra194_mc_clear_interrupt(struct tegra_mc *mc) +{ + mc_writel(mc, MC_INTSTATUS_CLEAR, MC_INTSTATUS); +} + +const struct tegra_mc_interrupt_ops tegra194_mc_interrupt_ops = { + .clear_interrupt = tegra194_mc_clear_interrupt, +}; + static const struct tegra_mc_client tegra194_mc_clients[] = { { .id = TEGRA194_MEMORY_CLIENT_PTCR, @@ -1348,4 +1359,5 @@ const struct tegra_mc_soc tegra194_mc_soc = { .clients = tegra194_mc_clients, .num_address_bits = 40, .ops = &tegra186_mc_ops, + .interrupt_ops = &tegra194_mc_interrupt_ops, }; diff --git a/drivers/memory/tegra/tegra20.c b/drivers/memory/tegra/tegra20.c index fcd7738..3bcb2ca 100644 --- a/drivers/memory/tegra/tegra20.c +++ b/drivers/memory/tegra/tegra20.c @@ -786,11 +786,15 @@ static irqreturn_t tegra20_mc_handle_irq(int irq, void *data) return IRQ_HANDLED; } +static const struct tegra_mc_interrupt_ops tegra20_mc_interrupt_ops = { + .handle_irq = tegra20_mc_handle_irq, +}; + static const struct tegra_mc_ops tegra20_mc_ops = { .probe = tegra20_mc_probe, .suspend = tegra20_mc_suspend, .resume = tegra20_mc_resume, - .handle_irq = tegra20_mc_handle_irq, + .interrupt_ops = tegra20_mc_interrupt_ops, }; const struct tegra_mc_soc tegra20_mc_soc = { diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c index 8ab6498..d7ed163 100644 --- a/drivers/memory/tegra/tegra210.c +++ b/drivers/memory/tegra/tegra210.c @@ -1287,4 +1287,5 @@ const struct tegra_mc_soc tegra210_mc_soc = { .resets = tegra210_mc_resets, .num_resets = ARRAY_SIZE(tegra210_mc_resets), .ops = &tegra30_mc_ops, + .interrupt_ops = &tegra30_mc_interrupt_ops, }; diff --git a/drivers/memory/tegra/tegra30.c b/drivers/memory/tegra/tegra30.c index 8431635..bb5ff68 100644 --- a/drivers/memory/tegra/tegra30.c +++ b/drivers/memory/tegra/tegra30.c @@ -1400,4 +1400,5 @@ const struct tegra_mc_soc tegra30_mc_soc = { .num_resets = ARRAY_SIZE(tegra30_mc_resets), .icc_ops = &tegra30_mc_icc_ops, .ops = &tegra30_mc_ops, + .interrupt_ops = &tegra30_mc_interrupt_ops, }; diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index 1066b11..debc47b 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -170,6 +170,11 @@ struct tegra_mc_icc_ops { void *data); }; +struct tegra_mc_interrupt_ops { + void (*clear_interrupt)(struct tegra_mc *mc); + irqreturn_t (*handle_irq)(int irq, void *data); +}; + struct tegra_mc_ops { /* * @probe: Callback to set up SoC-specific bits of the memory controller. This is called @@ -179,7 +184,6 @@ struct tegra_mc_ops { void (*remove)(struct tegra_mc *mc); int (*suspend)(struct tegra_mc *mc); int (*resume)(struct tegra_mc *mc); - irqreturn_t (*handle_irq)(int irq, void *data); int (*probe_device)(struct tegra_mc *mc, struct device *dev); }; @@ -205,6 +209,7 @@ struct tegra_mc_soc { const struct tegra_mc_icc_ops *icc_ops; const struct tegra_mc_ops *ops; + const struct tegra_mc_interrupt_ops *interrupt_ops; }; struct tegra_mc { From patchwork Tue Jan 11 18:45:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashish Mhetre X-Patchwork-Id: 1578650 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=pV/2CGd0; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4JYKQm6mxsz9s9c for ; Wed, 12 Jan 2022 05:46:08 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346237AbiAKSqH (ORCPT ); Tue, 11 Jan 2022 13:46:07 -0500 Received: from mail-dm6nam10on2070.outbound.protection.outlook.com ([40.107.93.70]:44673 "EHLO NAM10-DM6-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1346160AbiAKSqG (ORCPT ); Tue, 11 Jan 2022 13:46:06 -0500 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Uk2wKM1QZsDSNw3g+TPZFvnkESYderzCkX5Sgg+BLjJjjdBIk1br3xIF96KtgM+GoPTZdtXwr17p/tSDZLGn4YIcCsSI/Mffcr5pu9qOxMbZiQB0saFZxS8B45wwioKbxKt+ioamNkgBXpWq4HY4HO9Mzx3tf83vIK2KY/HHHZGFicg1YsXxLPIhKKvIqH20q6Z6wAtVAbR4nUAoJWcko7A6iNT2zaxi6pgaGCN/Att4Cprz6bAxuhjqNo46zt0HNuxUB6wXF204vKh/hwjqNH7r4CsuCFSBMXqBXBGi7Bvbrntwxbs98OUUYrg7D9ewzMdogo+toR1lDSmsfgC3uA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=N3etfX5PHnvTp0bk5bhFY+ysaRRd+/81Vf6iOcsuXZU=; b=MhoSq5Fge3A1SzkXoIQFl6fRcb+WF/77BTkdYZn189ey5Oc1kJDY2cZCU3Q4f0QfkhMq8lBrMflDFz298asRFyLaaAZu3VmaPaEdXcb+5ERyUT6gsQi++kYdWBw7VNsOu2a9HXqSYzJXr0lpLg1Wl13X8sTW5RUa3pPZ/msSzK++ao0prKauG6NEgBkUZO/V3PUKwC2oxXGZHIbQ4eOvbHnutS4XsGZi0N0qKC2HWF5KYLVn+YSmytGkMi6X9RL3PzL/zvKCndO2IEETmK6uiIlHRswa+jbAprbvER6rvtIVb5c5vroIIA0fSTMEw/8JjKMUM0r+sWTLOm3DeJvyeg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.235) smtp.rcpttodomain=gmail.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=N3etfX5PHnvTp0bk5bhFY+ysaRRd+/81Vf6iOcsuXZU=; b=pV/2CGd0jBg1sPNdpKetA0ICkS0zPSMS+R7uyCJI41drG3cOXsh/hr1WdoHsPnDiu2RhmE7QsfnKzc3jCt2REvO1XDTYuDgChmEGVsgg/938e3W22ytJBJrU2NrHlQwUKzGzgdemlvXezVPLJRBYA9Bpa/XTnEGaFh+YV+5okRFmvH+A3TecEFZTyzYML+hwgpl7jjJ0bRjyq2x/x1ngpmQ64eyoNP83PPMhGF3tQsXKXD12RwgM3v0tHaGSj0eOW+psxEJ8hqbyuGEjTXfsBjX9M+i3+hA6yufx2t01kzym9FoMoF5qGetYuexRABQvBFQ2p+vFKodO7ltxgNz0mQ== Received: from DM6PR11CA0070.namprd11.prod.outlook.com (2603:10b6:5:14c::47) by MWHPR12MB1247.namprd12.prod.outlook.com (2603:10b6:300:10::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4867.11; Tue, 11 Jan 2022 18:46:04 +0000 Received: from DM6NAM11FT022.eop-nam11.prod.protection.outlook.com (2603:10b6:5:14c:cafe::72) by DM6PR11CA0070.outlook.office365.com (2603:10b6:5:14c::47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4867.11 via Frontend Transport; Tue, 11 Jan 2022 18:46:04 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.235) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.235 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.235; helo=mail.nvidia.com; Received: from mail.nvidia.com (12.22.5.235) by DM6NAM11FT022.mail.protection.outlook.com (10.13.172.210) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4867.9 via Frontend Transport; Tue, 11 Jan 2022 18:46:04 +0000 Received: from HQMAIL111.nvidia.com (172.20.187.18) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 11 Jan 2022 18:46:04 +0000 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 11 Jan 2022 18:46:03 +0000 Received: from amhetre.nvidia.com (10.127.8.9) by mail.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 11 Jan 2022 18:46:01 +0000 From: Ashish Mhetre To: , , , , , CC: , Subject: [Patch V1 2/4] memory: tegra: Add interrupt mask Date: Wed, 12 Jan 2022 00:15:48 +0530 Message-ID: <1641926750-27544-3-git-send-email-amhetre@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1641926750-27544-1-git-send-email-amhetre@nvidia.com> References: <1641926750-27544-1-git-send-email-amhetre@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 23edda3a-0ddb-4bf5-275e-08d9d5329f4d X-MS-TrafficTypeDiagnostic: MWHPR12MB1247:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1728; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: +di7kRifh0w3+Q0WurfpyaseZsT6fGd7NkvjBGCYAIldPhqh0tY3pVykbM9CrCLgNPq5ysuLcxh8Y0p2Gb1femGewHelLe1LoZYmM40F6ASoR3vwJNb7Ps/J2OGxXrPSezH5Q4bZ6z/ijoZ1xvGqxbLBb+KpIIAco5lsI7T3FTA10UY6flYfieCG9PF2q3ICl+B8bphk/4867Apda5n8I6rz5rsm2Xn/EEN93K22phkuNRl6rWIGTgh4NmEwMI2Pky+n6cMpseFejlcDH2DPJMwlzpbXPj0ivLN5XJ3kYnh9KGj/G22jO0eksL3q8Nl470SB+SyeCkA0hvEYFC+fRPUaEjUPucHR9msQi7eAvjJpQ8qgWESl7b0r+dcbaV9JobhUwtoBB3HZcRxQGynT9WX165Ps99miHt20KyrZwCae0mMwbXlyuZx2/tMUs9Jo1A1hdddb0UGNQqV1EV1KVNtkP1wBV80vjuKZyBlkSO3lTApMLaOSKwGd0It2BWw8VN1Uq+IYt5m8b3oYvN0nozmQmSbfox5gT/9EhQdIs5UNGJGYYZOk+0XdMrIYqDzo9LX2CpeiMVDhOoQg4R30WGAMj20bsZjtLMsLPXugzm0W8rkOEl1u9evrZ4fk10dxoUlw95qakM+suokyqE4ZHUKpciamVxVUXvvtzzf2ayh7MSn9gpA6WEWN/X6Y2DVyC7T/sMyBHArvStFwTnbLPzuiPrMdyCtUPiFdMKaEmMs8W04oLMA3mPJ1W1hSSkJOaW3EVkOEVcjLBHQkoPO1E6q8OR2/ohI9y1sXlb90Fpk= X-Forefront-Antispam-Report: CIP:12.22.5.235;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(4636009)(40470700002)(46966006)(36840700001)(70586007)(54906003)(508600001)(7696005)(2616005)(356005)(4326008)(81166007)(8936002)(110136005)(426003)(336012)(70206006)(83380400001)(36756003)(2906002)(26005)(40460700001)(5660300002)(316002)(82310400004)(47076005)(86362001)(107886003)(6666004)(8676002)(36860700001)(186003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jan 2022 18:46:04.5944 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 23edda3a-0ddb-4bf5-275e-08d9d5329f4d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.235];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT022.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1247 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add interrupt masks for all supported interrupts on tegra MCs. Update interrupt mask value for T186 and T194 as per supported interrupts. Signed-off-by: Ashish Mhetre --- drivers/memory/tegra/mc.h | 4 ++++ drivers/memory/tegra/tegra186.c | 4 ++++ drivers/memory/tegra/tegra194.c | 4 ++++ 3 files changed, 12 insertions(+) diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h index f1fd457..2d4f495 100644 --- a/drivers/memory/tegra/mc.h +++ b/drivers/memory/tegra/mc.h @@ -44,6 +44,10 @@ #define MC_TIMING_CONTROL_DBG 0xf8 #define MC_TIMING_CONTROL 0xfc +#define MC_INT_DECERR_ROUTE_SANITY BIT(20) +#define MC_INT_WCAM_ERR BIT(19) +#define MC_INT_SCRUB_ECC_WR_ACK BIT(18) +#define MC_INT_DECERR_GENERALIZED_CARVEOUT BIT(17) #define MC_INT_DECERR_MTS BIT(16) #define MC_INT_SECERR_SEC BIT(13) #define MC_INT_DECERR_VPR BIT(12) diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c index b548b6a..6766cc4 100644 --- a/drivers/memory/tegra/tegra186.c +++ b/drivers/memory/tegra/tegra186.c @@ -886,6 +886,10 @@ const struct tegra_mc_soc tegra186_mc_soc = { .num_clients = ARRAY_SIZE(tegra186_mc_clients), .clients = tegra186_mc_clients, .num_address_bits = 40, + .intmask = MC_INT_WCAM_ERR | MC_INT_SCRUB_ECC_WR_ACK | + MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS | + MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | + MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, .ops = &tegra186_mc_ops, .interrupt_ops = &tegra186_mc_interrupt_ops, }; diff --git a/drivers/memory/tegra/tegra194.c b/drivers/memory/tegra/tegra194.c index 19f135f..76ba3da 100644 --- a/drivers/memory/tegra/tegra194.c +++ b/drivers/memory/tegra/tegra194.c @@ -1358,6 +1358,10 @@ const struct tegra_mc_soc tegra194_mc_soc = { .num_clients = ARRAY_SIZE(tegra194_mc_clients), .clients = tegra194_mc_clients, .num_address_bits = 40, + .intmask = MC_INT_DECERR_ROUTE_SANITY | MC_INT_WCAM_ERR | + MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS | + MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | + MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, .ops = &tegra186_mc_ops, .interrupt_ops = &tegra194_mc_interrupt_ops, }; From patchwork Tue Jan 11 18:45:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashish Mhetre X-Patchwork-Id: 1578651 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=uRKhga3Z; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4JYKQs3Hz4z9s9c for ; Wed, 12 Jan 2022 05:46:13 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346281AbiAKSqM (ORCPT ); Tue, 11 Jan 2022 13:46:12 -0500 Received: from mail-dm6nam11on2083.outbound.protection.outlook.com ([40.107.223.83]:56928 "EHLO NAM11-DM6-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1346268AbiAKSqK (ORCPT ); Tue, 11 Jan 2022 13:46:10 -0500 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=awfVeEciVjMQrlpHOYFQGrNrOVDW4DTLo19t5DlZnb8SoqjRZ2NXADUqQSnsHdIVkqixWRupl2dSHeo03y6kfSdvHuIJHSMvOg+766Ccg401Itb3bha7kLvvphKVMqKRca3I1MVuOp+FgD/+xGTPa8yBQ2NFDEU9Nb9+cOB1h/dVYySrewTQQQRqPmz+92SRNWoJFqVWCPX9ek+F0eNMd8ijbybfOypyLaF90VuOQGSQzjfvX5bkMexFklZnUxHcpTIImZQwAybrfb3lhAXi+9KZOUrJicEwTgdKrvyWdX7xSOkNwETXQc10n8s4JY03lQD5TmzuySBLzvKRdpmiSQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=mXYZNUzTWVTPgL4YEYRncozB2YklqYyv/gNe11XxZic=; b=iz+3GiqkvQKcynvTSmDblvHwBMjai688xGf3kDt4AaQWRY+CQ51lAzO/oEXSupffSLwH2Sjr662p0PBOpCXbSpuvaCMM2S3tso++BSxkOehu+Bu24AdFs6wVqBZnC7JsH2OL0A75fv6trez2KRTvIBd/yifmhP7VNhuEDItHuyRvVzcRa7C7p85CkjhGQqRg8ecV4TC6cK2MBnYcRfBt5kyyH5VEiWapTW0h46AumJoxUwGDBvyhq2jGn6TfVKP1xiFY6EA+1TEG3cVwvkoSmqvEJBEvFYJ7Hc/cTI1f6CrBsnmdg3kBdDVMzOOidzn8oGYSRvlrrgKfs2S738f6Yg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.234) smtp.rcpttodomain=gmail.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=mXYZNUzTWVTPgL4YEYRncozB2YklqYyv/gNe11XxZic=; b=uRKhga3Zcpvmgn50JyjgICDn+Soh/kXUQskTKdUQWJmQtujHJX1g92Ri/MAR1w6gboz3/Y393FSY8fAwyR61j3O2d+uAhBHdupu9TCwTGM2HfJDQNRAiIYj3msA8k6usgil6nO+/ZyE/y32JivaC1H2y1fxBwkm5e8F4BbxkPE5URWHmhJIidBPSEY90Wb+GYkzWJ9xY4bUvcCZ1inT1Zrj22tsC0sFr8GXyiI7W7IYiIlsp6vnKWbS1i3/5Ba9LiB2VV6UW/1fBzUPc0CroipM2EzgWGoEDlMMKrRjQm/yTfYtz/K1oR8mfmXa5YT+TRMr30iBQmrWd2Bn6D5u26A== Received: from DM6PR11CA0049.namprd11.prod.outlook.com (2603:10b6:5:14c::26) by MN2PR12MB4048.namprd12.prod.outlook.com (2603:10b6:208:1d5::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4867.9; Tue, 11 Jan 2022 18:46:08 +0000 Received: from DM6NAM11FT022.eop-nam11.prod.protection.outlook.com (2603:10b6:5:14c:cafe::f4) by DM6PR11CA0049.outlook.office365.com (2603:10b6:5:14c::26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4867.9 via Frontend Transport; Tue, 11 Jan 2022 18:46:08 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.234) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.234 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.234; helo=mail.nvidia.com; Received: from mail.nvidia.com (12.22.5.234) by DM6NAM11FT022.mail.protection.outlook.com (10.13.172.210) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4867.9 via Frontend Transport; Tue, 11 Jan 2022 18:46:08 +0000 Received: from HQMAIL109.nvidia.com (172.20.187.15) by DRHQMAIL101.nvidia.com (10.27.9.10) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 11 Jan 2022 18:46:07 +0000 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 11 Jan 2022 10:46:07 -0800 Received: from amhetre.nvidia.com (10.127.8.9) by mail.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 11 Jan 2022 18:46:05 +0000 From: Ashish Mhetre To: , , , , , CC: , Subject: [Patch V1 3/4] memory: tegra: add mc-err support for T186 Date: Wed, 12 Jan 2022 00:15:49 +0530 Message-ID: <1641926750-27544-4-git-send-email-amhetre@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1641926750-27544-1-git-send-email-amhetre@nvidia.com> References: <1641926750-27544-1-git-send-email-amhetre@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9f0c1262-28a1-4cda-3c0e-08d9d532a195 X-MS-TrafficTypeDiagnostic: MN2PR12MB4048:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:245; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: +eNKrul/PgH8HmAk0rJxI4F0M7YarS6Xx5/EI+ZW+SJzQyyOBRGuCVIzNUmDc/F3MjfZeEc2UHoFyEFXQsLKBD+ZM+Bnin4pCZBgXbSvbL298hyZyZ8zmS+fXSlDZchJ8Ymr3Z4OwH9yfu4mp0SwzFarJ2aC7EEPjUX/g85irIjbV/FWMaJMf4+xAZ6UkdugvCt1jIUuRmRseRkIbMsp0PP1tqsk65gYaDdvXsUGjZL6kxIk1SsJO64R+ZEDQzhTlnqUsStd1/qWI4/DaH5AOsbcet3GH2sAghRDd0VgPjXE5oiDWs85m1iAZ1bZQ6PzrxkZuErGXHnbKAASn+QDtVmD20Mj7STxC20BCdD/9TXc0GOngkEkPgr8QT1Qj9+YChFBaVjmamOWCulyH3EFAqtoEvtcjM1dwJgFNOpbVC9Ql/KghdTzPm9GD1KGzN3j1c86oaiPLfxb2Pq62pLRg4FJ38e1n36N4HtX9NghoObhHij9RANHbgjx8FKMsLbHiK2jXuWD3lzTRTLiXmzVPG5l1kEl5E/0L1IT1WDIQgccsHkVA/g4Th+1N1D2ZawNna/AAKs++a436BFxTOMWBIK/OpZlFHYGuJOOWUF96rMhufj4WZ04M7BqIRZ4HUBqa15b+cFid1blydh2UFSr5oBmNKhEcZyUbay0JX0VywI7vUVK+8+Ctw1ea443zuR9uO86lqkhvS7eHQYxSb0vYURdG56TDeMa06PwVa5MZJudMWP2rLIx38Qh910svNmrqdOE1Dnd66Q+MNVLZ0YwJkGvgGAWQWZNoXwi3Tvsgtw= X-Forefront-Antispam-Report: CIP:12.22.5.234;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(40470700002)(356005)(70206006)(4326008)(8936002)(81166007)(26005)(2906002)(54906003)(36756003)(86362001)(36860700001)(70586007)(47076005)(7696005)(107886003)(40460700001)(508600001)(83380400001)(316002)(6666004)(82310400004)(2616005)(110136005)(426003)(186003)(336012)(5660300002)(8676002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jan 2022 18:46:08.2504 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9f0c1262-28a1-4cda-3c0e-08d9d532a195 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.234];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT022.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4048 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add all mc-errors supported by T186. Implement mc interrupt handling routine for T186. Signed-off-by: Ashish Mhetre --- drivers/memory/tegra/mc.h | 17 +++++++ drivers/memory/tegra/tegra186.c | 100 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 117 insertions(+) diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h index 2d4f495..7817492 100644 --- a/drivers/memory/tegra/mc.h +++ b/drivers/memory/tegra/mc.h @@ -44,6 +44,15 @@ #define MC_TIMING_CONTROL_DBG 0xf8 #define MC_TIMING_CONTROL 0xfc +#define MC_ERR_VPR_STATUS 0x654 +#define MC_ERR_VPR_ADR 0x658 +#define MC_ERR_SEC_STATUS 0x67c +#define MC_ERR_SEC_ADR 0x680 +#define MC_ERR_MTS_STATUS 0x9b0 +#define MC_ERR_MTS_ADR 0x9b4 +#define MC_ERR_GENERALIZED_CARVEOUT_STATUS 0xc00 +#define MC_ERR_GENERALIZED_CARVEOUT_ADR 0xc04 + #define MC_INT_DECERR_ROUTE_SANITY BIT(20) #define MC_INT_WCAM_ERR BIT(19) #define MC_INT_SCRUB_ECC_WR_ACK BIT(18) @@ -159,6 +168,14 @@ extern const struct tegra_mc_ops tegra186_mc_ops; extern const char * const tegra_mc_status_names[32]; extern const char * const tegra_mc_error_names[8]; +struct tegra_mc_error { + u32 int_bit; + const char *msg; + u32 status_reg; + u32 addr_reg; + u32 addr_reg_hi; +}; + /* * These IDs are for internal use of Tegra ICC drivers. The ID numbers are * chosen such that they don't conflict with the device-tree ICC node IDs. diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c index 6766cc4..4f3ae71 100644 --- a/drivers/memory/tegra/tegra186.c +++ b/drivers/memory/tegra/tegra186.c @@ -146,8 +146,107 @@ static void tegra186_mc_clear_interrupt(struct tegra_mc *mc) mc_writel(mc, MC_INTSTATUS_CLEAR, MC_INTSTATUS); } +static const struct tegra_mc_error int_mc_errors[] = { + { + .int_bit = MC_INT_DECERR_EMEM, + .msg = "EMEM address decode error", + .status_reg = MC_ERR_STATUS, + .addr_reg = MC_ERR_ADR, + }, + { + .int_bit = MC_INT_SECURITY_VIOLATION, + .msg = "non secure access to secure region", + .status_reg = MC_ERR_STATUS, + .addr_reg = MC_ERR_ADR, + }, + { + .int_bit = MC_INT_DECERR_VPR, + .msg = "MC request violates VPR requirements", + .status_reg = MC_ERR_VPR_STATUS, + .addr_reg = MC_ERR_VPR_ADR, + }, + { + .int_bit = MC_INT_SECERR_SEC, + .msg = "MC request violated SEC carveout requirements", + .status_reg = MC_ERR_SEC_STATUS, + .addr_reg = MC_ERR_SEC_ADR, + }, + { + .int_bit = MC_INT_DECERR_MTS, + .msg = "MTS carveout access violation", + .status_reg = MC_ERR_MTS_STATUS, + .addr_reg = MC_ERR_MTS_ADR, + }, + { + .int_bit = MC_INT_DECERR_GENERALIZED_CARVEOUT, + .msg = "GSC access violation", + .status_reg = MC_ERR_GENERALIZED_CARVEOUT_STATUS, + .addr_reg = MC_ERR_GENERALIZED_CARVEOUT_ADR, + }, +}; + +static irqreturn_t tegra186_mc_handle_irq(int irq, void *data) +{ + struct tegra_mc *mc = data; + unsigned long status; + unsigned int bit; + + status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask; + if (!status) + return IRQ_NONE; + + for_each_set_bit(bit, &status, 32) { + const char *error = int_mc_errors[bit].msg ?: "unknown"; + const char *client = "unknown"; + const char *direction, *secure; + phys_addr_t addr = 0; + unsigned int i; + u8 id; + u32 value; + + value = mc_readl(mc, int_mc_errors[bit].status_reg); + +#ifdef CONFIG_PHYS_ADDR_T_64BIT + if (mc->soc->num_address_bits > 32) { + addr = ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) & + MC_ERR_STATUS_ADR_HI_MASK); + addr <<= 32; + } +#endif + addr |= mc_readl(mc, int_mc_errors[bit].addr_reg); + + if (value & MC_ERR_STATUS_RW) + direction = "write"; + else + direction = "read"; + + if (value & MC_ERR_STATUS_SECURITY) + secure = "secure "; + else + secure = ""; + + id = value & mc->soc->client_id_mask; + + for (i = 0; i < mc->soc->num_clients; i++) { + if (mc->soc->clients[i].id == id) { + client = mc->soc->clients[i].name; + break; + } + } + + dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s\n", + client, secure, direction, &addr, error); + } + + /* clear interrupts */ + mc_writel(mc, status, MC_INTSTATUS); + + return IRQ_HANDLED; +} + const struct tegra_mc_interrupt_ops tegra186_mc_interrupt_ops = { .clear_interrupt = tegra186_mc_clear_interrupt, + .handle_irq = tegra186_mc_handle_irq, }; const struct tegra_mc_ops tegra186_mc_ops = { @@ -886,6 +985,7 @@ const struct tegra_mc_soc tegra186_mc_soc = { .num_clients = ARRAY_SIZE(tegra186_mc_clients), .clients = tegra186_mc_clients, .num_address_bits = 40, + .client_id_mask = 0xff, .intmask = MC_INT_WCAM_ERR | MC_INT_SCRUB_ECC_WR_ACK | MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | From patchwork Tue Jan 11 18:45:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashish Mhetre X-Patchwork-Id: 1578653 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=oyGTeqAi; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4JYKR16YB5z9s9c for ; Wed, 12 Jan 2022 05:46:21 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350191AbiAKSqU (ORCPT ); Tue, 11 Jan 2022 13:46:20 -0500 Received: from mail-bn7nam10on2089.outbound.protection.outlook.com ([40.107.92.89]:45216 "EHLO NAM10-BN7-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1349997AbiAKSqO (ORCPT ); Tue, 11 Jan 2022 13:46:14 -0500 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=NKtjcDvdOzgkhT3bvtkh0FVSutKX/8PlMvZPt3NO6Pp2UbBcRxoJTys7J3nMUdwL9yRqfhgIkIbdVv5NRBQangDFEBv/7tRlcpmIiJaIVYuOd7Kc2qQ9LWOkhyjSSTz3R9JhvixhYxD/NsFtK8iHR8+g9bPTyS2fQyosBzCaxsM4RaUk1/dHKJ/fdw93RmEq9Crw4vL7zcrEoJeLPyRTInf9RXtr5PTUmQnIHqfbhJM907dwk5lGgePJuKrNgHd/0XfmOAqudMYwYT/DkEOpX2X/Hxs8egXilx/8az1Z97P1gorNz65MMpZT4yfTc/1vGzP58+WVwgwrYW0U1rvpqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=WZzIAog4hER4wmq/II7cBW9bXtZoT79oP9IDSmmXYSU=; b=W+z+qgJUxhr12Q1YD6aLWbVzTZqoiB0wmToEzbXLDQQ/YHEYcNdjTl6w3en0E+wGqRLJZl5Ft820bSIKUSsbYWGLOnLgQAQ3NF/XGXko3yGZ4nmMJ6+L3Lhp7xdrf387lbSzMZkeqDr9HNSE/9LgEPvusJIGLn21OXw6yJ/uBTpgYLeqPtXLUoE2r8EnL+9SGwH6ve3CjpBzos6QMGEhWdGW4TRJtWHsV8vNXELWUEU1CiHhs3iGdl4iipgVz7ILxHrVmNw7QuwTyXjXw8pEHo0MgrWfWPwtKXK1MX2fLDAOCUqb3lHc5wK0mUt0Fe+lxLhNZMhI9pZHR4lbxvi/YQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.236) smtp.rcpttodomain=gmail.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=WZzIAog4hER4wmq/II7cBW9bXtZoT79oP9IDSmmXYSU=; b=oyGTeqAi66t0KlqlmhebVg9q1Wg24nGlTotcj4cnj+8pBh3siRMQn34+b/j28wuSLprcwEVoFXEUNCSdJfmJEJYeLInUm6Ek1OByiCIOt2dtyDX1m6/Dto6xQaSt7ict9zxdoAFc4TpWmhRzQf+JsKm/y2OGHqXLwX3pSSv6N9wMg1M9HP+ngIootqR6UNuy6qf5Mhuqn0kwD1KrCalXEEdgeXCD71fDj1+HMOw0HPrCNf0rBJA2UFeqsKurbmfNuhFPMpVq+7+KO6d7EOB4EBR8bcMnO+N8o9hsN/BF454VGJ7FWW3hoFhD1/HkYPPfUdIJ2fK4XTEN9msOzoQPxA== Received: from DM5PR19CA0053.namprd19.prod.outlook.com (2603:10b6:3:116::15) by DM5PR1201MB0187.namprd12.prod.outlook.com (2603:10b6:4:5b::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4867.9; Tue, 11 Jan 2022 18:46:12 +0000 Received: from DM6NAM11FT067.eop-nam11.prod.protection.outlook.com (2603:10b6:3:116:cafe::c0) by DM5PR19CA0053.outlook.office365.com (2603:10b6:3:116::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4888.9 via Frontend Transport; Tue, 11 Jan 2022 18:46:12 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.236) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.236 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.236; helo=mail.nvidia.com; Received: from mail.nvidia.com (12.22.5.236) by DM6NAM11FT067.mail.protection.outlook.com (10.13.172.76) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4867.9 via Frontend Transport; Tue, 11 Jan 2022 18:46:11 +0000 Received: from HQMAIL109.nvidia.com (172.20.187.15) by DRHQMAIL109.nvidia.com (10.27.9.19) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 11 Jan 2022 18:46:11 +0000 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 11 Jan 2022 10:46:11 -0800 Received: from amhetre.nvidia.com (10.127.8.9) by mail.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 11 Jan 2022 18:46:09 +0000 From: Ashish Mhetre To: , , , , , CC: , Subject: [Patch V1 4/4] memory: tegra: add mc-err support for T194 Date: Wed, 12 Jan 2022 00:15:50 +0530 Message-ID: <1641926750-27544-5-git-send-email-amhetre@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1641926750-27544-1-git-send-email-amhetre@nvidia.com> References: <1641926750-27544-1-git-send-email-amhetre@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 68804713-fa48-42ff-c8c2-08d9d532a3b4 X-MS-TrafficTypeDiagnostic: DM5PR1201MB0187:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:168; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: RynJXY3uWiIOsAWZy+Evsz0FMvpwfjfimq8zng7LdPxVaas4P3ZLlbpD+VDA2DMV+OuGaT6r/czNuFwPDXoHeJ/SGRjsIe0kG6uyXLraHSrftCZIF3Ziu1y5/vOjnAVRo2XtmnqwWWAyxYlqgbPiLw5wOlEXffEg0CIDsqgWYSoSFybKtmoND0w6ol8nqzmv1jp58hglKmzvuduTy0XfUwkbKYHthhEhbX4L88jt/d+N0BlezMPLQHhlss2Kf3zcRbN62NUnABVsmIg5q5x7zDMNAThTH6SRXvieLsSytXmgHjPsb96T1/0DTdxCQFwHKsj3reSBPiLPdqQt+qWXrlCfLPBABcftNf8nPzoaMSPcwrFlQyN2n4GfsSl6NJBATTBIFlcZm8mNOWR452bSU4NfWyEOUKVcIPmarFofPuWnoUJzgD3XFWcI8GP28Tisrr9MIWKcBpIZ3YDvHbYo1W1qqEK4nrzVTW4AAa2tVkHk24m58PxELcu9j2++GovD3k8ZjLOVZsDbH1HSeULZp4g7U49LWhegX7ikegMMEwOykPOF7bSXK/3TTUy0C5JoTbzNSfc56V2g2ituHkPOqlJIXKTvUVS+1lhd6YfASAEVR5+ZcB5uFu4nTUbyi0looSPbfMUrzIRT2hNP6R6YMcuaW0GEbhGBjjBML9JRAEjtI/L96fUFcJOYet2g3lVVsaw2d0AkgmDAiu26nvo4HwW8wo6c6EFK69TFNyQyJQPyfFeQFcgNYEttuYw4vTNI+Ypka61wXM370REyNzgXiwY/cVug66mtjcmA+STA6Dg= X-Forefront-Antispam-Report: CIP:12.22.5.236;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(4636009)(40470700002)(46966006)(36840700001)(426003)(5660300002)(26005)(86362001)(36756003)(82310400004)(7696005)(36860700001)(70586007)(316002)(110136005)(4326008)(107886003)(508600001)(40460700001)(356005)(6666004)(70206006)(81166007)(186003)(8936002)(8676002)(54906003)(2616005)(47076005)(2906002)(83380400001)(336012)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jan 2022 18:46:11.9844 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 68804713-fa48-42ff-c8c2-08d9d532a3b4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.236];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT067.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR1201MB0187 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add all basic mc-errors supported by T194. Implement mc interrupt handling routine for T194. Signed-off-by: Ashish Mhetre --- drivers/memory/tegra/mc.h | 2 + drivers/memory/tegra/tegra194.c | 108 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 110 insertions(+) diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h index 7817492..1d881e7 100644 --- a/drivers/memory/tegra/mc.h +++ b/drivers/memory/tegra/mc.h @@ -43,6 +43,7 @@ #define MC_EMEM_ARB_OVERRIDE 0xe8 #define MC_TIMING_CONTROL_DBG 0xf8 #define MC_TIMING_CONTROL 0xfc +#define MC_ERR_ADR_HI 0x11fc #define MC_ERR_VPR_STATUS 0x654 #define MC_ERR_VPR_ADR 0x658 @@ -50,6 +51,7 @@ #define MC_ERR_SEC_ADR 0x680 #define MC_ERR_MTS_STATUS 0x9b0 #define MC_ERR_MTS_ADR 0x9b4 +#define MC_ERR_GENERALIZED_CARVEOUT_STATUS_1 0xbfc #define MC_ERR_GENERALIZED_CARVEOUT_STATUS 0xc00 #define MC_ERR_GENERALIZED_CARVEOUT_ADR 0xc04 diff --git a/drivers/memory/tegra/tegra194.c b/drivers/memory/tegra/tegra194.c index 76ba3da..a0af6a0 100644 --- a/drivers/memory/tegra/tegra194.c +++ b/drivers/memory/tegra/tegra194.c @@ -4,6 +4,7 @@ */ #include +#include #include @@ -16,8 +17,114 @@ static void tegra194_mc_clear_interrupt(struct tegra_mc *mc) mc_writel(mc, MC_INTSTATUS_CLEAR, MC_INTSTATUS); } +static const struct tegra_mc_error int_mc_errors[] = { + { + .int_bit = MC_INT_DECERR_EMEM, + .msg = "EMEM address decode error", + .status_reg = MC_ERR_STATUS, + .addr_reg = MC_ERR_ADR, + .addr_reg_hi = MC_ERR_ADR_HI, + }, + { + .int_bit = MC_INT_SECURITY_VIOLATION, + .msg = "non secure access to secure region", + .status_reg = MC_ERR_STATUS, + .addr_reg = MC_ERR_ADR, + .addr_reg_hi = MC_ERR_ADR_HI, + }, + { + .int_bit = MC_INT_DECERR_VPR, + .msg = "MC request violates VPR requirements", + .status_reg = MC_ERR_VPR_STATUS, + .addr_reg = MC_ERR_VPR_ADR, + }, + { + .int_bit = MC_INT_SECERR_SEC, + .msg = "MC request violated SEC carveout requirements", + .status_reg = MC_ERR_SEC_STATUS, + .addr_reg = MC_ERR_SEC_ADR, + }, + { + .int_bit = MC_INT_DECERR_MTS, + .msg = "MTS carveout access violation", + .status_reg = MC_ERR_MTS_STATUS, + .addr_reg = MC_ERR_MTS_ADR, + }, + { + .int_bit = MC_INT_DECERR_GENERALIZED_CARVEOUT, + .msg = "GSC access violation", + .status_reg = MC_ERR_GENERALIZED_CARVEOUT_STATUS, + .addr_reg = MC_ERR_GENERALIZED_CARVEOUT_ADR, + .addr_reg_hi = MC_ERR_GENERALIZED_CARVEOUT_STATUS_1, + }, +}; + +static irqreturn_t tegra194_mc_handle_irq(int irq, void *data) +{ + struct tegra_mc *mc = data; + unsigned long status; + unsigned int bit; + + status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask; + if (!status) + return IRQ_NONE; + + for_each_set_bit(bit, &status, 32) { + const char *error = int_mc_errors[bit].msg ?: "unknown"; + const char *client = "unknown"; + const char *direction, *secure; + phys_addr_t addr = 0; + unsigned int i; + u8 id; + u32 value; + + value = mc_readl(mc, int_mc_errors[bit].status_reg); + +#ifdef CONFIG_PHYS_ADDR_T_64BIT + if (mc->soc->num_address_bits > 32) { + if (int_mc_errors[bit].addr_reg_hi) + addr = mc_readl(mc, + int_mc_errors[bit].addr_reg_hi); + else + addr = ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) & + MC_ERR_STATUS_ADR_HI_MASK); + addr <<= 32; + } +#endif + addr |= mc_readl(mc, int_mc_errors[bit].addr_reg); + + if (value & MC_ERR_STATUS_RW) + direction = "write"; + else + direction = "read"; + + if (value & MC_ERR_STATUS_SECURITY) + secure = "secure "; + else + secure = ""; + + id = value & mc->soc->client_id_mask; + + for (i = 0; i < mc->soc->num_clients; i++) { + if (mc->soc->clients[i].id == id) { + client = mc->soc->clients[i].name; + break; + } + } + + dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s\n", + client, secure, direction, &addr, error); + } + + /* clear interrupts */ + mc_writel(mc, status, MC_INTSTATUS); + + return IRQ_HANDLED; +} + const struct tegra_mc_interrupt_ops tegra194_mc_interrupt_ops = { .clear_interrupt = tegra194_mc_clear_interrupt, + .handle_irq = tegra194_mc_handle_irq, }; static const struct tegra_mc_client tegra194_mc_clients[] = { @@ -1358,6 +1465,7 @@ const struct tegra_mc_soc tegra194_mc_soc = { .num_clients = ARRAY_SIZE(tegra194_mc_clients), .clients = tegra194_mc_clients, .num_address_bits = 40, + .client_id_mask = 0xff, .intmask = MC_INT_DECERR_ROUTE_SANITY | MC_INT_WCAM_ERR | MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |