From patchwork Fri Dec 24 07:25:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 1572972 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=Eni3GC0C; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4JKzBS5fW6z9sR4 for ; Fri, 24 Dec 2021 18:26:08 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 0B09D83774; Fri, 24 Dec 2021 08:25:59 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="Eni3GC0C"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 0701783510; Fri, 24 Dec 2021 08:25:51 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 18BE583691 for ; Fri, 24 Dec 2021 08:25:47 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=vigneshr@ti.com Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 1BO7PkAm060259; Fri, 24 Dec 2021 01:25:46 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1640330746; bh=LJS3eB01ZVxZi89Hei2+9Nd5rxsgdlhUafP4qRzj8kA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Eni3GC0CWuXEV7/iR0ZwU5HKZAI+6SkxaJhTh16PjvDEU/gCOsTv1ZkKW/LtupTsF +vRhRiEKQIwE8F1eR5WnmGNFKx7Lol29hhOw/fUO2s7IDXHJguWs4PqaM078pWFyKt aYqL2taGhgF0cQ+wBlBpH9m8s/L1pwH0GnjP73og= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 1BO7PjaY091474 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 24 Dec 2021 01:25:45 -0600 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Fri, 24 Dec 2021 01:25:45 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Fri, 24 Dec 2021 01:25:45 -0600 Received: from ula0132425.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 1BO7PcJR097108; Fri, 24 Dec 2021 01:25:43 -0600 From: Vignesh Raghavendra To: Dave Gerlach , Joe Hershberger , Ramon Fried , Tom Rini CC: , Vignesh Raghavendra , Grygorii Strashko Subject: [PATCH 1/8] mach-k3: common: Instantiate AM65 CPSW NUSS wrapper Date: Fri, 24 Dec 2021 12:55:29 +0530 Message-ID: <20211224072536.270251-2-vigneshr@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211224072536.270251-1-vigneshr@ti.com> References: <20211224072536.270251-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Probe toplevel AM65 CPSW NUSS driver from misc_init_r() when driver is enabled. Since driver is modeled as UCLASS_MISC, we need to explicitly probe the driver. Use common misc_init_r() that entire K3 family of SoCs. Signed-off-by: Vignesh Raghavendra --- arch/arm/mach-k3/common.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index 2666cd2d7b..39d00270b7 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -549,3 +549,19 @@ void spl_board_prepare_for_linux(void) dcache_disable(); } #endif + +int misc_init_r(void) +{ + if (IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS)) { + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(am65_cpsw_nuss), + &dev); + if (ret) + printf("Failed to probe am65_cpsw_nuss driver\n"); + } + + return 0; +} From patchwork Fri Dec 24 07:25:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 1572973 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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Fri, 24 Dec 2021 01:25:48 -0600 Received: from ula0132425.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 1BO7PcJS097108; Fri, 24 Dec 2021 01:25:46 -0600 From: Vignesh Raghavendra To: Dave Gerlach , Joe Hershberger , Ramon Fried , Tom Rini CC: , Vignesh Raghavendra , Grygorii Strashko Subject: [PATCH 2/8] net: ti: am65-cpsw: Add support for multi port independent MAC mode Date: Fri, 24 Dec 2021 12:55:30 +0530 Message-ID: <20211224072536.270251-3-vigneshr@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211224072536.270251-1-vigneshr@ti.com> References: <20211224072536.270251-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean On certain TI SoC, like AM64x there is a CPSW3G which supports 2 external independent MAC ports for single CPSW instance. It is not possible for Ethernet driver to register more than one port for given instance. This patch modifies top level CPSW NUSS as UCLASS_MISC and binds UCLASS_ETH to individual ports so as to support bring up more than one Ethernet interface in U-Boot. Note that there is no isolation in the since, CPSW NUSS is in promisc mode and forwards all packets to host. Since top level driver is now UCLASS_MISC, board files would need to instantiate this driver explicitly. Signed-off-by: Vignesh Raghavendra --- drivers/net/ti/Kconfig | 2 + drivers/net/ti/am65-cpsw-nuss.c | 77 +++++++++++++++++++++------------ 2 files changed, 52 insertions(+), 27 deletions(-) diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig index f2dbbd0128..59c96d862d 100644 --- a/drivers/net/ti/Kconfig +++ b/drivers/net/ti/Kconfig @@ -28,6 +28,8 @@ config DRIVER_TI_KEYSTONE_NET config TI_AM65_CPSW_NUSS bool "TI K3 AM65x MCU CPSW Nuss Ethernet controller driver" depends on ARCH_K3 + imply MISC_INIT_R + imply MISC select PHYLIB help This driver supports TI K3 MCU CPSW Nuss Ethernet controller diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c index 3ab6a30828..6ae69b51c7 100644 --- a/drivers/net/ti/am65-cpsw-nuss.c +++ b/drivers/net/ti/am65-cpsw-nuss.c @@ -597,7 +597,7 @@ static int am65_cpsw_phy_init(struct udevice *dev) return ret; } -static int am65_cpsw_ofdata_parse_phy(struct udevice *dev, ofnode port_np) +static int am65_cpsw_ofdata_parse_phy(struct udevice *dev) { struct eth_pdata *pdata = dev_get_plat(dev); struct am65_cpsw_priv *priv = dev_get_priv(dev); @@ -605,7 +605,9 @@ static int am65_cpsw_ofdata_parse_phy(struct udevice *dev, ofnode port_np) const char *phy_mode; int ret = 0; - phy_mode = ofnode_read_string(port_np, "phy-mode"); + dev_read_u32(dev, "reg", &priv->port_id); + + phy_mode = dev_read_string(dev, "phy-mode"); if (phy_mode) { pdata->phy_interface = phy_get_interface_by_name(phy_mode); @@ -617,13 +619,13 @@ static int am65_cpsw_ofdata_parse_phy(struct udevice *dev, ofnode port_np) } } - ofnode_read_u32(port_np, "max-speed", (u32 *)&pdata->max_speed); + dev_read_u32(dev, "max-speed", (u32 *)&pdata->max_speed); if (pdata->max_speed) dev_err(dev, "Port %u speed froced to %uMbit\n", priv->port_id, pdata->max_speed); priv->has_phy = true; - ret = ofnode_parse_phandle_with_args(port_np, "phy-handle", + ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "phy-handle", NULL, 0, 0, &out_args); if (ret) { dev_err(dev, "can't parse phy-handle port %u (%d)\n", @@ -646,21 +648,46 @@ out: return ret; } -static int am65_cpsw_probe_cpsw(struct udevice *dev) +static int am65_cpsw_port_probe(struct udevice *dev) { struct am65_cpsw_priv *priv = dev_get_priv(dev); struct eth_pdata *pdata = dev_get_plat(dev); struct am65_cpsw_common *cpsw_common; - ofnode ports_np, node; - int ret, i; + char portname[15]; + int ret; priv->dev = dev; - cpsw_common = calloc(1, sizeof(*priv->cpsw_common)); - if (!cpsw_common) - return -ENOMEM; + cpsw_common = dev_get_priv(dev->parent); priv->cpsw_common = cpsw_common; + sprintf(portname, "%s%s", dev->parent->name, dev->name); + device_set_name(dev, portname); + + ret = am65_cpsw_ofdata_parse_phy(dev); + if (ret) + goto out; + + am65_cpsw_gmii_sel_k3(priv, pdata->phy_interface, priv->port_id); + + ret = am65_cpsw_mdio_init(dev); + if (ret) + goto out; + + ret = am65_cpsw_phy_init(dev); + if (ret) + goto out; +out: + return ret; +} + +static int am65_cpsw_probe_nuss(struct udevice *dev) +{ + struct am65_cpsw_common *cpsw_common = dev_get_priv(dev); + ofnode ports_np, node; + int ret, i; + struct udevice *port_dev; + cpsw_common->dev = dev; cpsw_common->ss_base = dev_read_addr(dev); if (cpsw_common->ss_base == FDT_ADDR_T_NONE) @@ -723,10 +750,9 @@ static int am65_cpsw_probe_cpsw(struct udevice *dev) if (disabled) continue; - priv->port_id = port_id; - ret = am65_cpsw_ofdata_parse_phy(dev, node); + ret = device_bind_driver_to_node(dev, "am65_cpsw_nuss_port", ofnode_get_name(node), node, &port_dev); if (ret) - goto out; + printf("SCREEEM\n"); } for (i = 0; i < AM65_CPSW_CPSWNU_MAX_PORTS; i++) { @@ -756,16 +782,6 @@ static int am65_cpsw_probe_cpsw(struct udevice *dev) dev_read_u32_default(dev, "bus_freq", AM65_CPSW_MDIO_BUS_FREQ_DEF); - am65_cpsw_gmii_sel_k3(priv, pdata->phy_interface, priv->port_id); - - ret = am65_cpsw_mdio_init(dev); - if (ret) - goto out; - - ret = am65_cpsw_phy_init(dev); - if (ret) - goto out; - dev_info(dev, "K3 CPSW: nuss_ver: 0x%08X cpsw_ver: 0x%08X ale_ver: 0x%08X Ports:%u mdio_freq:%u\n", readl(cpsw_common->ss_base), readl(cpsw_common->cpsw_base), @@ -786,11 +802,18 @@ static const struct udevice_id am65_cpsw_nuss_ids[] = { { } }; -U_BOOT_DRIVER(am65_cpsw_nuss_slave) = { - .name = "am65_cpsw_nuss_slave", - .id = UCLASS_ETH, +U_BOOT_DRIVER(am65_cpsw_nuss) = { + .name = "am65_cpsw_nuss", + .id = UCLASS_MISC, .of_match = am65_cpsw_nuss_ids, - .probe = am65_cpsw_probe_cpsw, + .probe = am65_cpsw_probe_nuss, + .priv_auto = sizeof(struct am65_cpsw_common), +}; + +U_BOOT_DRIVER(am65_cpsw_nuss_port) = { + .name = "am65_cpsw_nuss_port", + .id = UCLASS_ETH, + .probe = am65_cpsw_port_probe, .ops = &am65_cpsw_ops, .priv_auto = sizeof(struct am65_cpsw_priv), .plat_auto = sizeof(struct eth_pdata), From patchwork Fri Dec 24 07:25:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 1572974 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=HqM5ebNL; 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Fri, 24 Dec 2021 01:25:52 -0600 Received: from ula0132425.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 1BO7PcJT097108; Fri, 24 Dec 2021 01:25:49 -0600 From: Vignesh Raghavendra To: Dave Gerlach , Joe Hershberger , Ramon Fried , Tom Rini CC: , Vignesh Raghavendra , Grygorii Strashko Subject: [PATCH 3/8] board: ti: am64x: Init DRAM size in R5/A53 SPL Date: Fri, 24 Dec 2021 12:55:31 +0530 Message-ID: <20211224072536.270251-4-vigneshr@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211224072536.270251-1-vigneshr@ti.com> References: <20211224072536.270251-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Call dram_init_banksize() from spl_board_init() otherwise TFTP download fails due to lmb_get_free_size() not able to find unreserved region due to lack of DRAM size info. Required to support Ethernet boot on AM64x. Signed-off-by: Vignesh Raghavendra --- board/ti/am64x/evm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/board/ti/am64x/evm.c b/board/ti/am64x/evm.c index 1a9f69c6cf..8373c768f1 100644 --- a/board/ti/am64x/evm.c +++ b/board/ti/am64x/evm.c @@ -196,5 +196,8 @@ void spl_board_init(void) val = readl(CTRLMMR_USB0_PHY_CTRL); val &= ~(CORE_VOLTAGE); writel(val, CTRLMMR_USB0_PHY_CTRL); + + /* Init DRAM size for R5/A53 SPL */ + dram_init_banksize(); } #endif From patchwork Fri Dec 24 07:25:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 1572975 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=ubKo5tzi; dkim-atps=neutral Authentication-Results: ozlabs.org; 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a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1640330756; bh=Ld2Qn0dGjfnjCC1NiFOUfuHXA3bj+0775DeUHYhOUco=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ubKo5tzicgnZHU5gzfPNmzj2IpXe6F6q0O7KqYV7Y65pPvds8y5ADiHqe0e4SeEzU fTGO/CpTKwUVy4JKcrupAN0+ECK6iveQKHMHk89Yu0acb0X6a71m7jH3q8pbNHe2+U UhR3WhdbmBwfTVpPIP0mvgX0tKf5J4pDFRnonago= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 1BO7PuKn091558 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 24 Dec 2021 01:25:56 -0600 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Fri, 24 Dec 2021 01:25:56 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Fri, 24 Dec 2021 01:25:56 -0600 Received: from ula0132425.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 1BO7PcJU097108; Fri, 24 Dec 2021 01:25:53 -0600 From: Vignesh Raghavendra To: Dave Gerlach , Joe Hershberger , Ramon Fried , Tom Rini CC: , Vignesh Raghavendra , Grygorii Strashko Subject: [PATCH 4/8] mach-k3: am642_init: Probe AM65 CPSW NUSS for R5/A53 SPL Date: Fri, 24 Dec 2021 12:55:32 +0530 Message-ID: <20211224072536.270251-5-vigneshr@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211224072536.270251-1-vigneshr@ti.com> References: <20211224072536.270251-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean In order to support Ethernet boot on AM64x, probe AM65 CPSW NUSS. Signed-off-by: Vignesh Raghavendra --- arch/arm/mach-k3/am642_init.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c index 533905daeb..184f1a2761 100644 --- a/arch/arm/mach-k3/am642_init.c +++ b/arch/arm/mach-k3/am642_init.c @@ -196,6 +196,13 @@ void board_init_f(ulong dummy) if (ret) panic("DRAM init failed: %d\n", ret); #endif + if (IS_ENABLED(CONFIG_SPL_ETH) && IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS) && + spl_boot_device() == BOOT_DEVICE_ETHERNET) { + struct udevice *cpswdev; + + if (uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(am65_cpsw_nuss), &cpswdev)) + printf("Failed to probe am65_cpsw_nuss driver\n"); + } } u32 spl_mmc_boot_mode(const u32 boot_device) From patchwork Fri Dec 24 07:25:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 1572976 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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Fri, 24 Dec 2021 01:25:59 -0600 Received: from ula0132425.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 1BO7PcJV097108; Fri, 24 Dec 2021 01:25:56 -0600 From: Vignesh Raghavendra To: Dave Gerlach , Joe Hershberger , Ramon Fried , Tom Rini CC: , Vignesh Raghavendra , Grygorii Strashko Subject: [PATCH 5/8] mach-k3: am64_spl: Alias Ethernet RGMII boot to CPGMAC Date: Fri, 24 Dec 2021 12:55:33 +0530 Message-ID: <20211224072536.270251-6-vigneshr@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211224072536.270251-1-vigneshr@ti.com> References: <20211224072536.270251-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean This is required to enables spl_net boot on AM64x Signed-off-by: Vignesh Raghavendra --- arch/arm/mach-k3/include/mach/am64_spl.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-k3/include/mach/am64_spl.h b/arch/arm/mach-k3/include/mach/am64_spl.h index 607b09c2e5..b4f396b2c0 100644 --- a/arch/arm/mach-k3/include/mach/am64_spl.h +++ b/arch/arm/mach-k3/include/mach/am64_spl.h @@ -12,6 +12,7 @@ #define BOOT_DEVICE_QSPI 0x02 #define BOOT_DEVICE_SPI 0x03 #define BOOT_DEVICE_ETHERNET 0x04 +#define BOOT_DEVICE_CPGMAC 0x04 #define BOOT_DEVICE_ETHERNET_RGMII 0x04 #define BOOT_DEVICE_ETHERNET_RMII 0x05 #define BOOT_DEVICE_I2C 0x06 From patchwork Fri Dec 24 07:25:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 1572977 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=v265ph/V; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4JKzCR139Bz9sR4 for ; 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Fri, 24 Dec 2021 01:26:02 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Fri, 24 Dec 2021 01:26:02 -0600 Received: from ula0132425.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 1BO7PcJW097108; Fri, 24 Dec 2021 01:26:00 -0600 From: Vignesh Raghavendra To: Dave Gerlach , Joe Hershberger , Ramon Fried , Tom Rini CC: , Vignesh Raghavendra , Grygorii Strashko Subject: [PATCH 6/8] configs: am64x_evm: set eth1 as boot interface Date: Fri, 24 Dec 2021 12:55:34 +0530 Message-ID: <20211224072536.270251-7-vigneshr@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211224072536.270251-1-vigneshr@ti.com> References: <20211224072536.270251-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean ROM supports boot from CPSW second port, therefore set eth1 boot interface Signed-off-by: Vignesh Raghavendra --- include/configs/am64x_evm.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h index 99624081c3..cd4b658e5f 100644 --- a/include/configs/am64x_evm.h +++ b/include/configs/am64x_evm.h @@ -33,7 +33,7 @@ * our memory footprint. The less we use for BSS the more we have available * for everything else. */ -#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 +#define CONFIG_SPL_BSS_MAX_SIZE 0xa000 /* * Link BSS to be within SPL in a dedicated region located near the top of * the MCU SRAM, this way making it available also before relocation. Note @@ -64,6 +64,7 @@ "if test $fdtfile = undefined; then " \ "echo WARNING: Could not determine device tree to use; fi; \0" \ "name_kern=Image\0" \ + "ethact=eth0\0" \ "console=ttyS2,115200n8\0" \ "args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000 " \ "${mtdparts}\0" \ @@ -140,4 +141,6 @@ #define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_ETH_DEVICE "eth1" + #endif /* __CONFIG_AM642_EVM_H */ From patchwork Fri Dec 24 07:25:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 1572978 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=S01IntG2; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; 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Fri, 24 Dec 2021 01:26:04 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Fri, 24 Dec 2021 01:26:04 -0600 Received: from ula0132425.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 1BO7PcJX097108; Fri, 24 Dec 2021 01:26:02 -0600 From: Vignesh Raghavendra To: Dave Gerlach , Joe Hershberger , Ramon Fried , Tom Rini CC: , Vignesh Raghavendra , Grygorii Strashko Subject: [PATCH 7/8] ARM: dts: K3-am642-r5-sk: Enable Second CPSW port in R5/A53 SPL Date: Fri, 24 Dec 2021 12:55:35 +0530 Message-ID: <20211224072536.270251-8-vigneshr@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211224072536.270251-1-vigneshr@ti.com> References: <20211224072536.270251-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Enable Second Ethernet port on which ROM support Ethboot. Signed-off-by: Vignesh Raghavendra --- arch/arm/dts/k3-am642-r5-sk.dts | 74 ++++++++++++++++++++++++++++ arch/arm/dts/k3-am642-sk-u-boot.dtsi | 40 ++++++++++++++- 2 files changed, 113 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/k3-am642-r5-sk.dts b/arch/arm/dts/k3-am642-r5-sk.dts index 79eff8259f..b4a0438449 100644 --- a/arch/arm/dts/k3-am642-r5-sk.dts +++ b/arch/arm/dts/k3-am642-r5-sk.dts @@ -5,6 +5,8 @@ /dts-v1/; +#include +#include #include "k3-am642.dtsi" #include "k3-am64-sk-lp4-1333MTs.dtsi" #include "k3-am64-ddr.dtsi" @@ -107,6 +109,47 @@ AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */ >; }; + + mdio1_pins_default: mdio1-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ + AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ + >; + }; + + rgmii1_pins_default: rgmii1-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */ + AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */ + AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */ + AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */ + AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */ + AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */ + AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */ + AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */ + AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */ + AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */ + AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */ + AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */ + >; + }; + + rgmii2_pins_default: rgmii2-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ + AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ + AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */ + AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */ + AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */ + AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */ + AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */ + AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */ + AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */ + AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */ + AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */ + AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ + >; + }; }; &dmsc { @@ -142,4 +185,35 @@ pinctrl-0 = <&main_mmc1_pins_default>; }; +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&mdio1_pins_default + &rgmii1_pins_default + &rgmii2_pins_default>; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy0>; +}; + +&cpsw_port2 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy1>; +}; + +&cpsw3g_mdio { + cpsw3g_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + }; + + cpsw3g_phy1: ethernet-phy@1 { + reg = <1>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + }; +}; + #include "k3-am642-sk-u-boot.dtsi" diff --git a/arch/arm/dts/k3-am642-sk-u-boot.dtsi b/arch/arm/dts/k3-am642-sk-u-boot.dtsi index efbcfb36e9..ade040e601 100644 --- a/arch/arm/dts/k3-am642-sk-u-boot.dtsi +++ b/arch/arm/dts/k3-am642-sk-u-boot.dtsi @@ -100,13 +100,51 @@ <0x0 0x43000200 0x0 0x8>; reg-names = "cpsw_nuss", "mac_efuse"; /delete-property/ ranges; + u-boot,dm-spl; cpsw-phy-sel@04044 { compatible = "ti,am64-phy-gmii-sel"; reg = <0x0 0x43004044 0x0 0x8>; + u-boot,dm-spl; + }; + + ethernet-ports { + u-boot,dm-spl; }; }; &cpsw_port2 { - status = "disabled"; + u-boot,dm-spl; +}; + +&cpsw_port1 { + u-boot,dm-spl; +}; + +&main_bcdma { + u-boot,dm-spl; +}; + +&main_pktdma { + u-boot,dm-spl; +}; + +&rgmii1_pins_default { + u-boot,dm-spl; +}; + +&rgmii2_pins_default { + u-boot,dm-spl; +}; + +&mdio1_pins_default { + u-boot,dm-spl; +}; + +&cpsw3g_phy0 { + u-boot,dm-spl; +}; + +&cpsw3g_phy1 { + u-boot,dm-spl; }; From patchwork Fri Dec 24 07:25:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 1572979 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=lTsDuR9b; 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Fri, 24 Dec 2021 01:26:07 -0600 Received: from ula0132425.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 1BO7PcJY097108; Fri, 24 Dec 2021 01:26:05 -0600 From: Vignesh Raghavendra To: Dave Gerlach , Joe Hershberger , Ramon Fried , Tom Rini CC: , Vignesh Raghavendra , Grygorii Strashko Subject: [PATCH 8/8] configs: am64x_evm_r5/a53_defconfig: Enable configs required for Ethboot Date: Fri, 24 Dec 2021 12:55:36 +0530 Message-ID: <20211224072536.270251-9-vigneshr@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211224072536.270251-1-vigneshr@ti.com> References: <20211224072536.270251-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.38 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Enable config options needed to support Ethernet boot on AM64x SK. Signed-off-by: Vignesh Raghavendra --- configs/am64x_evm_a53_defconfig | 4 ++++ configs/am64x_evm_r5_defconfig | 12 ++++++++++++ 2 files changed, 16 insertions(+) diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig index aafbb410b6..b8add31a30 100644 --- a/configs/am64x_evm_a53_defconfig +++ b/configs/am64x_evm_a53_defconfig @@ -28,6 +28,7 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run run_kern" CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y @@ -36,8 +37,11 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_DMA=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y +CONFIG_SPL_ETH=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_NET=y +CONFIG_SPL_NET_VCI_STRING="AM64X U-Boot A53 SPL" CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig index f564fa064e..01c1bc02ae 100644 --- a/configs/am64x_evm_r5_defconfig +++ b/configs/am64x_evm_r5_defconfig @@ -36,10 +36,14 @@ CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_EARLY_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 +CONFIG_SPL_DMA=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y +CONFIG_SPL_ETH=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_NET=y +CONFIG_SPL_NET_VCI_STRING="AM64X U-Boot R5 SPL" CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_SUPPORT=y @@ -61,6 +65,7 @@ CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y CONFIG_CMD_TIME=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y @@ -84,12 +89,15 @@ CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000 +CONFIG_DMA_CHANNELS=y +CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_TI_SCI_PROTOCOL=y CONFIG_DA8XX_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_OMAP24XX=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y +CONFIG_SPL_MISC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y CONFIG_SPL_MMC_SDHCI_ADMA=y @@ -97,6 +105,9 @@ CONFIG_MMC_SDHCI_AM654=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_TI_DP83867=y +CONFIG_DM_ETH=y +CONFIG_TI_AM65_CPSW_NUSS=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set CONFIG_SPL_PINCTRL=y @@ -114,6 +125,7 @@ CONFIG_DM_RESET=y CONFIG_RESET_TI_SCI=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y +CONFIG_SOC_TI=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_CADENCE_QSPI=y