From patchwork Sat Dec 18 14:10:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 1570502 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=GFyZ96bt; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4JGSRt50kcz9sRR for ; Sun, 19 Dec 2021 01:10:34 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233340AbhLROKd (ORCPT ); Sat, 18 Dec 2021 09:10:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48192 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233335AbhLROKd (ORCPT ); Sat, 18 Dec 2021 09:10:33 -0500 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5FE8DC06173F for ; Sat, 18 Dec 2021 06:10:32 -0800 (PST) Received: by mail-lf1-x134.google.com with SMTP id k37so10819516lfv.3 for ; Sat, 18 Dec 2021 06:10:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tkCGnjxecVs6iJ5OhJolrVkfI81Gc2C3djNJPu21hcI=; b=GFyZ96bt5P1Tdq7Rdod0rseW5Qkj+OeJeADZWdowfdTwcFDkf8x2BxjroPSizd1tPy zwUUP1uzUnxvrGZhAGfEI66MN6BCltA4Kd/HJLIn82oICdx5A/SfvFp2eMg6+G7ECvFR HrPOsxoPyJcuB41676w7LRSU6HL88vB5JUozjLMmIppYTPmOIf0GtwdCOXg11YNuUy0w YygMfwwbtUrkiS3ITRGoTkQ9NIpesQR5fFTIoYvfFh3pK0ZxhPEZEp9dnjgb7XNN74YU FqjBoM2BpbPb7N538F9vi9eT9TYO3pxjartRZjuAoIZ6CR/I9b6IMD22K/FmM9EourUM CbzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tkCGnjxecVs6iJ5OhJolrVkfI81Gc2C3djNJPu21hcI=; b=ZfqLYT9SFf7kQqLjsnZcQkWa29U3pWL0E/oh77rlRjrEqfRGUZZfg/QYDoSDAnmyfn Os0XW+uvb0GaQntyA29tqXq58V7yN7MeMFgiSnc0AtgCJQy/eEmxO/Gvc4CS/Rq6tP5S MUw9ulW6QnZx7evb+5o7wqJtllGwLXJari7qqgAdL/WasUL8Adp6BmUoOGOz04EM4cl2 9dMppPJ5V//yyfDSpj+JpN6dbzomVW3GIkURDWSJ7nLaB0I5yJcT2k2zJ1K6UKTmQYH0 Jc1LWX/5qMjsC4/4sPIlXrGtiFAucRQxq3dBWGWO0joutcqWtmpSIwVRiTC3ijODzafq qlKQ== X-Gm-Message-State: AOAM5304GmX5YC4wQYmOTvFAGA/c8Q823rbZiIRSB0wLzibA+VLGf27Q BUvJM19Ib44+WM1wv1eY27AzBOpLl1IygTQL X-Google-Smtp-Source: ABdhPJy5/t4pXWcG0z5Cg2A8VE9LuZpptJFuMFz/QjV74cxv/fgkZu5Wto1gxgsGm6nwyH2eDjJINg== X-Received: by 2002:a19:8c48:: with SMTP id i8mr7449715lfj.179.1639836630630; Sat, 18 Dec 2021 06:10:30 -0800 (PST) Received: from eriador.lan ([2001:470:dd84:abc0::8a5]) by smtp.gmail.com with ESMTPSA id c2sm145789lfh.189.2021.12.18.06.10.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Dec 2021 06:10:30 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Vinod Koul , Kishon Vijay Abraham I , Stanimir Varbanov , Lorenzo Pieralisi Cc: Bjorn Helgaas , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v5 1/5] dt-bindings: pci: qcom: Document PCIe bindings for SM8450 Date: Sat, 18 Dec 2021 17:10:20 +0300 Message-Id: <20211218141024.500952-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211218141024.500952-1-dmitry.baryshkov@linaro.org> References: <20211218141024.500952-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Document the PCIe DT bindings for SM8450 SoC. The PCIe IP is similar to the one used on SM8250, however unlike SM8250, PCIe0 and PCIe1 use different set of clocks, so two compatible entries are required. Signed-off-by: Dmitry Baryshkov Reviewed-by: Rob Herring Reviewed-by: Bjorn Andersson --- .../devicetree/bindings/pci/qcom,pcie.txt | 22 ++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index a0ae024c2d0c..0adb56d5645e 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -15,6 +15,8 @@ - "qcom,pcie-sc8180x" for sc8180x - "qcom,pcie-sdm845" for sdm845 - "qcom,pcie-sm8250" for sm8250 + - "qcom,pcie-sm8450-pcie0" for PCIe0 on sm8450 + - "qcom,pcie-sm8450-pcie1" for PCIe1 on sm8450 - "qcom,pcie-ipq6018" for ipq6018 - reg: @@ -169,6 +171,24 @@ - "ddrss_sf_tbu" PCIe SF TBU clock - "pipe" PIPE clock +- clock-names: + Usage: required for sm8450-pcie0 and sm8450-pcie1 + Value type: + Definition: Should contain the following entries + - "aux" Auxiliary clock + - "cfg" Configuration clock + - "bus_master" Master AXI clock + - "bus_slave" Slave AXI clock + - "slave_q2a" Slave Q2A clock + - "tbu" PCIe TBU clock + - "ddrss_sf_tbu" PCIe SF TBU clock + - "pipe" PIPE clock + - "pipe_mux" PIPE MUX + - "phy_pipe" PIPE output clock + - "ref" REFERENCE clock + - "aggre0" Aggre NoC PCIe0 AXI clock, only for sm8450-pcie0 + - "aggre1" Aggre NoC PCIe1 AXI clock + - resets: Usage: required Value type: @@ -246,7 +266,7 @@ - "ahb" AHB reset - reset-names: - Usage: required for sc8180x, sdm845 and sm8250 + Usage: required for sc8180x, sdm845, sm8250 and sm8450 Value type: Definition: Should contain the following entries - "pci" PCIe core reset From patchwork Sat Dec 18 14:10:21 2021 Content-Type: text/plain; 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Sat, 18 Dec 2021 06:10:31 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Vinod Koul , Kishon Vijay Abraham I , Stanimir Varbanov , Lorenzo Pieralisi Cc: Bjorn Helgaas , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v5 2/5] PCI: qcom: Remove redundancy between qcom_pcie and qcom_pcie_cfg Date: Sat, 18 Dec 2021 17:10:21 +0300 Message-Id: <20211218141024.500952-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211218141024.500952-1-dmitry.baryshkov@linaro.org> References: <20211218141024.500952-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org In preparation to adding more flags to configuration data, use pointer to struct qcom_pcie_cfg directly inside struct qcom_pcie, rather than duplicating all its fields. This would save us from the boilerplate code that just copies flag values from one struct to another one. Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson --- drivers/pci/controller/dwc/pcie-qcom.c | 31 +++++++++++--------------- 1 file changed, 13 insertions(+), 18 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 4e668da96ef4..1204011c96ee 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -200,8 +200,7 @@ struct qcom_pcie { union qcom_pcie_resources res; struct phy *phy; struct gpio_desc *reset; - const struct qcom_pcie_ops *ops; - unsigned int pipe_clk_need_muxing:1; + const struct qcom_pcie_cfg *cfg; }; #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) @@ -225,8 +224,8 @@ static int qcom_pcie_start_link(struct dw_pcie *pci) struct qcom_pcie *pcie = to_qcom_pcie(pci); /* Enable Link Training state machine */ - if (pcie->ops->ltssm_enable) - pcie->ops->ltssm_enable(pcie); + if (pcie->cfg->ops->ltssm_enable) + pcie->cfg->ops->ltssm_enable(pcie); return 0; } @@ -1145,7 +1144,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) if (ret < 0) return ret; - if (pcie->pipe_clk_need_muxing) { + if (pcie->cfg->pipe_clk_need_muxing) { res->pipe_clk_src = devm_clk_get(dev, "pipe_mux"); if (IS_ERR(res->pipe_clk_src)) return PTR_ERR(res->pipe_clk_src); @@ -1180,7 +1179,7 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) } /* Set pipe clock as clock source for pcie_pipe_clk_src */ - if (pcie->pipe_clk_need_muxing) + if (pcie->cfg->pipe_clk_need_muxing) clk_set_parent(res->pipe_clk_src, res->phy_pipe_clk); ret = clk_bulk_prepare_enable(res->num_clks, res->clks); @@ -1243,7 +1242,7 @@ static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) clk_bulk_disable_unprepare(res->num_clks, res->clks); /* Set TCXO as clock source for pcie_pipe_clk_src */ - if (pcie->pipe_clk_need_muxing) + if (pcie->cfg->pipe_clk_need_muxing) clk_set_parent(res->pipe_clk_src, res->ref_clk_src); regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); @@ -1336,7 +1335,7 @@ static int qcom_pcie_host_init(struct pcie_port *pp) qcom_ep_reset_assert(pcie); - ret = pcie->ops->init(pcie); + ret = pcie->cfg->ops->init(pcie); if (ret) return ret; @@ -1346,8 +1345,8 @@ static int qcom_pcie_host_init(struct pcie_port *pp) qcom_ep_reset_deassert(pcie); - if (pcie->ops->config_sid) { - ret = pcie->ops->config_sid(pcie); + if (pcie->cfg->ops->config_sid) { + ret = pcie->cfg->ops->config_sid(pcie); if (ret) goto err; } @@ -1358,7 +1357,7 @@ static int qcom_pcie_host_init(struct pcie_port *pp) qcom_ep_reset_assert(pcie); phy_power_off(pcie->phy); err_deinit: - pcie->ops->deinit(pcie); + pcie->cfg->ops->deinit(pcie); return ret; } @@ -1468,7 +1467,6 @@ static int qcom_pcie_probe(struct platform_device *pdev) struct pcie_port *pp; struct dw_pcie *pci; struct qcom_pcie *pcie; - const struct qcom_pcie_cfg *pcie_cfg; int ret; pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); @@ -1485,15 +1483,12 @@ static int qcom_pcie_probe(struct platform_device *pdev) pcie->pci = pci; - pcie_cfg = of_device_get_match_data(dev); - if (!pcie_cfg || !pcie_cfg->ops) { + pcie->cfg = of_device_get_match_data(dev); + if (!pcie->cfg || !pcie->cfg->ops) { dev_err(dev, "Invalid platform data\n"); return -EINVAL; } - pcie->ops = pcie_cfg->ops; - pcie->pipe_clk_need_muxing = pcie_cfg->pipe_clk_need_muxing; - pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH); if (IS_ERR(pcie->reset)) return PTR_ERR(pcie->reset); @@ -1510,7 +1505,7 @@ static int qcom_pcie_probe(struct platform_device *pdev) if (IS_ERR(pcie->phy)) return PTR_ERR(pcie->phy); - ret = pcie->ops->get_resources(pcie); + ret = pcie->cfg->ops->get_resources(pcie); if (ret) return ret; From patchwork Sat Dec 18 14:10:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 1570504 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=NbDUiOJD; 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Sat, 18 Dec 2021 06:10:34 -0800 (PST) Received: from eriador.lan ([2001:470:dd84:abc0::8a5]) by smtp.gmail.com with ESMTPSA id c2sm145789lfh.189.2021.12.18.06.10.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Dec 2021 06:10:33 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Vinod Koul , Kishon Vijay Abraham I , Stanimir Varbanov , Lorenzo Pieralisi Cc: Bjorn Helgaas , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v5 3/5] PCI: qcom: Add ddrss_sf_tbu flag Date: Sat, 18 Dec 2021 17:10:22 +0300 Message-Id: <20211218141024.500952-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211218141024.500952-1-dmitry.baryshkov@linaro.org> References: <20211218141024.500952-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Qualcomm PCIe driver uses compatible string to check if the ddrss_sf_tbu clock should be used. Since sc7280 support has added flags, switch to the new mechanism to check if this clock should be used. Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson --- drivers/pci/controller/dwc/pcie-qcom.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 1204011c96ee..d8d400423a0a 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -191,6 +191,7 @@ struct qcom_pcie_ops { struct qcom_pcie_cfg { const struct qcom_pcie_ops *ops; unsigned int pipe_clk_need_muxing:1; + unsigned int has_ddrss_sf_tbu_clk:1; }; struct qcom_pcie { @@ -1133,7 +1134,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) res->clks[3].id = "bus_slave"; res->clks[4].id = "slave_q2a"; res->clks[5].id = "tbu"; - if (of_device_is_compatible(dev->of_node, "qcom,pcie-sm8250")) { + if (pcie->cfg->has_ddrss_sf_tbu_clk) { res->clks[6].id = "ddrss_sf_tbu"; res->num_clks = 7; } else { @@ -1449,6 +1450,7 @@ static const struct qcom_pcie_cfg sdm845_cfg = { static const struct qcom_pcie_cfg sm8250_cfg = { .ops = &ops_1_9_0, + .has_ddrss_sf_tbu_clk = true, }; static const struct qcom_pcie_cfg sc7280_cfg = { From patchwork Sat Dec 18 14:10:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 1570505 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=U/R7IWDR; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4JGSS00jGKz9sRR for ; Sun, 19 Dec 2021 01:10:40 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233366AbhLROKi (ORCPT ); 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Sat, 18 Dec 2021 06:10:35 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Vinod Koul , Kishon Vijay Abraham I , Stanimir Varbanov , Lorenzo Pieralisi Cc: Bjorn Helgaas , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v5 4/5] PCI: qcom: Add interconnect support to 2.7.0/1.9.0 ops Date: Sat, 18 Dec 2021 17:10:23 +0300 Message-Id: <20211218141024.500952-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211218141024.500952-1-dmitry.baryshkov@linaro.org> References: <20211218141024.500952-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add optional interconnect support for the 2.7.0/1.9.0 hosts. Set the bandwidth according to the values from the downstream driver. Signed-off-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pcie-qcom.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index d8d400423a0a..55ac3caa6d7d 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -167,6 +168,7 @@ struct qcom_pcie_resources_2_7_0 { struct clk *pipe_clk_src; struct clk *phy_pipe_clk; struct clk *ref_clk_src; + struct icc_path *path; }; union qcom_pcie_resources { @@ -1121,6 +1123,10 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) if (IS_ERR(res->pci_reset)) return PTR_ERR(res->pci_reset); + res->path = devm_of_icc_get(dev, "pci"); + if (IS_ERR(res->path)) + return PTR_ERR(res->path); + res->supplies[0].supply = "vdda"; res->supplies[1].supply = "vddpe-3v3"; ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies), @@ -1183,6 +1189,9 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) if (pcie->cfg->pipe_clk_need_muxing) clk_set_parent(res->pipe_clk_src, res->phy_pipe_clk); + if (res->path) + icc_set_bw(res->path, 500, 800); + ret = clk_bulk_prepare_enable(res->num_clks, res->clks); if (ret < 0) goto err_disable_regulators; @@ -1241,6 +1250,8 @@ static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; clk_bulk_disable_unprepare(res->num_clks, res->clks); + if (res->path) + icc_set_bw(res->path, 0, 0); /* Set TCXO as clock source for pcie_pipe_clk_src */ if (pcie->cfg->pipe_clk_need_muxing) From patchwork Sat Dec 18 14:10:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 1570506 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=iOFMgvFm; dkim-atps=neutral Authentication-Results: ozlabs.org; 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Sat, 18 Dec 2021 06:10:37 -0800 (PST) Received: from eriador.lan ([2001:470:dd84:abc0::8a5]) by smtp.gmail.com with ESMTPSA id c2sm145789lfh.189.2021.12.18.06.10.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Dec 2021 06:10:37 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Vinod Koul , Kishon Vijay Abraham I , Stanimir Varbanov , Lorenzo Pieralisi Cc: Bjorn Helgaas , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v5 5/5] PCI: qcom: Add SM8450 PCIe support Date: Sat, 18 Dec 2021 17:10:24 +0300 Message-Id: <20211218141024.500952-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20211218141024.500952-1-dmitry.baryshkov@linaro.org> References: <20211218141024.500952-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On SM8450 platform PCIe hosts do not use all the clocks (and add several additional clocks), so expand the driver to handle these requirements. PCIe0 and PCIe1 hosts use different sets of clocks, so separate entries are required. Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson --- drivers/pci/controller/dwc/pcie-qcom.c | 57 ++++++++++++++++++++------ 1 file changed, 44 insertions(+), 13 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 55ac3caa6d7d..fe6ed1e0415a 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -161,7 +161,7 @@ struct qcom_pcie_resources_2_3_3 { /* 6 clocks typically, 7 for sm8250 */ struct qcom_pcie_resources_2_7_0 { - struct clk_bulk_data clks[7]; + struct clk_bulk_data clks[9]; int num_clks; struct regulator_bulk_data supplies[2]; struct reset_control *pci_reset; @@ -193,7 +193,10 @@ struct qcom_pcie_ops { struct qcom_pcie_cfg { const struct qcom_pcie_ops *ops; unsigned int pipe_clk_need_muxing:1; + unsigned int has_tbu_clk:1; unsigned int has_ddrss_sf_tbu_clk:1; + unsigned int has_aggre0_clk:1; + unsigned int has_aggre1_clk:1; }; struct qcom_pcie { @@ -1117,6 +1120,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; struct dw_pcie *pci = pcie->pci; struct device *dev = pci->dev; + unsigned int idx; int ret; res->pci_reset = devm_reset_control_get_exclusive(dev, "pci"); @@ -1134,18 +1138,22 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) if (ret) return ret; - res->clks[0].id = "aux"; - res->clks[1].id = "cfg"; - res->clks[2].id = "bus_master"; - res->clks[3].id = "bus_slave"; - res->clks[4].id = "slave_q2a"; - res->clks[5].id = "tbu"; - if (pcie->cfg->has_ddrss_sf_tbu_clk) { - res->clks[6].id = "ddrss_sf_tbu"; - res->num_clks = 7; - } else { - res->num_clks = 6; - } + idx = 0; + res->clks[idx++].id = "aux"; + res->clks[idx++].id = "cfg"; + res->clks[idx++].id = "bus_master"; + res->clks[idx++].id = "bus_slave"; + res->clks[idx++].id = "slave_q2a"; + if (pcie->cfg->has_tbu_clk) + res->clks[idx++].id = "tbu"; + if (pcie->cfg->has_ddrss_sf_tbu_clk) + res->clks[idx++].id = "ddrss_sf_tbu"; + if (pcie->cfg->has_aggre0_clk) + res->clks[idx++].id = "aggre0"; + if (pcie->cfg->has_aggre1_clk) + res->clks[idx++].id = "aggre1"; + + res->num_clks = idx; ret = devm_clk_bulk_get(dev, res->num_clks, res->clks); if (ret < 0) @@ -1210,6 +1218,9 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) goto err_disable_clocks; } + /* Wait for reset to complete, required on SM8450 */ + usleep_range(1000, 1500); + /* configure PCIe to RC mode */ writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE); @@ -1457,15 +1468,33 @@ static const struct qcom_pcie_cfg ipq4019_cfg = { static const struct qcom_pcie_cfg sdm845_cfg = { .ops = &ops_2_7_0, + .has_tbu_clk = true, }; static const struct qcom_pcie_cfg sm8250_cfg = { + .ops = &ops_1_9_0, + .has_tbu_clk = true, + .has_ddrss_sf_tbu_clk = true, +}; + +static const struct qcom_pcie_cfg sm8450_pcie0_cfg = { .ops = &ops_1_9_0, .has_ddrss_sf_tbu_clk = true, + .pipe_clk_need_muxing = true, + .has_aggre0_clk = true, + .has_aggre1_clk = true, +}; + +static const struct qcom_pcie_cfg sm8450_pcie1_cfg = { + .ops = &ops_1_9_0, + .has_ddrss_sf_tbu_clk = true, + .pipe_clk_need_muxing = true, + .has_aggre1_clk = true, }; static const struct qcom_pcie_cfg sc7280_cfg = { .ops = &ops_1_9_0, + .has_tbu_clk = true, .pipe_clk_need_muxing = true, }; @@ -1564,6 +1593,8 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg }, { .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg }, { .compatible = "qcom,pcie-sc8180x", .data = &sm8250_cfg }, + { .compatible = "qcom,pcie-sm8450-pcie0", .data = &sm8450_pcie0_cfg }, + { .compatible = "qcom,pcie-sm8450-pcie1", .data = &sm8450_pcie1_cfg }, { .compatible = "qcom,pcie-sc7280", .data = &sc7280_cfg }, { } };