From patchwork Tue Dec 14 18:26:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 1567827 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=dYMZ6+Bt; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4JD6Kj5nHMz9s3q for ; Wed, 15 Dec 2021 05:27:05 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234283AbhLNS1C (ORCPT ); Tue, 14 Dec 2021 13:27:02 -0500 Received: from dfw.source.kernel.org ([139.178.84.217]:45120 "EHLO dfw.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234274AbhLNS1B (ORCPT ); Tue, 14 Dec 2021 13:27:01 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 3DE8A616A0; Tue, 14 Dec 2021 18:27:01 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 95BA2C34607; Tue, 14 Dec 2021 18:27:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1639506420; bh=aJHCgMacXpRVWXn7mJ31w116FEaIhCRiKhktss7HZbc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dYMZ6+Bt/zCVqdRA+Rh0iZsLtwNlVo+eKollD1MKnL0fiBjDfiwuXqaz42qGsp3Sy l1QOpa2NrPI9WOsDNoQdd/NOTcFH+m80hKBUzeusFzDKyj7IgDP2gZ6mUnMU/4UIHK wceTSjdjS4xTmVT5XkshAvSWtPZOA+HhTe8+eNnQl9GVCjVh9ZtwOr5mJ2DwiE3NdU HmIxMJU+Rhls+92yo1NS0IUBbzvWCrgwAOMT+GY7wyt/zkbaxI6Ee4TTQMAnjv/dcB iDwCssNDYidOTEpYjxpUGPqcewHo/soG+SxQUHWEaMESzinclrISshFesPVMTOKRod w64T7dNcygNrQ== Received: from cfbb000407.r.cam.camfibre.uk ([185.219.108.64] helo=why.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mxCVu-00C7Tq-Hc; Tue, 14 Dec 2021 18:26:58 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Rutland , Will Deacon , Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Thomas Gleixner , Dougall , kernel-team@android.com, Rob Herring Subject: [PATCH v3 01/10] dt-bindings: arm-pmu: Document Apple PMU compatible strings Date: Tue, 14 Dec 2021 18:26:25 +0000 Message-Id: <20211214182634.727330-2-maz@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211214182634.727330-1-maz@kernel.org> References: <20211214182634.727330-1-maz@kernel.org> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, will@kernel.org, marcan@marcan.st, sven@svenpeter.dev, alyssa@rosenzweig.io, robh+dt@kernel.org, tglx@linutronix.de, dougallj@gmail.com, kernel-team@android.com, robh@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org As we are about to add support fur the Apple PMUs, document the compatible strings associated with the two micro-architectures present in the Apple M1. Acked-by: Rob Herring Reviewed-by: Hector Martin Signed-off-by: Marc Zyngier --- Documentation/devicetree/bindings/arm/pmu.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation/devicetree/bindings/arm/pmu.yaml index e17ac049e890..1a6986b4e552 100644 --- a/Documentation/devicetree/bindings/arm/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/pmu.yaml @@ -20,6 +20,8 @@ properties: items: - enum: - apm,potenza-pmu + - apple,firestorm-pmu + - apple,icestorm-pmu - arm,armv8-pmuv3 # Only for s/w models - arm,arm1136-pmu - arm,arm1176-pmu From patchwork Tue Dec 14 18:26:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 1567828 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=DZs2p2u+; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4JD6Kk3ccVz9sRK for ; Wed, 15 Dec 2021 05:27:06 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236964AbhLNS1C (ORCPT ); Tue, 14 Dec 2021 13:27:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60940 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231875AbhLNS1B (ORCPT ); Tue, 14 Dec 2021 13:27:01 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 93D7AC061574; Tue, 14 Dec 2021 10:27:01 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 386E1616A1; Tue, 14 Dec 2021 18:27:01 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 912AFC34604; Tue, 14 Dec 2021 18:27:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1639506420; bh=JUqDleAAmmdXoCD3MpSn26A3e+dzkil8Xshl3lWRacM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DZs2p2u+doCFSWlU6AUx7+7jXEqhFiHKqNGF9eKt66KATiNhGu/BnoiweV9mFUPpL ZQjH+BBki2tvbrlHb1wJ3Cl8dOeQh+0sycpoQzBL+yig/6QrD5Q5H0kYagOzVrEjS3 xACB8XLbRe9nG5A7hNBYpDoR0VDDQwxzWPn30/bQk8obwGqDRPRKb1JtCVjT3YNsag GiHzwOPStAo4kw7HDvpGvKpAdIPZn7OS7xxnF0Gf83IrFu3qGQWXnxtnx4EJGh9oRz RFmoMfu/sHh0EQXWvZ5qb5yxqZstkhiEa1dMmzakHVTO36TpZbTVFcQ60IKftt43F4 bD5GKamDzuhEw== Received: from cfbb000407.r.cam.camfibre.uk ([185.219.108.64] helo=why.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mxCVu-00C7Tq-PM; Tue, 14 Dec 2021 18:26:58 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Rutland , Will Deacon , Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Thomas Gleixner , Dougall , kernel-team@android.com, Rob Herring Subject: [PATCH v3 02/10] dt-bindings: apple,aic: Add CPU PMU per-cpu pseudo-interrupts Date: Tue, 14 Dec 2021 18:26:26 +0000 Message-Id: <20211214182634.727330-3-maz@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211214182634.727330-1-maz@kernel.org> References: <20211214182634.727330-1-maz@kernel.org> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, will@kernel.org, marcan@marcan.st, sven@svenpeter.dev, alyssa@rosenzweig.io, robh+dt@kernel.org, tglx@linutronix.de, dougallj@gmail.com, kernel-team@android.com, robh@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Advertise the two pseudo-interrupts that tied to the two PMU flavours present in the Apple M1 SoC. We choose the expose two different pseudo-interrupts to the OS as the e-core PMU is obviously different from the p-core one, effectively presenting two different devices. Acked-by: Rob Herring Reviewed-by: Hector Martin Signed-off-by: Marc Zyngier --- .../devicetree/bindings/interrupt-controller/apple,aic.yaml | 2 ++ include/dt-bindings/interrupt-controller/apple-aic.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml index cf6c091a07b1..b95e41816953 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml @@ -56,6 +56,8 @@ properties: - 1: virtual HV timer - 2: physical guest timer - 3: virtual guest timer + - 4: 'efficient' CPU PMU + - 5: 'performance' CPU PMU The 3rd cell contains the interrupt flags. This is normally IRQ_TYPE_LEVEL_HIGH (4). diff --git a/include/dt-bindings/interrupt-controller/apple-aic.h b/include/dt-bindings/interrupt-controller/apple-aic.h index 604f2bb30ac0..bf3aac0e5491 100644 --- a/include/dt-bindings/interrupt-controller/apple-aic.h +++ b/include/dt-bindings/interrupt-controller/apple-aic.h @@ -11,5 +11,7 @@ #define AIC_TMR_HV_VIRT 1 #define AIC_TMR_GUEST_PHYS 2 #define AIC_TMR_GUEST_VIRT 3 +#define AIC_CPU_PMU_E 4 +#define AIC_CPU_PMU_P 5 #endif From patchwork Tue Dec 14 18:26:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 1567830 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=os5pRyO0; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4JD6Kr6qdHz9s3q for ; Wed, 15 Dec 2021 05:27:12 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237024AbhLNS1L (ORCPT ); Tue, 14 Dec 2021 13:27:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60952 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236988AbhLNS1D (ORCPT ); Tue, 14 Dec 2021 13:27:03 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 75BD6C06173E; Tue, 14 Dec 2021 10:27:03 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 34B6CB81C53; Tue, 14 Dec 2021 18:27:02 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C8F1CC34610; Tue, 14 Dec 2021 18:27:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1639506420; bh=eE+a2Gf7Eb4EYOYDngrt1iDAhmc9juBU3zk7/0ma9Sc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=os5pRyO0rdjqOLkQJWCJ7sJu0uYgcvsGd9/1RFSDShk1VWOiR/x9LfZF2/NIAMYGA VVlQe0dxP4u0OkBsPgCzfUOWMeor1rZ7jzoJpgOeDSr+YnmXOLikHVjcblk8HWsX6b 06DWpUaH52pgfWcR90HGDro7uz8iKio+3noA8qdW3eG/o6BUe/l+JNW+aLrvReKzuk rh06pF8C8Vziuhw8dudc04/vxpqvOZDZIR8cgYZFpkDJHG56SYi60xPj1tq5qAAsNK TYsgCsPbYd7zWsyKbfasVO7T44Yj5sNLlU4y4D2Z4ADXrsEDw8Zj+kvRsT0/p1Rpns pVUJcm+b8jS6A== Received: from cfbb000407.r.cam.camfibre.uk ([185.219.108.64] helo=why.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mxCVv-00C7Tq-0M; Tue, 14 Dec 2021 18:26:59 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Rutland , Will Deacon , Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Thomas Gleixner , Dougall , kernel-team@android.com Subject: [PATCH v3 03/10] dt-bindings: apple,aic: Add affinity description for per-cpu pseudo-interrupts Date: Tue, 14 Dec 2021 18:26:27 +0000 Message-Id: <20211214182634.727330-4-maz@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211214182634.727330-1-maz@kernel.org> References: <20211214182634.727330-1-maz@kernel.org> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, will@kernel.org, marcan@marcan.st, sven@svenpeter.dev, alyssa@rosenzweig.io, robh+dt@kernel.org, tglx@linutronix.de, dougallj@gmail.com, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Some of the FIQ per-cpu pseudo-interrupts are better described with a specific affinity, the most obvious candidate being the CPU PMUs. Augment the AIC binding to be able to specify that affinity in the interrupt controller node. Signed-off-by: Marc Zyngier --- .../interrupt-controller/apple,aic.yaml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml index b95e41816953..ac1c82cffa0a 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml @@ -67,6 +67,32 @@ properties: Specifies base physical address and size of the AIC registers. maxItems: 1 + affinities: + type: object + description: + FIQ affinity can be expressed as a single "affinities" node, + containing a set of sub-nodes, one per FIQ with a non-default + affinity. + patternProperties: + "^.+-affinity$": + type: object + properties: + fiq-index: + description: + The interrupt number specified as a FIQ, and for which + the affinity is not the default. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 5 + affinity: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Should be a list of phandles to CPU nodes (as described in + Documentation/devicetree/bindings/arm/cpus.yaml). + + required: + - fiq-index + - affinity + required: - compatible - '#interrupt-cells'