From patchwork Tue Dec 7 21:08:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 1564911 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.a=rsa-sha256 header.s=badeba3b8450 header.b=JMxB8wxG; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2404:9400:2:0:216:3eff:fee1:b9f1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4J7tGr648kz9sRK for ; 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Wed, 8 Dec 2021 08:08:59 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1638911326; bh=ucTTqYfqrAIEEQUOAqIQuTU4lLZGs0Rtoae2Ggs56Lk=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=JMxB8wxG8C8TyjLgWq12CJQRzhzbOn2CbRMLngVQ5T8LFHWpTO+dYH6M30ZHNejGj mXmUQTZLQd12/0pIJEiQtAk94jqUVZAdmUadPmMp7sM0ZQlXyswZVDmdI4baHwuvsP KFMe/32VdpZ4b7JrIT7xDQr/J9Db3OmzT9dQYrsY= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([5.146.194.160]) by mail.gmx.net (mrgmx105 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MQMuX-1nGNHb1yxV-00MIU3; Tue, 07 Dec 2021 22:08:46 +0100 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 1/8] dt-bindings: arm/npcm: Add binding for global control registers (GCR) Date: Tue, 7 Dec 2021 22:08:16 +0100 Message-Id: <20211207210823.1975632-2-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211207210823.1975632-1-j.neuschaefer@gmx.net> References: <20211207210823.1975632-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:5z6fEwkITtvUUGanwwbUAU9wniS3Wxx/3lxzUrIulEn2I63yJtD 2ZJaoUkFgy/5lelXXUnnsIeIHi4tAIEojSrz6nzdNhILkTKHXJu6zGm31w/lk2gfZfIlHhj e2brlbpU+yQqnd6seeDz8jx/m5Lz8NcDzo5HEayRqFXGGof3x+eAq1CdqtzNKsdBetFbDRN 87M0qpknnQsCbuVPCN2mA== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1;V03:K0:BdxySlRDLD8=:YMshSa6kD+dYBdTNnTBAsk UeMhi1NiJHp6Yf88bupwAc+LxGKIiR8SoJeN2oFWYnisPRBrOyUzb+GpnZaJWsmhMZc4rSrdw nPkL1FL7e7Bn+1AAOtFlHkH6cFq5W1ZXPbiI3sSSBkuiBlGteJOR1QcU7AJb19XgPyRakjaS1 z+K0Uovf7uoH2iH2VBkg2BAGx4q1l1U+uw6/HhpzYJhxIRhtdbnKWhMaW85yR14ZHMwRKpHlI WFriqjcrbVoECGnCyNko/A2eeNczLraAEq8WMIJc0uF13Bl+/H5TKMnJHvlSsxXzwLj6tpDZP sXcf9OfOV+0uutcyyPkp4lGGys7AJtlevK+UtXESDebc2tXH0LQ73DkaUb3nnP9juzBPzC1DV bn2KUyFdrSFPTptnZg/o72xUlmlCymSt+6XJYTKXvhDlj+sVpOrubweaToQRYC1fcY0Yld2Xu qj2wm/E1gGo7Qo07UimbL4tc7DFwLk7oRYQjugdLzRoj+DY6a4QXwGxK8J/TlfmuXlc53kDFW ltOpJez/x12B/0/nuU1qwEA5innGtu9XS/TyweFA1lCpiEIJdetkm7O5GDN00QXQDIrEXE3IZ CLPzrYArvaKTLt2TVU+eVQm5Fd/1HyoTF2WMtlMvThxn70ur1+BapfrDgWCF0KPrs/Dl7HMu4 8gcZcyuVvoRR9W6W1Wgx+HiLus/S3y1OyHrbBalrosvchez6fq4Kjk2YhrgUs0nVpNbK2RxxY ZBT6W7yzQc37NFVkTM9M56GNqMn6c4O2DcmcX/WxtlntLUkAQHuAD0Wg4rJSOGR3n/DjefVEY j65Wp6/sA81mRBsuUzBzIQpGcH4izDHl4paY3NzzDHaUYug/cXEKyrwqoVlGpTTEXeE7ySHyd UvFHhoojM3QODJHL8XwAXnRcTPk4/Z7wgbJHy0mV6Y6+5U6MSjt96i5fMJMyNvF768/5ZEplc 47Tsu8OoYr8/w+FE2FMStNOJvbgm3LMTzc1wdOUVsVAG2QgrsbJFNMHSlVFW1sz7QhATlPurb 6O/9FPAAS7RKtR49U1oPeFq3FAt7k+qWaGbqRkCHcHJqwojWlXJZKaNgO+1P4SknsmqcJn1TJ h96n/2qkTawnWI= X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tomer Maimon , Avi Fishman , Patrick Venture , Linus Walleij , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Rob Herring , Tali Perry , openbmc@lists.ozlabs.org, Benjamin Fair Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" A nuvoton,*-gcr node is present in nuvoton-common-npcm7xx.dtsi and will be added to nuvoton-wpcm450.dtsi. It is necessary for the NPCM7xx and WPCM450 pinctrl drivers, and may later be used to retrieve SoC model and version information. This patch adds a binding to describe this node. Signed-off-by: Jonathan Neuschäfer --- v2: - Rename node in example to syscon@800000 - Add subnode to example v1: - https://lore.kernel.org/lkml/20210602120329.2444672-2-j.neuschaefer@gmx.net/ --- .../bindings/arm/npcm/nuvoton,gcr.yaml | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml -- 2.30.2 diff --git a/Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml b/Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml new file mode 100644 index 0000000000000..62020d7ac305b --- /dev/null +++ b/Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/npcm/nuvoton,gcr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Global Control Registers block in Nuvoton SoCs + +maintainers: + - Jonathan Neuschäfer + +description: | + The Global Control Registers (GCR) are a block of registers in Nuvoton SoCs + that expose misc functionality such as chip model and version information or + pinmux settings. + +properties: + compatible: + items: + - enum: + - nuvoton,wpcm450-gcr + - nuvoton,npcm750-gcr + - const: syscon + - const: simple-mfd + reg: true + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + gcr: syscon@800000 { + compatible = "nuvoton,npcm750-gcr", "syscon", "simple-mfd"; + reg = <0x800000 0x1000>; + + uart-mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x38 0x07>; + idle-states = <2>; + }; + }; From patchwork Tue Dec 7 21:08:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 1564915 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.a=rsa-sha256 header.s=badeba3b8450 header.b=jdNIaXUD; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2404:9400:2:0:216:3eff:fee1:b9f1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4J7tJF15QWz9sRK for ; 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Wed, 8 Dec 2021 08:09:00 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1638911329; bh=KuuD6eeMVERCTcB38ObnXFq9aI+j62KUONB7+XNWmJ8=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=jdNIaXUDI61KFrl2Uu0kT7UxcRjjqO8DfRWt4ncRFTfj2rMk5/OK1R5mRekNs9mys ETarCqHd5oWGS51PRb1C6o+D+mOfRNnsdDlWGiVLo7CPTuoxqrgLK+brZFyMcCOpXZ l7Z51DWkqwYMuFhyzHY+Y34HyoUn5Cuj4a1hI2RM= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([5.146.194.160]) by mail.gmx.net (mrgmx005 [212.227.17.190]) with ESMTPSA (Nemesis) id 1ML9yS-1nBgah0rA2-00IAob; Tue, 07 Dec 2021 22:08:49 +0100 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 2/8] MAINTAINERS: Match all of bindings/arm/npcm/ as part of NPCM architecture Date: Tue, 7 Dec 2021 22:08:17 +0100 Message-Id: <20211207210823.1975632-3-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211207210823.1975632-1-j.neuschaefer@gmx.net> References: <20211207210823.1975632-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:EtnkHO3/DgWnnNDn9NeWYv3hTDh3PjMdqIiWBau9Fa2MKUIVYWZ /2Fy9Yc2jXJUIRJJ8bcHEsfFzYKpeRiWr5n6J7yHi42PF4FvPETUwac8BO4qCwodPdbRUHR TxWTZEiLhqtALU3mEY7zTrqkrQww2my+8LWAJCfBX+v6lLhwNGbCgP9lS0eLvybCmBi4VIr u/2epOCUVYoRviwPqamEQ== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1;V03:K0:Y0aYPSWaj9w=:yLYx2bO7tUZnINS6uBXipG V9ChDAAOGIKJ+vfw1AUIE4PWsSO6KTVjHBvaL+tlX1GL3x35v/9qdRZa6qAmw+41Hoa32evCV JCoDkLljd7B3LfyWG6/KgscRuhHBV7Ufhx3Ij7XuqYJyDhCHp8arn/Qxib/y9P1QvzQ9yHNbG I4HAKOMBr+rbQRLhW3UhJJaOKjZV36uRcrscwZyXwGYCZKmARERByxRDKi1NQCdbaO+bDMdy5 yMVf4URgR1CHDKgakMxtKOewsqquqblh0D+LeCK1SyscBCFKVwu41sK+aywP985HCumBIcCdE lDOQum+pAuLY0W63ashC297z9tsQ5zP4vzB48HqVkgzXOm3I21dx+LvYV7NoSEITLy7xLIryc RKP88CGA/EsKOhqupNVy8Vk3zlocTaMxpx32zeO+4awmhE+ja4F34scimakXlwyKnQR0TQofD +xVyxdVXcNZVyTYGKDK2Kq2ZutSpuqD1QcA5Kj5XNUetUatPIIu/sjsxUDrjwmsR6OUaSmNAT yh6D/EZk38frUmwuy8wPWqUmMOyCa8hb2ZYUrPCuUIOIn7XVEdzhhJGL8MmTklB8fryOhhqLF 02JhHJehkr/baQLLDKjf2vEJzF0/0Zw1lfw1ap/5IyWJ7UGUbEr8IDQcaUU7nsnRlmdEhhFT+ INC+k0XxINHGjbzZuCnJZMKVmDKdgQOAs3MNIfNETnOFSt5c6dvkuBGzyLBb5K19NZt9BXq38 /B/TBFWze5at2ad2CY5moFhkrX+YFJ+psMc2jQ9TYLqVWaCIpjLIJ1I8saDjgwNYlZKpX3k7t 8vyzFFTbAe1ytlhNBamj8AUc3xs1GHpUgYI9cC/GFQGrOpbE8wGi4ti081VNlE9jyLVBybnup iG7pYpqYIPPAXTfi9pNOzbQrFo+HVx1NPKCLMi3Lozwi/4ObbbhtHD51ny2xzIHN9VWaRwWAS pzxKRdSU9V2ZZIKe55x1IZuD5AMH5qvWs4sKgUtRROTU+N9ztbWxxnZQkjMk1bD8MA84ZNwzn 4ygjsDe+N189FXivGvn8NECpK/9YJxFOY8POdetZYqQIM/Afio2ubOsGYRh7haOj5MUOAB9VB Ifo6WQdwupJFz0= X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tomer Maimon , Linus Walleij , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Rob Herring , openbmc@lists.ozlabs.org Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" All files in Documentation/devicetree/bindings/arm/npcm/ belong to the Nuvoton NPCM architecture, even when their names might not spell it out explicitly. Signed-off-by: Jonathan Neuschäfer --- v2: - no changes v1: - https://lore.kernel.org/lkml/20210602120329.2444672-3-j.neuschaefer@gmx.net/ --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) -- 2.30.2 diff --git a/MAINTAINERS b/MAINTAINERS index 360e9aa0205d6..eff3edafd8814 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2338,6 +2338,7 @@ L: openbmc@lists.ozlabs.org (moderated for non-subscribers) S: Supported F: Documentation/devicetree/bindings/*/*/*npcm* F: Documentation/devicetree/bindings/*/*npcm* +F: Documentation/devicetree/bindings/arm/npcm/* F: arch/arm/boot/dts/nuvoton-npcm* F: arch/arm/mach-npcm/ F: drivers/*/*npcm* From patchwork Tue Dec 7 21:08:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 1564912 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; 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dkim-atps=neutral X-Original-To: openbmc@lists.ozlabs.org Delivered-To: openbmc@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmx.net (client-ip=212.227.15.19; helo=mout.gmx.net; envelope-from=j.neuschaefer@gmx.net; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.a=rsa-sha256 header.s=badeba3b8450 header.b=V9lovWgd; dkim-atps=neutral Received: from mout.gmx.net (mout.gmx.net [212.227.15.19]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4J7tFm4jrZz2yHj for ; Wed, 8 Dec 2021 08:09:00 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1638911330; bh=1dtTDXD/Lvi01K4UbWYjNJTZ/ggnPgZ9xGaEukkWfB0=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=V9lovWgdCch7Uwa7Yur4HhZe67zRs2d/jd5aGtEF6j/jtMXwdljffV47p8JjEkV1E gMAjPcyoD5aH+dWGHWQElC6w7osrretjuErJt9kUOyK8WZliTi4V6/vRNl3Ig1/PL6 3+vAYz1FiP+EhrHfBhtiZvOKSTGXJsAT7VDyAvZQ= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([5.146.194.160]) by mail.gmx.net (mrgmx004 [212.227.17.190]) with ESMTPSA (Nemesis) id 1MatVh-1mIKwz1GcV-00cU1b; Tue, 07 Dec 2021 22:08:50 +0100 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 3/8] ARM: dts: wpcm450: Add global control registers (GCR) node Date: Tue, 7 Dec 2021 22:08:18 +0100 Message-Id: <20211207210823.1975632-4-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211207210823.1975632-1-j.neuschaefer@gmx.net> References: <20211207210823.1975632-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:/AEDgg1Hsm8PKkviv0rCSL50+S5ZpzOGhxAK9NCh4rQtu+koWJT dBq0cdOjqi5t/zBU3S/lXxYlVtZZigPP+W/xrO1VKumlqEUd313XNSlV5VKYOFtyIdlJjG7 VYjsRt5BWbwFmQV9OLiV5PUAwAeHRdqLCi4MuipcN656Y1kHELEdhd0eKJDQlT0bFWerW1J MJUl6wglsJuzzRaqUtNQQ== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1;V03:K0:Tnd+BuRe4f8=:yASc0zKfgfnnATWaT7symi 6GFAvsbRe7rInR0lrzfOsy/VFremHTp42/lNqzcVgUj6vzIJVA/tSRZmJ2kIboFDtWMeS4vlE JlyGJXaQ1yAZeD6pcH3TR+W+N2lLMMx6fB6ZV13a1BX4DHtdsETLO5dGtGmh6cEYjutoqiyL7 mt++bB9zhctFCJICtXlqy8vTjOvW4pG/FzQmmMl3T0S7mCXFlzZbWFxaEBNItmPUub4JC4CUQ rQ/dKz/p8adTazkUnfAFXuepb40MhKAnTj6rv0iFcjbs4EzHJTDFnm/+/iQjxxwWi1We7JrWR WX3swBB9aMpOaeFHvgn8nwNBtebx1/gilk2GD6Ic8Btxq+4k6QJT7Nm9xpZOAJg47QuR378Gk xsAruGvaXEfnDAKMSjIfde+Ec5A/7RyIVHC4G0OIC6bYkWOvPaKgGH0F+KjQFsU73hr22g0/v fVZXpBol+54u9bF+TjDFFDnCEZfpHXSOUicVoXJMlo9QGv+ngQ8gas8G2qhC/y1FEhkALxXND zP+nM2oc8fbzlIVGdSN33uhvPNuAWJQ9TD7360+3uhr8WVTVPs+vn8RF/LWZ8VAvaWGRL5YiR /8nGpaFE5VnZ/aAMefzVMp40SD+7Q7IPoOZXLg7vD0RiBWByrpVLXBicGBy4pdKXz+IEgmjRG 4Hm1NQfagX1/EUPUKhStq2R0Vw1npOL+YyQpRgC9xQ4gjXEbFgqtvU8UD3ftbBOl/U9/+azUg T9D9lmdezq5G6nu3vyYgvImjx7aaB+FWeIIKrEMB/11hk7lDptYEgulOmfLbKswVQxQMEdO2u 9Bca4JJpvG1J2XlHZFzWmROpg7A1DYidqkwTICwFnWN13MgMAUSFcltshNzzHh/XsjNfmnCcZ yM89qL5n99knO8m2MZI8ghwpmLMc20JwmKfYKGa0WOWADCBurM+Q3VklasLq9EfSUbereT3v8 nAfjwVi4oenRkz+xCB9f030dzZ/FAfOSAQdaP3kbLY7Psis8OSAKLmgrwvYT1RiifDV7EL8uq xRZg6E9D5N+8CWmVf5y/VG6SOpgEdFRdC9bHV+K7TLla+YFZALjeFCSn7hbtTfga94mhSFBwB IyUHRkRzfxK1Pg= X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tomer Maimon , Linus Walleij , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Rob Herring , openbmc@lists.ozlabs.org Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" The Global Control Registers (GCR) are a block of registers in Nuvoton SoCs that expose misc functionality such as chip model and version information or pinmux settings. This patch adds a GCR node to nuvoton-wpcm450.dtsi in preparation for enabling pinctrl on this SoC. Signed-off-by: Jonathan Neuschäfer --- v2: - Rename node to syscon@b0000000 v1: - https://lore.kernel.org/lkml/20210602120329.2444672-4-j.neuschaefer@gmx.net/ --- arch/arm/boot/dts/nuvoton-wpcm450.dtsi | 5 +++++ 1 file changed, 5 insertions(+) -- 2.30.2 diff --git a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi index d7cbeb1874840..a17ee70085dd0 100644 --- a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi +++ b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi @@ -33,6 +33,11 @@ soc { interrupt-parent = <&aic>; ranges; + gcr: syscon@b0000000 { + compatible = "nuvoton,wpcm450-gcr", "syscon", "simple-mfd"; + reg = <0xb0000000 0x200>; + }; + serial0: serial@b8000000 { compatible = "nuvoton,wpcm450-uart"; reg = <0xb8000000 0x20>; From patchwork Tue Dec 7 21:08:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 1564917 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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secure) header.d=gmx.net header.i=@gmx.net header.a=rsa-sha256 header.s=badeba3b8450 header.b=bL+cKa60; dkim-atps=neutral X-Original-To: openbmc@lists.ozlabs.org Delivered-To: openbmc@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmx.net (client-ip=212.227.15.15; helo=mout.gmx.net; envelope-from=j.neuschaefer@gmx.net; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.a=rsa-sha256 header.s=badeba3b8450 header.b=bL+cKa60; dkim-atps=neutral Received: from mout.gmx.net (mout.gmx.net [212.227.15.15]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4J7tG25jLgz3blF for ; Wed, 8 Dec 2021 08:09:14 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1638911332; bh=XAzA8gvNpKYxrPkC0Q1zECWGCmnDKj0uKiKMhz6ztHY=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=bL+cKa60ZM5sm30/i/0jdhGvCYLujzDXWTFZSeEdlAYpjSHcnvHcQOKXJP/z4o+eP 03WE9F6bZJR4wgByFjH+j77YI2Cmz6KrwaUUIhfggGoc3YrF64wA5MWC0LLeqyJ6em W0GOi+75eSYOZU10RM1apgxukgR4DP6ArUxS4fDg= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([5.146.194.160]) by mail.gmx.net (mrgmx004 [212.227.17.190]) with ESMTPSA (Nemesis) id 1N3KPg-1mTaOk0OlW-010J7u; Tue, 07 Dec 2021 22:08:52 +0100 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 4/8] dt-bindings: pinctrl: Add Nuvoton WPCM450 Date: Tue, 7 Dec 2021 22:08:19 +0100 Message-Id: <20211207210823.1975632-5-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211207210823.1975632-1-j.neuschaefer@gmx.net> References: <20211207210823.1975632-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:g1MLPD4Rdetv/nS3WvDAQiqkzqdHcUec68aeb50CZV3RSLW7tw0 UQbvBLDrf9O8Eo0oyQV68Roguo4L5B6kl2D3B3lmkmGEFTQ/txhnsguPrBmdP8dGfryZFBz O8XyZVgBbGGGqth1qDH2psdTIaK3RIUDscTXk414qvaduqpjIcqmaOf2oSjUiy4pMQ39svw LDF+caezVgq7nWShRawwQ== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1;V03:K0:2syvsrT2Qy0=:Ltlj6+/0LlH3WvLBRPEca4 3Gdn9wu0nn3hceYE3KpZrbJDzNaSjeH/lh0jamDw8/0u1XL+vInB98uZY4XhfnrdRja7Ywdj7 NCbUKTjUktboDLq55SMIaG4eAfNVMvJO5Ga7g07sjHlqyDdWQYYOPQ261Q/zoFgNYOszSY3y6 4TBgobR4v4sYk5QyZlW8D4R9c+Bqm/D5Tq6cF3EZ13yoSkZvsAfcvTmf9hc+8GTITzho58QH8 1330Axs868e0FJysfks/2kcXKRBQLCsXqCY8fCvcgEKnyUFM6eaLIC3U+wN47RZjU32WjQbeO 0V9aYPJ4eyiOGJF2YEg0bybbEZrsmIkqPDXXRVYA2+CYEV3iEaxBqKMF/iXHUDZsfLeDMiqpI qD4CMfoww5+ZwNJ5SIwckUiYSvjErK30IwcIQftT5fL61g1/LREMrrejokC0l8Hk9H13+ciUk ajkYwnGjOOzvHKG2Xe0uDw0xffpyPBEnYMNoYl2kj5+PTaNPRaqCICMRngWexMXnDEldODJ87 y1SZtCXpnFIietHmaCf44RJ4zr+FsvjCLfMngSFrE51ps8mJCeIIZ4wJTPyQnMi77Vtk2kBVS vopc2clT9m1uoCBsftUuaALw8xJFCZ+DPSScKSRaz/yMJU09k7pNQ5yPr/TX4ViKTdLQll7P3 3yP3T0y+1fNTsJie3QrmFZtCi99Aw4FEv5c04auiSvdYupfyBy9IFXGkXA/2i8n3RtV3L0T7P HOiour2LrYgbXKbQFxoGJnMckEHz+3mzevdd4h0gnRNNt3EEvivb9YQjkGXJbIlj89CjmtXbG IpXvGGxeZtoNPvgCamXu6vBDc8dzrPhZfDoACDztNv7Mezaxx6ZV5cgygYKdx4xq69K9AD8Jm EGGKFB657+UxUbYy5dIVSI8JfZsSR/1mzbNWlYr9gBS83pA8hqNnY3vo4qpYQFpMW/QFGA3jf wXQq8kw6wOCiga5nBthLQgYSsI7mlSNgy48tb5gowU4QD3Bmq70jrB92u/cy6exTCIRh0oDVR 1tQxqNwPwN18asc8TFD2foC2I+7YPodJCHLCNd0Cox9iyT3oZIYOo++DtRvP8SpqaxQhQz2Y2 NRs6LQsftKgtTk= X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tomer Maimon , Linus Walleij , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Rob Herring , openbmc@lists.ozlabs.org Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" This binding is heavily based on the one for NPCM7xx, because the hardware is similar. There are some notable differences, however: - The addresses of GPIO banks are not physical addresses but simple indices (0 to 7), because the GPIO registers are not laid out in convenient blocks. - Pinmux settings can explicitly specify that the GPIO mode is used. Certain pins support blink patterns in hardware. This is currently not modelled in the DT binding. Signed-off-by: Jonathan Neuschäfer --- v2: - Move GPIO into subnodes - Improve use of quotes - Remove unnecessary minItems/maxItems lines - Remove "phandle: true" - Use separate prefixes for pinmux and pincfg nodes - Add nuvoton,interrupt-map property - Make it possible to set pinmux to GPIO explicitly v1: - https://lore.kernel.org/lkml/20210602120329.2444672-5-j.neuschaefer@gmx.net/ --- .../pinctrl/nuvoton,wpcm450-pinctrl.yaml | 190 ++++++++++++++++++ 1 file changed, 190 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml -- 2.30.2 diff --git a/Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml new file mode 100644 index 0000000000000..2b783597794d7 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml @@ -0,0 +1,190 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nuvoton,wpcm450-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton WPCM450 pin control and GPIO + +maintainers: + - Jonathan Neuschäfer + +properties: + compatible: + const: nuvoton,wpcm450-pinctrl + + reg: + maxItems: 1 + +patternProperties: + # There are three kinds of subnodes: + # 1. a GPIO controller node for each GPIO bank + # 2. a pinmux node configures pin muxing for a group of pins (e.g. rmii2) + # 3. a pinconf node configures properties of a single pin + + "^gpio@.*$": + if: + type: object + then: + description: + Eight GPIO banks (gpio@0 to gpio@7), that each contain between 14 and 18 + GPIOs. Some GPIOs support interrupts. + + allOf: + - $ref: pinmux-node.yaml# + + properties: + reg: + description: GPIO bank number (0-7) + + gpio-controller: true + + "#gpio-cells": + const: 2 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + interrupts: + maxItems: 4 + + nuvoton,interrupt-map: + description: + This property defines which bits in the interrupt registers + correspond to which GPIOs. + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: First interrupt bit + - description: Number of interrupt bits + - description: First GPIO associated with an interrupt + + required: + - reg + - gpio-controller + - '#gpio-cells' + + "^mux_.*$": + if: + type: object + then: + allOf: + - $ref: pinmux-node.yaml# + properties: + groups: + description: + One or more groups of pins to mux to a certain function + items: + enum: [ smb3, smb4, smb5, scs1, scs2, scs3, smb0, smb1, smb2, bsp, + hsp1, hsp2, r1err, r1md, rmii2, r2err, r2md, kbcc, dvo, + clko, smi, uinc, gspi, mben, xcs2, xcs1, sdio, sspi, fi0, + fi1, fi2, fi3, fi4, fi5, fi6, fi7, fi8, fi9, fi10, fi11, + fi12, fi13, fi14, fi15, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, + pwm6, pwm7, hg0, hg1, hg2, hg3, hg4, hg5, hg6, hg7 ] + function: + description: + The function that a group of pins is muxed to + enum: [ smb3, smb4, smb5, scs1, scs2, scs3, smb0, smb1, smb2, bsp, + hsp1, hsp2, r1err, r1md, rmii2, r2err, r2md, kbcc, dvo0, + dvo1, dvo2, dvo3, dvo4, dvo5, dvo6, dvo7, clko, smi, uinc, + gspi, mben, xcs2, xcs1, sdio, sspi, fi0, fi1, fi2, fi3, fi4, + fi5, fi6, fi7, fi8, fi9, fi10, fi11, fi12, fi13, fi14, fi15, + pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, pwm6, pwm7, hg0, hg1, + hg2, hg3, hg4, hg5, hg6, hg7, gpio ] + + dependencies: + groups: [ function ] + function: [ groups ] + + additionalProperties: false + + "^cfg_.*$": + if: + type: object + then: + allOf: + - $ref: pincfg-node.yaml# + properties: + pins: + description: + A list of pins to configure in certain ways, such as enabling + debouncing + items: + enum: [ gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, + gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, gpio14, + gpio15, gpio16, gpio17, gpio18, gpio19, gpio20, gpio21, + gpio22, gpio23, gpio24, gpio25, gpio26, gpio27, gpio28, + gpio29, gpio30, gpio31, gpio32, gpio33, gpio34, gpio35, + gpio36, gpio37, gpio38, gpio39, gpio40, gpio41, gpio42, + gpio43, gpio44, gpio45, gpio46, gpio47, gpio48, gpio49, + gpio50, gpio51, gpio52, gpio53, gpio54, gpio55, gpio56, + gpio57, gpio58, gpio59, gpio60, gpio61, gpio62, gpio63, + gpio64, gpio65, gpio66, gpio67, gpio68, gpio69, gpio70, + gpio71, gpio72, gpio73, gpio74, gpio75, gpio76, gpio77, + gpio78, gpio79, gpio80, gpio81, gpio82, gpio83, gpio84, + gpio85, gpio86, gpio87, gpio88, gpio89, gpio90, gpio91, + gpio92, gpio93, gpio94, gpio95, gpio96, gpio97, gpio98, + gpio99, gpio100, gpio101, gpio102, gpio103, gpio104, + gpio105, gpio106, gpio107, gpio108, gpio109, gpio110, + gpio111, gpio112, gpio113, gpio114, gpio115, gpio116, + gpio117, gpio118, gpio119, gpio120, gpio121, gpio122, + gpio123, gpio124, gpio125, gpio126, gpio127 ] + + input-debounce: true + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + #include + pinctrl: pinctrl@b8003000 { + compatible = "nuvoton,wpcm450-pinctrl"; + reg = <0xb8003000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + gpio0: gpio@0 { + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH + 3 IRQ_TYPE_LEVEL_HIGH + 4 IRQ_TYPE_LEVEL_HIGH>; + nuvoton,interrupt-map = <0 16 0>; + }; + + mux_rmii2 { + groups = "rmii2"; + function = "rmii2"; + }; + + pinmux_uid: mux_uid { + groups = "gspi", "sspi"; + function = "gpio"; + }; + + pinctrl_uid: cfg_uid { + pins = "gpio14"; + input-debounce = <1>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uid>, <&pinmux_uid>; + + uid { + label = "UID"; + linux,code = <102>; + gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + }; + }; From patchwork Tue Dec 7 21:08:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 1564921 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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t=1638911338; bh=TSUe7hr/WBrDf46jzIs5Gq+0tXOKFoFSvTk4PJ/4hEA=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=KpoACaau4T7hYg231CxFk8YPc10lnceDhT7KQlHdCQIwYuR2YgSJOglwCa3utXscU xtq4D685uMLDA3kIXO9GboOsuIwdrwhR+6VLY9bjSAqrGe4eyjR2N279EWtWTbviAw 3Z4Zx9ZfRPf9HZjwzCcjQYRx/ahsOytnhWnFHghQ= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([5.146.194.160]) by mail.gmx.net (mrgmx104 [212.227.17.168]) with ESMTPSA (Nemesis) id 1Mw9QC-1mbnLR32ii-00s3OO; Tue, 07 Dec 2021 22:08:57 +0100 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 5/8] pinctrl: nuvoton: Add driver for WPCM450 Date: Tue, 7 Dec 2021 22:08:20 +0100 Message-Id: <20211207210823.1975632-6-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211207210823.1975632-1-j.neuschaefer@gmx.net> References: <20211207210823.1975632-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:QeqsC329B5FrkOzDfZhQlayciMWw8h9zkeZu/LWtd259UA/hGk4 6nr/l0ps3Er+CigtTLXNu/ja4tmYMF9MUtsPsNsL/va1uu5ChNt+ddsTFWeOq4KuDWJpCl8 l/fGRRHa3X1h6XtZzlWA+JIoYXhT/eqy/NxTytO3LP2BZMshoE7ZlPHj3qVzOB3biDQnYqg 1p6VuWOyIdEnvtUP63WaQ== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1;V03:K0:fH1w3fisNJk=:Vs2Xg8X/C8qD72ONFPUxry dH5r/lMwDEuLzq+GquUL8R0L9w8qLqZvWZq4WcxjhXpSGQpsiQY/Ty79cIkcP9NJ4yOhoETUO 0I4u0dERyNZljbyPiw/SYB57JqXgqTQmLdNbJk3p0B2VFDHEkcNLigE+NKeg6dtrYS49K7nva 5oYOHDpRp7o4tLkz/u4XJ80AdWgGiknyQQKZs1XUOPZqh/BOhex0sXu6Zu77GAqYKKmM4rYAd gTx0iq+mJClLNkUAu44PjeFNecsi/oC00TBg8U4oO+6oIVwJY3tL9p6q+Z0psyScXqt8u35WV LIqI2Kq5s9qEW/b3GkcoeBjFOazoRYIm6aix/i+ugBFKjcGyOjuHXO1Nnl8JrA4qcrj3gAcJ7 Ntee2VbvHahx9Jyy186Ijqc+fzbyUIlcgYUjTx55jdXi2ENT2AcsUIR2Dw5SyLWq6dcS26QOy BchoU+tTWAcun44YFSzBL55SLaDEaKeTaAd83rpOCGcF3eEOHJmBYUyRg8AwGKoLlUiXy4qyM zgpZgXc7zdlIoAKANVQlG7AgoQHdRxxZhIwYexwxQV08e7oyeBuYX6tHcOkqzxYFpw2k6wrVw o79E0+eAd1Q1Xmh/Aq9DpqLvmo0mDG/PVQqU4OIfSfIhssSPuE/riCMoIMuQ+VzoBreXKTuCD x8t366yNCu72/nAILofeGjx7HrU3qrjqanxNfyY37qc4PjwCq39CGwxa3CcHWM5+WAT5Phv2Y VZpuDQnA74+MGENfB7y6htAFJl4VKid7aqe3bkptiYDc1snIuxz6YBCzaRtD9LYtExC0v+n6X EnyLwvDWTqo5R6sBzsgioMb+Ge/BfcrwE9cfQVvsDsZBywIW9y9G0oqPSG8Zn1SIBacCjgcv5 bHmENzEUGF5C09m1C+LjyiXlp6xaBgRaI9gyHtg7xrT2ttN1IOtWQaYriTm6pwlbVJAXHGS2K /aybOArOVhyY7P8bB8HjzKtpZqBkfEdQzWy5vohFUgXiMsJSxPVkr3AP2CNlmF5tEze1teLS7 iEnkDUuVs6g1zILByDGBZEALthCW2cMkhv6UpSEusSyc54kphBlvQhpHygTXoGRniST1K6C2W BBq16ooC6nw3Cs= X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tomer Maimon , Linus Walleij , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Rob Herring , openbmc@lists.ozlabs.org Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" This driver is based on the one for NPCM7xx, because the WPCM450 is a predecessor of those SoCs. Notable differences: - WPCM450, the GPIO registers are not organized in multiple banks, but rather placed continually into the same register block. This affects how register offsets are computed. - Pinmux nodes can explicitly select GPIO mode, whereas, in the npcm7xx driver, this happens automatically when a GPIO is requested. Some functionality implemented in the hardware was (for now) left unused in the driver, specifically blinking and pull-up/down. Signed-off-by: Jonathan Neuschäfer Reported-by: kernel test robot Reported-by: kernel test robot --- This patch has a few checkpatch warnings, which are inherited from the pinctrl-npcm7xx driver. I decided to ignore those. Specifically: (1) WPCM450_GRPS is an unwrapped list; (2) use of -ENOTSUPP is discouraged. v2: - Adjust to binding change which put each GPIO bank into its own node - Use generic GPIO support - Make it possible to set pinmux to GPIO explicitly - Allow building the driver as a module - Fix spelling of "spin lock" in text - Include - Move linux/pinctrl/* headers to the end of the #include block - Remove/rework comments and printk messages - Switch to fwnode API - Remove comma after sentinel {} - Use dev_err_probe - Improve Kconfig help message - Declare for_each_set_bit iterator as unsigned int - Use __assign_bit - Set parent irq handler in set_irq_type callback - Use struct group_desc - Don't hide sysfs bind attributes - Remove unnecessary check for gpio-controller property - Use module_platform_driver() v1: - https://lore.kernel.org/lkml/20210602120329.2444672-6-j.neuschaefer@gmx.net/ --- MAINTAINERS | 1 + drivers/pinctrl/Makefile | 2 +- drivers/pinctrl/nuvoton/Kconfig | 18 + drivers/pinctrl/nuvoton/Makefile | 1 + drivers/pinctrl/nuvoton/pinctrl-wpcm450.c | 1134 +++++++++++++++++++++ 5 files changed, 1155 insertions(+), 1 deletion(-) create mode 100644 drivers/pinctrl/nuvoton/pinctrl-wpcm450.c -- 2.30.2 diff --git a/MAINTAINERS b/MAINTAINERS index eff3edafd8814..56c5c394877e1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2352,6 +2352,7 @@ S: Maintained F: Documentation/devicetree/bindings/*/*wpcm* F: arch/arm/boot/dts/nuvoton-wpcm450* F: arch/arm/mach-npcm/wpcm450.c +F: drivers/*/*/*wpcm* F: drivers/*/*wpcm* ARM/NXP S32G ARCHITECTURE diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 5e63de2ffcf41..823ff12847ed3 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -58,7 +58,7 @@ obj-y += freescale/ obj-$(CONFIG_X86) += intel/ obj-y += mvebu/ obj-y += nomadik/ -obj-$(CONFIG_ARCH_NPCM7XX) += nuvoton/ +obj-y += nuvoton/ obj-$(CONFIG_PINCTRL_PXA) += pxa/ obj-$(CONFIG_ARCH_QCOM) += qcom/ obj-$(CONFIG_PINCTRL_RALINK) += ralink/ diff --git a/drivers/pinctrl/nuvoton/Kconfig b/drivers/pinctrl/nuvoton/Kconfig index 48ba0469edda6..6a3c6f2a73f2d 100644 --- a/drivers/pinctrl/nuvoton/Kconfig +++ b/drivers/pinctrl/nuvoton/Kconfig @@ -1,4 +1,22 @@ # SPDX-License-Identifier: GPL-2.0-only + +config PINCTRL_WPCM450 + tristate "Pinctrl and GPIO driver for Nuvoton WPCM450" + depends on ARCH_WPCM450 || COMPILE_TEST + select PINMUX + select PINCONF + select GENERIC_PINCONF + select GPIOLIB + select GPIO_GENERIC + select GPIOLIB_IRQCHIP + help + Say Y or M here to enable pin controller and GPIO support for + the Nuvoton WPCM450 SoC. This is strongly recommended when + building a kernel that will run on this chip. + + If this driver is compiled as a module, it will be named + pinctrl-wpcm450. + config PINCTRL_NPCM7XX bool "Pinctrl and GPIO driver for Nuvoton NPCM7XX" depends on (ARCH_NPCM7XX || COMPILE_TEST) && OF diff --git a/drivers/pinctrl/nuvoton/Makefile b/drivers/pinctrl/nuvoton/Makefile index 886d00784cef5..9e66f5dc74bfc 100644 --- a/drivers/pinctrl/nuvoton/Makefile +++ b/drivers/pinctrl/nuvoton/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 # Nuvoton pinctrl support +obj-$(CONFIG_PINCTRL_WPCM450) += pinctrl-wpcm450.o obj-$(CONFIG_PINCTRL_NPCM7XX) += pinctrl-npcm7xx.o diff --git a/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c b/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c new file mode 100644 index 0000000000000..b1e190e45af93 --- /dev/null +++ b/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c @@ -0,0 +1,1134 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2016-2018 Nuvoton Technology corporation. +// Copyright (c) 2016, Dell Inc +// Copyright (c) 2021 Jonathan Neuschäfer +// +// This driver uses the following registers: +// - Pin mux registers, in the GCR (general control registers) block +// - GPIO registers, specific to each GPIO bank +// - GPIO event (interrupt) registers, located centrally in the GPIO register +// block, shared between all GPIO banks + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../core.h" + +/* GCR registers */ +#define WPCM450_GCR_MFSEL1 0x0C +#define WPCM450_GCR_MFSEL2 0x10 +#define WPCM450_GCR_NONE 0 + +/* GPIO event (interrupt) registers */ +#define WPCM450_GPEVTYPE 0x00 +#define WPCM450_GPEVPOL 0x04 +#define WPCM450_GPEVDBNC 0x08 +#define WPCM450_GPEVEN 0x0c +#define WPCM450_GPEVST 0x10 + +#define WPCM450_NUM_BANKS 8 +#define WPCM450_NUM_GPIOS 128 +#define WPCM450_NUM_GPIO_IRQS 4 + +struct wpcm450_pinctrl; + +struct wpcm450_gpio { + struct wpcm450_pinctrl *pctrl; + struct gpio_chip gc; + struct irq_chip irqc; + unsigned int first_irq_bit; + unsigned int num_irqs; + unsigned int first_irq_gpio; +}; + +struct wpcm450_pinctrl { + struct pinctrl_dev *pctldev; + struct device *dev; + struct irq_domain *domain; + struct regmap *gcr_regmap; + void __iomem *gpio_base; + struct wpcm450_gpio gpio_bank[WPCM450_NUM_BANKS]; + unsigned long both_edges; + + /* + * This spin lock protects registers and struct wpcm450_pinctrl fields + * against concurrent access. + */ + spinlock_t lock; +}; + +struct wpcm450_bank { + /* Range of GPIOs in this port */ + u8 base; + u8 length; + + /* Register offsets (0 = register doesn't exist in this port) */ + u8 cfg0, cfg1, cfg2; + u8 blink; + u8 dataout, datain; +}; + +static const struct wpcm450_bank wpcm450_banks[WPCM450_NUM_BANKS] = { + /* range cfg0 cfg1 cfg2 blink out in */ + { 0, 16, 0x14, 0x18, 0, 0, 0x1c, 0x20 }, + { 16, 16, 0x24, 0x28, 0x2c, 0x30, 0x34, 0x38 }, + { 32, 16, 0x3c, 0x40, 0x44, 0, 0x48, 0x4c }, + { 48, 16, 0x50, 0x54, 0x58, 0, 0x5c, 0x60 }, + { 64, 16, 0x64, 0x68, 0x6c, 0, 0x70, 0x74 }, + { 80, 16, 0x78, 0x7c, 0x80, 0, 0x84, 0x88 }, + { 96, 18, 0, 0, 0, 0, 0, 0x8c }, + { 114, 14, 0x90, 0x94, 0x98, 0, 0x9c, 0xa0 }, +}; + +static int wpcm450_gpio_irq_bitnum(struct wpcm450_gpio *gpio, struct irq_data *d) +{ + int hwirq = irqd_to_hwirq(d); + + if (hwirq < gpio->first_irq_gpio) + return -EINVAL; + + if (hwirq - gpio->first_irq_gpio >= gpio->num_irqs) + return -EINVAL; + + return hwirq - gpio->first_irq_gpio + gpio->first_irq_bit; +} + +static int wpcm450_irq_bitnum_to_gpio(struct wpcm450_gpio *gpio, int bitnum) +{ + if (bitnum < gpio->first_irq_bit) + return -EINVAL; + + if (bitnum - gpio->first_irq_bit > gpio->num_irqs) + return -EINVAL; + + return bitnum - gpio->first_irq_bit + gpio->first_irq_gpio; +} + +static void wpcm450_gpio_irq_ack(struct irq_data *d) +{ + struct wpcm450_gpio *gpio = gpiochip_get_data(irq_data_get_irq_chip_data(d)); + struct wpcm450_pinctrl *pctrl = gpio->pctrl; + unsigned long flags; + int bit; + + bit = wpcm450_gpio_irq_bitnum(gpio, d); + if (bit < 0) + return; + + spin_lock_irqsave(&pctrl->lock, flags); + iowrite32(BIT(bit), pctrl->gpio_base + WPCM450_GPEVST); + spin_unlock_irqrestore(&pctrl->lock, flags); +} + +static void wpcm450_gpio_irq_mask(struct irq_data *d) +{ + struct wpcm450_gpio *gpio = gpiochip_get_data(irq_data_get_irq_chip_data(d)); + struct wpcm450_pinctrl *pctrl = gpio->pctrl; + unsigned long flags; + unsigned long even; + int bit; + + bit = wpcm450_gpio_irq_bitnum(gpio, d); + if (bit < 0) + return; + + spin_lock_irqsave(&pctrl->lock, flags); + even = ioread32(pctrl->gpio_base + WPCM450_GPEVEN); + __assign_bit(bit, &even, 0); + iowrite32(even, pctrl->gpio_base + WPCM450_GPEVEN); + spin_unlock_irqrestore(&pctrl->lock, flags); +} + +static void wpcm450_gpio_irq_unmask(struct irq_data *d) +{ + struct wpcm450_gpio *gpio = gpiochip_get_data(irq_data_get_irq_chip_data(d)); + struct wpcm450_pinctrl *pctrl = gpio->pctrl; + unsigned long flags; + unsigned long even; + int bit; + + bit = wpcm450_gpio_irq_bitnum(gpio, d); + if (bit < 0) + return; + + spin_lock_irqsave(&pctrl->lock, flags); + even = ioread32(pctrl->gpio_base + WPCM450_GPEVEN); + __assign_bit(bit, &even, 1); + iowrite32(even, pctrl->gpio_base + WPCM450_GPEVEN); + spin_unlock_irqrestore(&pctrl->lock, flags); +} + +static void wpcm450_gpio_fix_evpol(struct wpcm450_gpio *gpio, unsigned long all) +{ + struct wpcm450_pinctrl *pctrl = gpio->pctrl; + unsigned long flags; + unsigned int bit; + + for_each_set_bit(bit, &all, 32) { + int offset = wpcm450_irq_bitnum_to_gpio(gpio, bit); + unsigned long evpol; + int level; + + spin_lock_irqsave(&gpio->gc.bgpio_lock, flags); + do { + evpol = ioread32(pctrl->gpio_base + WPCM450_GPEVPOL); + level = gpio->gc.get(&gpio->gc, offset); + + /* Switch event polarity to the opposite of the current level */ + __assign_bit(bit, &evpol, !level); + + iowrite32(evpol, pctrl->gpio_base + WPCM450_GPEVPOL); + } while (gpio->gc.get(&gpio->gc, offset) != level); + spin_unlock_irqrestore(&gpio->gc.bgpio_lock, flags); + } +} + +static int wpcm450_gpio_set_irq_type(struct irq_data *d, unsigned int flow_type) +{ + struct wpcm450_gpio *gpio = gpiochip_get_data(irq_data_get_irq_chip_data(d)); + struct wpcm450_pinctrl *pctrl = gpio->pctrl; + unsigned long evtype, evpol; + unsigned long flags; + int ret = 0; + int bit; + + bit = wpcm450_gpio_irq_bitnum(gpio, d); + if (bit < 0) + return bit; + + irq_set_handler_locked(d, handle_level_irq); + + spin_lock_irqsave(&pctrl->lock, flags); + evtype = ioread32(pctrl->gpio_base + WPCM450_GPEVTYPE); + evpol = ioread32(pctrl->gpio_base + WPCM450_GPEVPOL); + __assign_bit(bit, &pctrl->both_edges, 0); + switch (flow_type) { + case IRQ_TYPE_LEVEL_LOW: + __assign_bit(bit, &evtype, 1); + __assign_bit(bit, &evpol, 0); + break; + case IRQ_TYPE_LEVEL_HIGH: + __assign_bit(bit, &evtype, 1); + __assign_bit(bit, &evpol, 1); + break; + case IRQ_TYPE_EDGE_FALLING: + __assign_bit(bit, &evtype, 0); + __assign_bit(bit, &evpol, 0); + break; + case IRQ_TYPE_EDGE_RISING: + __assign_bit(bit, &evtype, 0); + __assign_bit(bit, &evpol, 1); + break; + case IRQ_TYPE_EDGE_BOTH: + __assign_bit(bit, &evtype, 0); + __assign_bit(bit, &pctrl->both_edges, 1); + break; + default: + ret = -EINVAL; + } + iowrite32(evtype, pctrl->gpio_base + WPCM450_GPEVTYPE); + iowrite32(evpol, pctrl->gpio_base + WPCM450_GPEVPOL); + + /* clear the event status for good measure */ + iowrite32(BIT(bit), pctrl->gpio_base + WPCM450_GPEVST); + + /* fix event polarity after clearing event status */ + wpcm450_gpio_fix_evpol(gpio, BIT(bit)); + + spin_unlock_irqrestore(&pctrl->lock, flags); + + return ret; +} + +static const struct irq_chip wpcm450_gpio_irqchip = { + .name = "WPCM450-GPIO-IRQ", + .irq_ack = wpcm450_gpio_irq_ack, + .irq_unmask = wpcm450_gpio_irq_unmask, + .irq_mask = wpcm450_gpio_irq_mask, + .irq_set_type = wpcm450_gpio_set_irq_type, +}; + +static void wpcm450_gpio_irqhandler(struct irq_desc *desc) +{ + struct wpcm450_gpio *gpio = gpiochip_get_data(irq_desc_get_handler_data(desc)); + struct wpcm450_pinctrl *pctrl = gpio->pctrl; + struct irq_chip *chip = irq_desc_get_chip(desc); + unsigned long pending; + unsigned long flags; + unsigned long ours; + unsigned int bit; + + ours = ((1UL << gpio->num_irqs) - 1) << gpio->first_irq_bit; + + spin_lock_irqsave(&pctrl->lock, flags); + + pending = ioread32(pctrl->gpio_base + WPCM450_GPEVST); + pending &= ioread32(pctrl->gpio_base + WPCM450_GPEVEN); + pending &= ours; + + if (pending & pctrl->both_edges) + wpcm450_gpio_fix_evpol(gpio, pending & pctrl->both_edges); + + spin_unlock_irqrestore(&pctrl->lock, flags); + + chained_irq_enter(chip, desc); + for_each_set_bit(bit, &pending, 32) { + int offset = wpcm450_irq_bitnum_to_gpio(gpio, bit); + int irq = irq_find_mapping(gpio->gc.irq.domain, offset); + + generic_handle_irq(irq); + } + chained_irq_exit(chip, desc); +} + +static int smb0_pins[] = { 115, 114 }; +static int smb1_pins[] = { 117, 116 }; +static int smb2_pins[] = { 119, 118 }; +static int smb3_pins[] = { 30, 31 }; +static int smb4_pins[] = { 28, 29 }; +static int smb5_pins[] = { 26, 27 }; + +static int scs1_pins[] = { 32 }; +static int scs2_pins[] = { 33 }; +static int scs3_pins[] = { 34 }; + +static int bsp_pins[] = { 41, 42 }; +static int hsp1_pins[] = { 43, 44, 45, 46, 47, 61, 62, 63 }; +static int hsp2_pins[] = { 48, 49, 50, 51, 52, 53, 54, 55 }; + +static int r1err_pins[] = { 56 }; +static int r1md_pins[] = { 57, 58 }; +static int rmii2_pins[] = { 84, 85, 86, 87, 88, 89 }; +static int r2err_pins[] = { 90 }; +static int r2md_pins[] = { 91, 92 }; + +static int kbcc_pins[] = { 94, 93 }; +static int clko_pins[] = { 96 }; +static int smi_pins[] = { 97 }; +static int uinc_pins[] = { 19 }; +static int mben_pins[] = {}; + +static int gspi_pins[] = { 12, 13, 14, 15 }; +static int sspi_pins[] = { 12, 13, 14, 15 }; + +static int xcs1_pins[] = { 35 }; +static int xcs2_pins[] = { 36 }; + +static int sdio_pins[] = { 7, 22, 43, 44, 45, 46, 47, 60 }; + +static int fi0_pins[] = { 64 }; +static int fi1_pins[] = { 65 }; +static int fi2_pins[] = { 66 }; +static int fi3_pins[] = { 67 }; +static int fi4_pins[] = { 68 }; +static int fi5_pins[] = { 69 }; +static int fi6_pins[] = { 70 }; +static int fi7_pins[] = { 71 }; +static int fi8_pins[] = { 72 }; +static int fi9_pins[] = { 73 }; +static int fi10_pins[] = { 74 }; +static int fi11_pins[] = { 75 }; +static int fi12_pins[] = { 76 }; +static int fi13_pins[] = { 77 }; +static int fi14_pins[] = { 78 }; +static int fi15_pins[] = { 79 }; + +static int pwm0_pins[] = { 80 }; +static int pwm1_pins[] = { 81 }; +static int pwm2_pins[] = { 82 }; +static int pwm3_pins[] = { 83 }; +static int pwm4_pins[] = { 20 }; +static int pwm5_pins[] = { 21 }; +static int pwm6_pins[] = { 16 }; +static int pwm7_pins[] = { 17 }; + +static int hg0_pins[] = { 20 }; +static int hg1_pins[] = { 21 }; +static int hg2_pins[] = { 22 }; +static int hg3_pins[] = { 23 }; +static int hg4_pins[] = { 24 }; +static int hg5_pins[] = { 25 }; +static int hg6_pins[] = { 59 }; +static int hg7_pins[] = { 60 }; + +#define WPCM450_GRPS \ + WPCM450_GRP(smb3), \ + WPCM450_GRP(smb4), \ + WPCM450_GRP(smb5), \ + WPCM450_GRP(scs1), \ + WPCM450_GRP(scs2), \ + WPCM450_GRP(scs3), \ + WPCM450_GRP(smb0), \ + WPCM450_GRP(smb1), \ + WPCM450_GRP(smb2), \ + WPCM450_GRP(bsp), \ + WPCM450_GRP(hsp1), \ + WPCM450_GRP(hsp2), \ + WPCM450_GRP(r1err), \ + WPCM450_GRP(r1md), \ + WPCM450_GRP(rmii2), \ + WPCM450_GRP(r2err), \ + WPCM450_GRP(r2md), \ + WPCM450_GRP(kbcc), \ + WPCM450_GRP(clko), \ + WPCM450_GRP(smi), \ + WPCM450_GRP(uinc), \ + WPCM450_GRP(gspi), \ + WPCM450_GRP(mben), \ + WPCM450_GRP(xcs2), \ + WPCM450_GRP(xcs1), \ + WPCM450_GRP(sdio), \ + WPCM450_GRP(sspi), \ + WPCM450_GRP(fi0), \ + WPCM450_GRP(fi1), \ + WPCM450_GRP(fi2), \ + WPCM450_GRP(fi3), \ + WPCM450_GRP(fi4), \ + WPCM450_GRP(fi5), \ + WPCM450_GRP(fi6), \ + WPCM450_GRP(fi7), \ + WPCM450_GRP(fi8), \ + WPCM450_GRP(fi9), \ + WPCM450_GRP(fi10), \ + WPCM450_GRP(fi11), \ + WPCM450_GRP(fi12), \ + WPCM450_GRP(fi13), \ + WPCM450_GRP(fi14), \ + WPCM450_GRP(fi15), \ + WPCM450_GRP(pwm0), \ + WPCM450_GRP(pwm1), \ + WPCM450_GRP(pwm2), \ + WPCM450_GRP(pwm3), \ + WPCM450_GRP(pwm4), \ + WPCM450_GRP(pwm5), \ + WPCM450_GRP(pwm6), \ + WPCM450_GRP(pwm7), \ + WPCM450_GRP(hg0), \ + WPCM450_GRP(hg1), \ + WPCM450_GRP(hg2), \ + WPCM450_GRP(hg3), \ + WPCM450_GRP(hg4), \ + WPCM450_GRP(hg5), \ + WPCM450_GRP(hg6), \ + WPCM450_GRP(hg7), \ + +enum { +#define WPCM450_GRP(x) fn_ ## x + WPCM450_GRPS + /* add placeholder for none/gpio */ + WPCM450_GRP(gpio), + WPCM450_GRP(none), +#undef WPCM450_GRP +}; + +static struct group_desc wpcm450_groups[] = { +#define WPCM450_GRP(x) { .name = #x, .pins = x ## _pins, \ + .num_pins = ARRAY_SIZE(x ## _pins) } + WPCM450_GRPS +#undef WPCM450_GRP +}; + +#define WPCM450_SFUNC(a) WPCM450_FUNC(a, #a) +#define WPCM450_FUNC(a, b...) static const char *a ## _grp[] = { b } +#define WPCM450_MKFUNC(nm) { .name = #nm, .ngroups = ARRAY_SIZE(nm ## _grp), \ + .groups = nm ## _grp } +struct wpcm450_func { + const char *name; + const unsigned int ngroups; + const char *const *groups; +}; + +WPCM450_SFUNC(smb3); +WPCM450_SFUNC(smb4); +WPCM450_SFUNC(smb5); +WPCM450_SFUNC(scs1); +WPCM450_SFUNC(scs2); +WPCM450_SFUNC(scs3); +WPCM450_SFUNC(smb0); +WPCM450_SFUNC(smb1); +WPCM450_SFUNC(smb2); +WPCM450_SFUNC(bsp); +WPCM450_SFUNC(hsp1); +WPCM450_SFUNC(hsp2); +WPCM450_SFUNC(r1err); +WPCM450_SFUNC(r1md); +WPCM450_SFUNC(rmii2); +WPCM450_SFUNC(r2err); +WPCM450_SFUNC(r2md); +WPCM450_SFUNC(kbcc); +WPCM450_SFUNC(clko); +WPCM450_SFUNC(smi); +WPCM450_SFUNC(uinc); +WPCM450_SFUNC(gspi); +WPCM450_SFUNC(mben); +WPCM450_SFUNC(xcs2); +WPCM450_SFUNC(xcs1); +WPCM450_SFUNC(sdio); +WPCM450_SFUNC(sspi); +WPCM450_SFUNC(fi0); +WPCM450_SFUNC(fi1); +WPCM450_SFUNC(fi2); +WPCM450_SFUNC(fi3); +WPCM450_SFUNC(fi4); +WPCM450_SFUNC(fi5); +WPCM450_SFUNC(fi6); +WPCM450_SFUNC(fi7); +WPCM450_SFUNC(fi8); +WPCM450_SFUNC(fi9); +WPCM450_SFUNC(fi10); +WPCM450_SFUNC(fi11); +WPCM450_SFUNC(fi12); +WPCM450_SFUNC(fi13); +WPCM450_SFUNC(fi14); +WPCM450_SFUNC(fi15); +WPCM450_SFUNC(pwm0); +WPCM450_SFUNC(pwm1); +WPCM450_SFUNC(pwm2); +WPCM450_SFUNC(pwm3); +WPCM450_SFUNC(pwm4); +WPCM450_SFUNC(pwm5); +WPCM450_SFUNC(pwm6); +WPCM450_SFUNC(pwm7); +WPCM450_SFUNC(hg0); +WPCM450_SFUNC(hg1); +WPCM450_SFUNC(hg2); +WPCM450_SFUNC(hg3); +WPCM450_SFUNC(hg4); +WPCM450_SFUNC(hg5); +WPCM450_SFUNC(hg6); +WPCM450_SFUNC(hg7); + +#define WPCM450_GRP(x) #x +WPCM450_FUNC(gpio, WPCM450_GRPS); +#undef WPCM450_GRP + +/* Function names */ +static struct wpcm450_func wpcm450_funcs[] = { + WPCM450_MKFUNC(smb3), + WPCM450_MKFUNC(smb4), + WPCM450_MKFUNC(smb5), + WPCM450_MKFUNC(scs1), + WPCM450_MKFUNC(scs2), + WPCM450_MKFUNC(scs3), + WPCM450_MKFUNC(smb0), + WPCM450_MKFUNC(smb1), + WPCM450_MKFUNC(smb2), + WPCM450_MKFUNC(bsp), + WPCM450_MKFUNC(hsp1), + WPCM450_MKFUNC(hsp2), + WPCM450_MKFUNC(r1err), + WPCM450_MKFUNC(r1md), + WPCM450_MKFUNC(rmii2), + WPCM450_MKFUNC(r2err), + WPCM450_MKFUNC(r2md), + WPCM450_MKFUNC(kbcc), + WPCM450_MKFUNC(clko), + WPCM450_MKFUNC(smi), + WPCM450_MKFUNC(uinc), + WPCM450_MKFUNC(gspi), + WPCM450_MKFUNC(mben), + WPCM450_MKFUNC(xcs2), + WPCM450_MKFUNC(xcs1), + WPCM450_MKFUNC(sdio), + WPCM450_MKFUNC(sspi), + WPCM450_MKFUNC(fi0), + WPCM450_MKFUNC(fi1), + WPCM450_MKFUNC(fi2), + WPCM450_MKFUNC(fi3), + WPCM450_MKFUNC(fi4), + WPCM450_MKFUNC(fi5), + WPCM450_MKFUNC(fi6), + WPCM450_MKFUNC(fi7), + WPCM450_MKFUNC(fi8), + WPCM450_MKFUNC(fi9), + WPCM450_MKFUNC(fi10), + WPCM450_MKFUNC(fi11), + WPCM450_MKFUNC(fi12), + WPCM450_MKFUNC(fi13), + WPCM450_MKFUNC(fi14), + WPCM450_MKFUNC(fi15), + WPCM450_MKFUNC(pwm0), + WPCM450_MKFUNC(pwm1), + WPCM450_MKFUNC(pwm2), + WPCM450_MKFUNC(pwm3), + WPCM450_MKFUNC(pwm4), + WPCM450_MKFUNC(pwm5), + WPCM450_MKFUNC(pwm6), + WPCM450_MKFUNC(pwm7), + WPCM450_MKFUNC(hg0), + WPCM450_MKFUNC(hg1), + WPCM450_MKFUNC(hg2), + WPCM450_MKFUNC(hg3), + WPCM450_MKFUNC(hg4), + WPCM450_MKFUNC(hg5), + WPCM450_MKFUNC(hg6), + WPCM450_MKFUNC(hg7), + WPCM450_MKFUNC(gpio), +}; + +#define WPCM450_PINCFG(a, b, c, d, e, f, g) \ + [a] { .fn0 = fn_ ## b, .reg0 = WPCM450_GCR_ ## c, .bit0 = d, \ + .fn1 = fn_ ## e, .reg1 = WPCM450_GCR_ ## f, .bit1 = g } + +struct wpcm450_pincfg { + int fn0, reg0, bit0; + int fn1, reg1, bit1; +}; + +static const struct wpcm450_pincfg pincfg[] = { + /* PIN FUNCTION 1 FUNCTION 2 */ + WPCM450_PINCFG(0, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(1, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(2, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(3, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(4, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(5, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(6, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(7, none, NONE, 0, sdio, MFSEL1, 30), + WPCM450_PINCFG(8, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(9, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(10, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(11, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(12, gspi, MFSEL1, 24, sspi, MFSEL1, 31), + WPCM450_PINCFG(13, gspi, MFSEL1, 24, sspi, MFSEL1, 31), + WPCM450_PINCFG(14, gspi, MFSEL1, 24, sspi, MFSEL1, 31), + WPCM450_PINCFG(15, gspi, MFSEL1, 24, sspi, MFSEL1, 31), + WPCM450_PINCFG(16, none, NONE, 0, pwm6, MFSEL2, 22), + WPCM450_PINCFG(17, none, NONE, 0, pwm7, MFSEL2, 23), + WPCM450_PINCFG(18, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(19, uinc, MFSEL1, 23, none, NONE, 0), + WPCM450_PINCFG(20, hg0, MFSEL2, 24, pwm4, MFSEL2, 20), + WPCM450_PINCFG(21, hg1, MFSEL2, 25, pwm5, MFSEL2, 21), + WPCM450_PINCFG(22, hg2, MFSEL2, 26, none, NONE, 0), + WPCM450_PINCFG(23, hg3, MFSEL2, 27, none, NONE, 0), + WPCM450_PINCFG(24, hg4, MFSEL2, 28, none, NONE, 0), + WPCM450_PINCFG(25, hg5, MFSEL2, 29, none, NONE, 0), + WPCM450_PINCFG(26, smb5, MFSEL1, 2, none, NONE, 0), + WPCM450_PINCFG(27, smb5, MFSEL1, 2, none, NONE, 0), + WPCM450_PINCFG(28, smb4, MFSEL1, 1, none, NONE, 0), + WPCM450_PINCFG(29, smb4, MFSEL1, 1, none, NONE, 0), + WPCM450_PINCFG(30, smb3, MFSEL1, 0, none, NONE, 0), + WPCM450_PINCFG(31, smb3, MFSEL1, 0, none, NONE, 0), + + WPCM450_PINCFG(32, scs1, MFSEL1, 3, none, NONE, 0), + WPCM450_PINCFG(33, scs2, MFSEL1, 4, none, NONE, 0), + WPCM450_PINCFG(34, scs3, MFSEL1, 5, none, NONE, 0), + WPCM450_PINCFG(35, xcs1, MFSEL1, 29, none, NONE, 0), + WPCM450_PINCFG(36, xcs2, MFSEL1, 28, none, NONE, 0), + WPCM450_PINCFG(37, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(38, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(39, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(40, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(41, bsp, MFSEL1, 9, none, NONE, 0), + WPCM450_PINCFG(42, bsp, MFSEL1, 9, none, NONE, 0), + WPCM450_PINCFG(43, hsp1, MFSEL1, 10, sdio, MFSEL1, 30), + WPCM450_PINCFG(44, hsp1, MFSEL1, 10, sdio, MFSEL1, 30), + WPCM450_PINCFG(45, hsp1, MFSEL1, 10, sdio, MFSEL1, 30), + WPCM450_PINCFG(46, hsp1, MFSEL1, 10, sdio, MFSEL1, 30), + WPCM450_PINCFG(47, hsp1, MFSEL1, 10, sdio, MFSEL1, 30), + WPCM450_PINCFG(48, hsp2, MFSEL1, 11, none, NONE, 0), + WPCM450_PINCFG(49, hsp2, MFSEL1, 11, none, NONE, 0), + WPCM450_PINCFG(50, hsp2, MFSEL1, 11, none, NONE, 0), + WPCM450_PINCFG(51, hsp2, MFSEL1, 11, none, NONE, 0), + WPCM450_PINCFG(52, hsp2, MFSEL1, 11, none, NONE, 0), + WPCM450_PINCFG(53, hsp2, MFSEL1, 11, none, NONE, 0), + WPCM450_PINCFG(54, hsp2, MFSEL1, 11, none, NONE, 0), + WPCM450_PINCFG(55, hsp2, MFSEL1, 11, none, NONE, 0), + WPCM450_PINCFG(56, r1err, MFSEL1, 12, none, NONE, 0), + WPCM450_PINCFG(57, r1md, MFSEL1, 13, none, NONE, 0), + WPCM450_PINCFG(58, r1md, MFSEL1, 13, none, NONE, 0), + WPCM450_PINCFG(59, hg6, MFSEL2, 30, none, NONE, 0), + WPCM450_PINCFG(60, hg7, MFSEL2, 31, sdio, MFSEL1, 30), + WPCM450_PINCFG(61, hsp1, MFSEL1, 10, none, NONE, 0), + WPCM450_PINCFG(62, hsp1, MFSEL1, 10, none, NONE, 0), + WPCM450_PINCFG(63, hsp1, MFSEL1, 10, none, NONE, 0), + + WPCM450_PINCFG(64, fi0, MFSEL2, 0, none, NONE, 0), + WPCM450_PINCFG(65, fi1, MFSEL2, 1, none, NONE, 0), + WPCM450_PINCFG(66, fi2, MFSEL2, 2, none, NONE, 0), + WPCM450_PINCFG(67, fi3, MFSEL2, 3, none, NONE, 0), + WPCM450_PINCFG(68, fi4, MFSEL2, 4, none, NONE, 0), + WPCM450_PINCFG(69, fi5, MFSEL2, 5, none, NONE, 0), + WPCM450_PINCFG(70, fi6, MFSEL2, 6, none, NONE, 0), + WPCM450_PINCFG(71, fi7, MFSEL2, 7, none, NONE, 0), + WPCM450_PINCFG(72, fi8, MFSEL2, 8, none, NONE, 0), + WPCM450_PINCFG(73, fi9, MFSEL2, 9, none, NONE, 0), + WPCM450_PINCFG(74, fi10, MFSEL2, 10, none, NONE, 0), + WPCM450_PINCFG(75, fi11, MFSEL2, 11, none, NONE, 0), + WPCM450_PINCFG(76, fi12, MFSEL2, 12, none, NONE, 0), + WPCM450_PINCFG(77, fi13, MFSEL2, 13, none, NONE, 0), + WPCM450_PINCFG(78, fi14, MFSEL2, 14, none, NONE, 0), + WPCM450_PINCFG(79, fi15, MFSEL2, 15, none, NONE, 0), + WPCM450_PINCFG(80, pwm0, MFSEL2, 16, none, NONE, 0), + WPCM450_PINCFG(81, pwm1, MFSEL2, 17, none, NONE, 0), + WPCM450_PINCFG(82, pwm2, MFSEL2, 18, none, NONE, 0), + WPCM450_PINCFG(83, pwm3, MFSEL2, 19, none, NONE, 0), + WPCM450_PINCFG(84, rmii2, MFSEL1, 14, none, NONE, 0), + WPCM450_PINCFG(85, rmii2, MFSEL1, 14, none, NONE, 0), + WPCM450_PINCFG(86, rmii2, MFSEL1, 14, none, NONE, 0), + WPCM450_PINCFG(87, rmii2, MFSEL1, 14, none, NONE, 0), + WPCM450_PINCFG(88, rmii2, MFSEL1, 14, none, NONE, 0), + WPCM450_PINCFG(89, rmii2, MFSEL1, 14, none, NONE, 0), + WPCM450_PINCFG(90, r2err, MFSEL1, 15, none, NONE, 0), + WPCM450_PINCFG(91, r2md, MFSEL1, 16, none, NONE, 0), + WPCM450_PINCFG(92, r2md, MFSEL1, 16, none, NONE, 0), + WPCM450_PINCFG(93, kbcc, MFSEL1, 17, none, NONE, 0), + WPCM450_PINCFG(94, kbcc, MFSEL1, 17, none, NONE, 0), + WPCM450_PINCFG(95, none, NONE, 0, none, NONE, 0), + + WPCM450_PINCFG(96, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(97, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(98, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(99, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(100, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(101, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(102, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(103, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(104, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(105, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(106, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(107, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(108, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(109, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(110, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(111, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(112, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(113, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(114, smb0, MFSEL1, 6, none, NONE, 0), + WPCM450_PINCFG(115, smb0, MFSEL1, 6, none, NONE, 0), + WPCM450_PINCFG(116, smb1, MFSEL1, 7, none, NONE, 0), + WPCM450_PINCFG(117, smb1, MFSEL1, 7, none, NONE, 0), + WPCM450_PINCFG(118, smb2, MFSEL1, 8, none, NONE, 0), + WPCM450_PINCFG(119, smb2, MFSEL1, 8, none, NONE, 0), + WPCM450_PINCFG(120, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(121, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(122, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(123, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(124, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(125, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(126, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(127, none, NONE, 0, none, NONE, 0), /* DVO */ +}; + +#define WPCM450_PIN(n) PINCTRL_PIN(n, "gpio" #n) + +static const struct pinctrl_pin_desc wpcm450_pins[] = { + WPCM450_PIN(0), WPCM450_PIN(1), WPCM450_PIN(2), WPCM450_PIN(3), + WPCM450_PIN(4), WPCM450_PIN(5), WPCM450_PIN(6), WPCM450_PIN(7), + WPCM450_PIN(8), WPCM450_PIN(9), WPCM450_PIN(10), WPCM450_PIN(11), + WPCM450_PIN(12), WPCM450_PIN(13), WPCM450_PIN(14), WPCM450_PIN(15), + WPCM450_PIN(16), WPCM450_PIN(17), WPCM450_PIN(18), WPCM450_PIN(19), + WPCM450_PIN(20), WPCM450_PIN(21), WPCM450_PIN(22), WPCM450_PIN(23), + WPCM450_PIN(24), WPCM450_PIN(25), WPCM450_PIN(26), WPCM450_PIN(27), + WPCM450_PIN(28), WPCM450_PIN(29), WPCM450_PIN(30), WPCM450_PIN(31), + WPCM450_PIN(32), WPCM450_PIN(33), WPCM450_PIN(34), WPCM450_PIN(35), + WPCM450_PIN(36), WPCM450_PIN(37), WPCM450_PIN(38), WPCM450_PIN(39), + WPCM450_PIN(40), WPCM450_PIN(41), WPCM450_PIN(42), WPCM450_PIN(43), + WPCM450_PIN(44), WPCM450_PIN(45), WPCM450_PIN(46), WPCM450_PIN(47), + WPCM450_PIN(48), WPCM450_PIN(49), WPCM450_PIN(50), WPCM450_PIN(51), + WPCM450_PIN(52), WPCM450_PIN(53), WPCM450_PIN(54), WPCM450_PIN(55), + WPCM450_PIN(56), WPCM450_PIN(57), WPCM450_PIN(58), WPCM450_PIN(59), + WPCM450_PIN(60), WPCM450_PIN(61), WPCM450_PIN(62), WPCM450_PIN(63), + WPCM450_PIN(64), WPCM450_PIN(65), WPCM450_PIN(66), WPCM450_PIN(67), + WPCM450_PIN(68), WPCM450_PIN(69), WPCM450_PIN(70), WPCM450_PIN(71), + WPCM450_PIN(72), WPCM450_PIN(73), WPCM450_PIN(74), WPCM450_PIN(75), + WPCM450_PIN(76), WPCM450_PIN(77), WPCM450_PIN(78), WPCM450_PIN(79), + WPCM450_PIN(80), WPCM450_PIN(81), WPCM450_PIN(82), WPCM450_PIN(83), + WPCM450_PIN(84), WPCM450_PIN(85), WPCM450_PIN(86), WPCM450_PIN(87), + WPCM450_PIN(88), WPCM450_PIN(89), WPCM450_PIN(90), WPCM450_PIN(91), + WPCM450_PIN(92), WPCM450_PIN(93), WPCM450_PIN(94), WPCM450_PIN(95), + WPCM450_PIN(96), WPCM450_PIN(97), WPCM450_PIN(98), WPCM450_PIN(99), + WPCM450_PIN(100), WPCM450_PIN(101), WPCM450_PIN(102), WPCM450_PIN(103), + WPCM450_PIN(104), WPCM450_PIN(105), WPCM450_PIN(106), WPCM450_PIN(107), + WPCM450_PIN(108), WPCM450_PIN(109), WPCM450_PIN(110), WPCM450_PIN(111), + WPCM450_PIN(112), WPCM450_PIN(113), WPCM450_PIN(114), WPCM450_PIN(115), + WPCM450_PIN(116), WPCM450_PIN(117), WPCM450_PIN(118), WPCM450_PIN(119), + WPCM450_PIN(120), WPCM450_PIN(121), WPCM450_PIN(122), WPCM450_PIN(123), + WPCM450_PIN(124), WPCM450_PIN(125), WPCM450_PIN(126), WPCM450_PIN(127), +}; + +/* Enable mode in pin group */ +static void wpcm450_setfunc(struct regmap *gcr_regmap, const unsigned int *pin, + int npins, int func) +{ + const struct wpcm450_pincfg *cfg; + int i; + + for (i = 0; i < npins; i++) { + cfg = &pincfg[pin[i]]; + if (func == fn_gpio || cfg->fn0 == func || cfg->fn1 == func) { + if (cfg->reg0) + regmap_update_bits(gcr_regmap, cfg->reg0, + BIT(cfg->bit0), + (cfg->fn0 == func) ? BIT(cfg->bit0) : 0); + if (cfg->reg1) + regmap_update_bits(gcr_regmap, cfg->reg1, + BIT(cfg->bit1), + (cfg->fn1 == func) ? BIT(cfg->bit1) : 0); + } + } +} + +static int wpcm450_get_groups_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(wpcm450_groups); +} + +static const char *wpcm450_get_group_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + return wpcm450_groups[selector].name; +} + +static int wpcm450_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int selector, + const unsigned int **pins, + unsigned int *npins) +{ + *npins = wpcm450_groups[selector].num_pins; + *pins = wpcm450_groups[selector].pins; + + return 0; +} + +static int wpcm450_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, + u32 *num_maps) +{ + return pinconf_generic_dt_node_to_map(pctldev, np_config, + map, num_maps, + PIN_MAP_TYPE_INVALID); +} + +static void wpcm450_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, u32 num_maps) +{ + kfree(map); +} + +static const struct pinctrl_ops wpcm450_pinctrl_ops = { + .get_groups_count = wpcm450_get_groups_count, + .get_group_name = wpcm450_get_group_name, + .get_group_pins = wpcm450_get_group_pins, + .dt_node_to_map = wpcm450_dt_node_to_map, + .dt_free_map = wpcm450_dt_free_map, +}; + +static int wpcm450_get_functions_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(wpcm450_funcs); +} + +static const char *wpcm450_get_function_name(struct pinctrl_dev *pctldev, + unsigned int function) +{ + return wpcm450_funcs[function].name; +} + +static int wpcm450_get_function_groups(struct pinctrl_dev *pctldev, + unsigned int function, + const char * const **groups, + unsigned int * const ngroups) +{ + *ngroups = wpcm450_funcs[function].ngroups; + *groups = wpcm450_funcs[function].groups; + + return 0; +} + +static int wpcm450_pinmux_set_mux(struct pinctrl_dev *pctldev, + unsigned int function, + unsigned int group) +{ + struct wpcm450_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + wpcm450_setfunc(pctrl->gcr_regmap, wpcm450_groups[group].pins, + wpcm450_groups[group].num_pins, function); + + return 0; +} + +static const struct pinmux_ops wpcm450_pinmux_ops = { + .get_functions_count = wpcm450_get_functions_count, + .get_function_name = wpcm450_get_function_name, + .get_function_groups = wpcm450_get_function_groups, + .set_mux = wpcm450_pinmux_set_mux, +}; + +static int debounce_bitnum(int gpio) +{ + if (gpio >= 0 && gpio < 16) + return gpio; + return -EINVAL; +} + +static int wpcm450_config_get(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *config) +{ + struct wpcm450_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param = pinconf_to_config_param(*config); + unsigned long flags; + int bit; + u32 reg; + + switch (param) { + case PIN_CONFIG_INPUT_DEBOUNCE: + bit = debounce_bitnum(pin); + if (bit < 0) + return bit; + + spin_lock_irqsave(&pctrl->lock, flags); + reg = ioread32(pctrl->gpio_base + WPCM450_GPEVDBNC); + spin_unlock_irqrestore(&pctrl->lock, flags); + + *config = pinconf_to_config_packed(param, !!(reg & BIT(bit))); + break; + default: + return -ENOTSUPP; + } + + return 0; +} + +static int wpcm450_config_set_one(struct wpcm450_pinctrl *pctrl, + unsigned int pin, unsigned long config) +{ + enum pin_config_param param = pinconf_to_config_param(config); + unsigned long flags; + unsigned long reg; + int bit; + int arg; + + switch (param) { + case PIN_CONFIG_INPUT_DEBOUNCE: + bit = debounce_bitnum(pin); + if (bit < 0) + return bit; + + arg = pinconf_to_config_argument(config); + + spin_lock_irqsave(&pctrl->lock, flags); + reg = ioread32(pctrl->gpio_base + WPCM450_GPEVDBNC); + __assign_bit(bit, ®, arg); + iowrite32(reg, pctrl->gpio_base + WPCM450_GPEVDBNC); + spin_unlock_irqrestore(&pctrl->lock, flags); + break; + default: + return -ENOTSUPP; + } + + return 0; +} + +static int wpcm450_config_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int num_configs) +{ + struct wpcm450_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + int ret; + + while (num_configs--) { + ret = wpcm450_config_set_one(pctrl, pin, *configs++); + if (ret) + return ret; + } + + return 0; +} + +static const struct pinconf_ops wpcm450_pinconf_ops = { + .is_generic = true, + .pin_config_get = wpcm450_config_get, + .pin_config_set = wpcm450_config_set, +}; + +static struct pinctrl_desc wpcm450_pinctrl_desc = { + .name = "wpcm450-pinctrl", + .pins = wpcm450_pins, + .npins = ARRAY_SIZE(wpcm450_pins), + .pctlops = &wpcm450_pinctrl_ops, + .pmxops = &wpcm450_pinmux_ops, + .confops = &wpcm450_pinconf_ops, + .owner = THIS_MODULE, +}; + +static int wpcm450_gpio_set_config(struct gpio_chip *chip, + unsigned int offset, unsigned long config) +{ + struct wpcm450_gpio *gpio = gpiochip_get_data(chip); + + return wpcm450_config_set_one(gpio->pctrl, offset, config); +} + +static int wpcm450_gpio_register(struct platform_device *pdev, + struct wpcm450_pinctrl *pctrl) +{ + int ret = 0; + struct fwnode_handle *np; + + pctrl->gpio_base = devm_platform_ioremap_resource(pdev, 0); + if (!pctrl->gpio_base) { + dev_err(pctrl->dev, "Resource fail for GPIO controller\n"); + return -ENOMEM; + } + + fwnode_for_each_available_child_node(pctrl->dev->fwnode, np) { + void __iomem *dat = NULL; + void __iomem *set = NULL; + void __iomem *dirout = NULL; + unsigned long flags = 0; + const struct wpcm450_bank *bank; + struct wpcm450_gpio *gpio; + struct gpio_irq_chip *girq; + u32 interrupt_map[3]; + int reg, i; + + if (!fwnode_property_read_bool(np, "gpio-controller")) + continue; + + ret = fwnode_property_read_u32(np, "reg", ®); + if (ret < 0) + return ret; + + gpio = &pctrl->gpio_bank[reg]; + gpio->pctrl = pctrl; + + if (reg < 0 || reg > WPCM450_NUM_BANKS) { + dev_err(pctrl->dev, "GPIO index %d out of range!\n", reg); + return -EINVAL; + } + + bank = &wpcm450_banks[reg]; + + dat = pctrl->gpio_base + bank->datain; + if (bank->dataout) { + set = pctrl->gpio_base + bank->dataout; + dirout = pctrl->gpio_base + bank->cfg0; + } else { + flags = BGPIOF_NO_OUTPUT; + } + ret = bgpio_init(&gpio->gc, pctrl->dev, 4, + dat, set, NULL, dirout, NULL, flags); + if (ret < 0) { + dev_err(pctrl->dev, "GPIO initialization failed: %d\n", ret); + return ret; + } + + gpio->gc.ngpio = bank->length; + gpio->gc.set_config = wpcm450_gpio_set_config; + gpio->gc.of_node = to_of_node(np); + gpio->gc.parent = pctrl->dev; + + gpio->irqc = wpcm450_gpio_irqchip; + girq = &gpio->gc.irq; + girq->chip = &gpio->irqc; + girq->parent_handler = wpcm450_gpio_irqhandler; + girq->parents = devm_kcalloc(pctrl->dev, WPCM450_NUM_GPIO_IRQS, + sizeof(*girq->parents), GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_bad_irq; + + girq->num_parents = 0; + for (i = 0; i < WPCM450_NUM_GPIO_IRQS; i++) { + int irq = fwnode_irq_get(np, i); + + if (irq < 0) + break; + + girq->parents[i] = irq; + girq->num_parents++; + } + + ret = fwnode_property_read_u32_array(np, "nuvoton,interrupt-map", + interrupt_map, ARRAY_SIZE(interrupt_map)); + if (ret == 0) { + gpio->first_irq_bit = interrupt_map[0]; + gpio->num_irqs = interrupt_map[1]; + gpio->first_irq_gpio = interrupt_map[2]; + } + + ret = devm_gpiochip_add_data(pctrl->dev, &gpio->gc, gpio); + if (ret) { + dev_err(pctrl->dev, "Failed to add GPIO chip: %d\n", ret); + return ret; + } + + ret = gpiochip_add_pin_range(&gpio->gc, dev_name(pctrl->dev), + 0, bank->base, bank->length); + if (ret) { + dev_err(pctrl->dev, "Failed to add pin range for GPIO bank %u\n", reg); + return ret; + } + } + + return 0; +} + +static int wpcm450_pinctrl_probe(struct platform_device *pdev) +{ + struct wpcm450_pinctrl *pctrl; + int ret; + + pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) + return -ENOMEM; + + pctrl->dev = &pdev->dev; + spin_lock_init(&pctrl->lock); + dev_set_drvdata(&pdev->dev, pctrl); + + pctrl->gcr_regmap = + syscon_regmap_lookup_by_compatible("nuvoton,wpcm450-gcr"); + if (IS_ERR(pctrl->gcr_regmap)) { + dev_err_probe(pctrl->dev, PTR_ERR(pctrl->gcr_regmap), + "Failed to find nuvoton,wpcm450-gcr\n"); + return PTR_ERR(pctrl->gcr_regmap); + } + + pctrl->pctldev = devm_pinctrl_register(&pdev->dev, + &wpcm450_pinctrl_desc, pctrl); + if (IS_ERR(pctrl->pctldev)) { + dev_err_probe(&pdev->dev, PTR_ERR(pctrl->pctldev), + "Failed to register pinctrl device\n"); + return PTR_ERR(pctrl->pctldev); + } + + ret = wpcm450_gpio_register(pdev, pctrl); + if (ret < 0) + return ret; + + return 0; +} + +static const struct of_device_id wpcm450_pinctrl_match[] = { + { .compatible = "nuvoton,wpcm450-pinctrl" }, + { } +}; +MODULE_DEVICE_TABLE(of, wpcm450_pinctrl_match); + +static struct platform_driver wpcm450_pinctrl_driver = { + .probe = wpcm450_pinctrl_probe, + .driver = { + .name = "wpcm450-pinctrl", + .of_match_table = wpcm450_pinctrl_match, + }, +}; +module_platform_driver(wpcm450_pinctrl_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Jonathan Neuschäfer "); +MODULE_DESCRIPTION("Nuvoton WPCM450 Pinctrl and GPIO driver"); From patchwork Tue Dec 7 21:08:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 1564918 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.a=rsa-sha256 header.s=badeba3b8450 header.b=V+apZi5Z; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4J7tL348jGz9sRK for ; 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Wed, 8 Dec 2021 08:09:20 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1638911339; bh=aJK3aYkTjoNYFomlmBvcJiDYDAbn3yEMMH9PnGcwh0Q=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=V+apZi5Z0+zV19MkjBbX4/XYTOQl0U/cArYg5ZMl2USooSis7W1dZIM6t29q3PxaU 3nsKTqAyfc7vmRwQla2ZFPhL/fu/1a25QQRUxjpku3eC8D7hBQurPrZFXvD47dY1zG 1ClI7t3t80QPe1TUohZ5J+ZtN9eRTG3iidqlZjnY= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([5.146.194.160]) by mail.gmx.net (mrgmx104 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MFsYx-1mmDeH3JKp-00HQoC; Tue, 07 Dec 2021 22:08:58 +0100 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 6/8] ARM: dts: wpcm450: Add pinctrl and GPIO nodes Date: Tue, 7 Dec 2021 22:08:21 +0100 Message-Id: <20211207210823.1975632-7-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211207210823.1975632-1-j.neuschaefer@gmx.net> References: <20211207210823.1975632-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:usq2/YSpx5wQW1MyCXV07rtFXO7Ivj8A7enhBPFJxzJs5IuTmaR ckAN38qm7/pxxiUpvfjpUuJCr9f46BPCSem0daz6ogwZy+o8mQsbHPabpmodHB6/3gHFrlj Cbhkc4cqWlOFsg2VLaQ8Ts1Sl00St4JleGysUjV4QoO7B2EArNlhdgc4Fp6onvhPewpa58C BfZEppyS9BkFrmPrDwGAQ== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1;V03:K0:MeXJvmA2qww=:tZZ1gd1d8hrBvKOxGmsN9d utbwS06se01yGQaIQ960mOinzwa7be0TWDBaN3Hrv8U7u6xjRNBy40V3Aa0df3It5Ebs76HNR PW1307ibCHkhxRIRyIuHquZ4MU7jPU2aW2fFcLbUPIEtf8a7+TaVzknR+oRw9lbAn+/iUwlYl gn+VVC6x5xFy3Je1x9JpKToY6ruyyLw1net/TWVpiqMSQf2coX8NWDwJxJeShLvqGUGe0tCnd 2dO63p6qGaP6yyd1tU0nDKNygRl+3lHxMF4i3HfkkVoyIQx//H6FMY3LehtuJEMpwrcsA/t6r 32BrA7BEEyD4sLP7fKMkwDBTwL6onoQOXtJnZxoFEZykOmWnU2o+XX32jEogr2sYXTcu1PUsZ BVwd7PfLGA9/tlCnv5cssGMRo8xE4OBCSboeffWq0yn4LOoDd4rIabYjKbPGIdDHVn85E3MSb inFBL+jDBzT75p+49eZmyCLcW0BKu/K3XM2CV9w/mEm56R9CDn/P0J3G//PIINDeewuS+Y9kN L4rhYoqboW+1MVLG1XwrZb3RfmnSZxR8gq55pFk51wJ4iI+kZO0NDm7Dwf3cTTVHh2ODQpgst e3frKGKXXRbo+/YUjGSbm+P5RJkxNw6pQSt9OpZHcP9s+rpq6zu0PJfLmgtNy78Jdcgf8EWf6 h+oesDOR4XBFBtJgcvlOJbx9EZU6pjFLWDVukBEuXLPDBQzzHOQVJNDDW3TME00AT4HKWXiK2 Oe2ojapzSCb1IGSEvhog8p+k5Swm45Ts5lx74KKqoFottJW5BHZORCqk4iIkg3uBsk5ph6bnm kXrDm2OsjUC7jZwSUmmwbJIs4XDi6WL9Wj6F0q4giJgx4jM2LuJ1NflsSgae6p2oUjH46YR0N hq9UHL4guNP55X11K0munVngAoS6qCx4C4FxtLRijTBJ3A5sf3fgk3YUOCdF9fLHfb9fb4CK/ o7fLQcsGXavKITDUeWxo2cfeCHf19Ag3K0+83XMQW2r7sfhomA5xh8AImjILM9F52mNdbJ17L eHbBHJvd8IR0bVyakxOP7wdXV0ruEwWv+EOFIYs6zLtIBfwl9sigGjKJ062eMNCcZwp5jaaFr ys8YtwUJKcgV8c= X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tomer Maimon , Linus Walleij , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Rob Herring , openbmc@lists.ozlabs.org Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" This patch adds the pin controller and GPIO banks to the devicetree for the WPCM450 SoC. Signed-off-by: Jonathan Neuschäfer Reviewed-by: Linus Walleij --- v2: - Move GPIO banks into subnodes - Add /alias/gpio* v1: - https://lore.kernel.org/lkml/20210602120329.2444672-7-j.neuschaefer@gmx.net/ --- arch/arm/boot/dts/nuvoton-wpcm450.dtsi | 74 ++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) -- 2.30.2 diff --git a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi index a17ee70085dd0..a795cc4128654 100644 --- a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi +++ b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi @@ -8,6 +8,17 @@ / { #address-cells = <1>; #size-cells = <1>; + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + gpio5 = &gpio5; + gpio6 = &gpio6; + gpio7 = &gpio7; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -77,5 +88,68 @@ aic: interrupt-controller@b8002000 { interrupt-controller; #interrupt-cells = <2>; }; + + pinctrl: pinctrl@b8003000 { + compatible = "nuvoton,wpcm450-pinctrl"; + reg = <0xb8003000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + gpio0: gpio@0 { + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH + 3 IRQ_TYPE_LEVEL_HIGH + 4 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + nuvoton,interrupt-map = <0 16 0>; + }; + + gpio1: gpio@1 { + reg = <1>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + nuvoton,interrupt-map = <16 2 8>; + }; + + gpio2: gpio@2 { + reg = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio3: gpio@3 { + reg = <3>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio4: gpio@4 { + reg = <4>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio5: gpio@5 { + reg = <5>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio6: gpio@6 { + reg = <6>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio7: gpio@7 { + reg = <7>; + gpio-controller; + #gpio-cells = <2>; + }; + }; }; }; From patchwork Tue Dec 7 21:08:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 1564922 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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secure) header.d=gmx.net header.i=@gmx.net header.a=rsa-sha256 header.s=badeba3b8450 header.b=T9lTMve6; dkim-atps=neutral X-Original-To: openbmc@lists.ozlabs.org Delivered-To: openbmc@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmx.net (client-ip=212.227.17.22; helo=mout.gmx.net; envelope-from=j.neuschaefer@gmx.net; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.a=rsa-sha256 header.s=badeba3b8450 header.b=T9lTMve6; dkim-atps=neutral Received: from mout.gmx.net (mout.gmx.net [212.227.17.22]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4J7tGD6r9Pz3bqS for ; Wed, 8 Dec 2021 08:09:24 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1638911340; bh=ydeSff7ARSMRyer2h0d+ysVTraGKpuyvVeQKsq5VJR8=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=T9lTMve6OGkkF88AplB53qlRFXm0fKHzFXSBQ31Wh1df1U2S9lX6m7sJrt9wly+Il 8V5sheFbKAstTJPkU6aRS0yIMaWlK0x7ZPvI8QvcWf5S54JHGnvzuKZLqiz32S++mo 67aku9rwTkRp2b3kinXk7fWoiRzkNxTa6p42Dza8= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([5.146.194.160]) by mail.gmx.net (mrgmx105 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MLzBp-1nBxRS3hRZ-00Hsmq; Tue, 07 Dec 2021 22:08:59 +0100 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 7/8] ARM: dts: wpcm450: Add pin functions Date: Tue, 7 Dec 2021 22:08:22 +0100 Message-Id: <20211207210823.1975632-8-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211207210823.1975632-1-j.neuschaefer@gmx.net> References: <20211207210823.1975632-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:xPSju/tOW5OV/wGSkbiyijYM7IDYw6LltJqtBLSOpIeyTa3NxH3 vmF73ZHXxWgqfbe5IJXq/qNtkv47ZHdamDZFg+MoGzxfe63imFGEr4EVPMTy98HnQXfWkwf c6HnOWa51B2hYSUWjWlky7B4Wv39yDzrkwL2YZkTNTMu2CD3teyYnfu30nCRenZ5ZFn2lcH mRwsS4aTaq0XtJtXE2nYQ== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1;V03:K0:gSo5a5iquJs=:x76q+v18WI3JdeYPsXy5v8 H5FLcwMYpCG0UIvazeDFddTZD04vnUWWb78gYsDC7qVjnPckQbAqPMWdzhWzLtBF9t2LIX0zs dcAkzrWnwARrwgdUYg5GQxsKYzwr4J8z11Wss0C7SNGpWwB9X0Oodrj44GThgotPiqruY3Ona sX6czn1vCImfsqcFd9SpwWl+6We+v8lKcwvIKyBlwU9pyTQNB7N9lAQs7KwYAoonr0hJu1EeO +jV7GwK4z4CRMi0ZUZv9lXaeqkJ9thrP0YdSPFxbQR8dSNWhTTGY9WgOBwHCKqTDvyMslxETM T/s29MaiyMsfrCBJ/WmCPqdaMWDbsq6gyFL+lhxEmbOhGj4zTC5CYkRMzfmD54gci0MZh9B0O 5QcDWqXg0bf9VeqPoQd06NtFNGZLUVws16gh0jCyu/0anNA//kdnYhHoR1fxrKNM5OTsznqeC bdCaRfR7kfpchfAXuuwidfRGA1kDvifbxT5Y94xwK4C8yiZqbM1agapPwGr780P+lo2NQqXC0 8uqY99WRDL7M/pKqUzeziJ7qlPx8bdz1p6nKqPRO3TBa0wQirfXnFAvgCl8MH+GJP0yO5mpST FN3XcXwYJ9rlWzSq5A0VZr3f9CVgQBLEyBmsUcKwMVmpkFyULfA5idtiJDmUOdZZxB1CMt9sM GcavnR/0rVgGiKh2RKMXk2pqF9zBjsbVUd9P2BLXMj5utG9zNXprxtf2gQzjHqRzx21bRHUFQ Xjhrs8lpczYioZqAxCyPc+/hvNw9zMl/o6EOSxgK2zP3djhLAwfGE9m354vYHV66sJyQ9tNcu X/HvtAihJKs2uwLcb/fB2eGpC1TWZmLkRndVvJ+l3SuYc4YMEa/TDiDP+qky9RY2L28itr7Xg K3UCXtNWMtIccGyfxRxnsT0yG6A46U3telvCzMjOz4PZQ++wNXkfWvEEKRhXf+Sh+/+NvaMdy 0Xhrpqu0NtWQyCPHMlz1Z+vtfpxCLH8p7Rf6HLbwoGA0lqbjJ8wQEWm328HV9nhkB0M72Wm6b 7OI9SqiWCT5B4E5e4oDQ3kwuL4UFSIU50RJBlWJ/zDFmh6tW+cCKRCYATzjqc4Jge8nmoRYzP JqxVSfc+zxM+Wg= X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tomer Maimon , Linus Walleij , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Rob Herring , openbmc@lists.ozlabs.org Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" As done in nuvoton-common-npcm7xx.dtsi, this patch adds pinmux nodes for all pin functions to nuvoton-wpcm450.dtsi. Signed-off-by: Jonathan Neuschäfer --- I'm not quite convinced of the value of this patch, as the pin functions could easily be specified in board.dts files when needed. v2: - no changes v1: - https://lore.kernel.org/lkml/20210602120329.2444672-8-j.neuschaefer@gmx.net/ --- arch/arm/boot/dts/nuvoton-wpcm450.dtsi | 305 +++++++++++++++++++++++++ 1 file changed, 305 insertions(+) -- 2.30.2 diff --git a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi index a795cc4128654..b377e61714bcb 100644 --- a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi +++ b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi @@ -150,6 +150,311 @@ gpio7: gpio@7 { gpio-controller; #gpio-cells = <2>; }; + + smb3_pins: smb3-pins { + groups = "smb3"; + function = "smb3"; + }; + + smb4_pins: smb4-pins { + groups = "smb4"; + function = "smb4"; + }; + + smb5_pins: smb5-pins { + groups = "smb5"; + function = "smb5"; + }; + + scs1_pins: scs1-pins { + groups = "scs1"; + function = "scs1"; + }; + + scs2_pins: scs2-pins { + groups = "scs2"; + function = "scs2"; + }; + + scs3_pins: scs3-pins { + groups = "scs3"; + function = "scs3"; + }; + + smb0_pins: smb0-pins { + groups = "smb0"; + function = "smb0"; + }; + + smb1_pins: smb1-pins { + groups = "smb1"; + function = "smb1"; + }; + + smb2_pins: smb2-pins { + groups = "smb2"; + function = "smb2"; + }; + + bsp_pins: bsp-pins { + groups = "bsp"; + function = "bsp"; + }; + + hsp1_pins: hsp1-pins { + groups = "hsp1"; + function = "hsp1"; + }; + + hsp2_pins: hsp2-pins { + groups = "hsp2"; + function = "hsp2"; + }; + + r1err_pins: r1err-pins { + groups = "r1err"; + function = "r1err"; + }; + + r1md_pins: r1md-pins { + groups = "r1md"; + function = "r1md"; + }; + + rmii2_pins: rmii2-pins { + groups = "rmii2"; + function = "rmii2"; + }; + + r2err_pins: r2err-pins { + groups = "r2err"; + function = "r2err"; + }; + + r2md_pins: r2md-pins { + groups = "r2md"; + function = "r2md"; + }; + + kbcc_pins: kbcc-pins { + groups = "kbcc"; + function = "kbcc"; + }; + + dvo0_pins: dvo0-pins { + groups = "dvo"; + function = "dvo0"; + }; + + dvo3_pins: dvo3-pins { + groups = "dvo"; + function = "dvo3"; + }; + + clko_pins: clko-pins { + groups = "clko"; + function = "clko"; + }; + + smi_pins: smi-pins { + groups = "smi"; + function = "smi"; + }; + + uinc_pins: uinc-pins { + groups = "uinc"; + function = "uinc"; + }; + + gspi_pins: gspi-pins { + groups = "gspi"; + function = "gspi"; + }; + + mben_pins: mben-pins { + groups = "mben"; + function = "mben"; + }; + + xcs2_pins: xcs2-pins { + groups = "xcs2"; + function = "xcs2"; + }; + + xcs1_pins: xcs1-pins { + groups = "xcs1"; + function = "xcs1"; + }; + + sdio_pins: sdio-pins { + groups = "sdio"; + function = "sdio"; + }; + + sspi_pins: sspi-pins { + groups = "sspi"; + function = "sspi"; + }; + + fi0_pins: fi0-pins { + groups = "fi0"; + function = "fi0"; + }; + + fi1_pins: fi1-pins { + groups = "fi1"; + function = "fi1"; + }; + + fi2_pins: fi2-pins { + groups = "fi2"; + function = "fi2"; + }; + + fi3_pins: fi3-pins { + groups = "fi3"; + function = "fi3"; + }; + + fi4_pins: fi4-pins { + groups = "fi4"; + function = "fi4"; + }; + + fi5_pins: fi5-pins { + groups = "fi5"; + function = "fi5"; + }; + + fi6_pins: fi6-pins { + groups = "fi6"; + function = "fi6"; + }; + + fi7_pins: fi7-pins { + groups = "fi7"; + function = "fi7"; + }; + + fi8_pins: fi8-pins { + groups = "fi8"; + function = "fi8"; + }; + + fi9_pins: fi9-pins { + groups = "fi9"; + function = "fi9"; + }; + + fi10_pins: fi10-pins { + groups = "fi10"; + function = "fi10"; + }; + + fi11_pins: fi11-pins { + groups = "fi11"; + function = "fi11"; + }; + + fi12_pins: fi12-pins { + groups = "fi12"; + function = "fi12"; + }; + + fi13_pins: fi13-pins { + groups = "fi13"; + function = "fi13"; + }; + + fi14_pins: fi14-pins { + groups = "fi14"; + function = "fi14"; + }; + + fi15_pins: fi15-pins { + groups = "fi15"; + function = "fi15"; + }; + + pwm0_pins: pwm0-pins { + groups = "pwm0"; + function = "pwm0"; + }; + + pwm1_pins: pwm1-pins { + groups = "pwm1"; + function = "pwm1"; + }; + + pwm2_pins: pwm2-pins { + groups = "pwm2"; + function = "pwm2"; + }; + + pwm3_pins: pwm3-pins { + groups = "pwm3"; + function = "pwm3"; + }; + + pwm4_pins: pwm4-pins { + groups = "pwm4"; + function = "pwm4"; + }; + + pwm5_pins: pwm5-pins { + groups = "pwm5"; + function = "pwm5"; + }; + + pwm6_pins: pwm6-pins { + groups = "pwm6"; + function = "pwm6"; + }; + + pwm7_pins: pwm7-pins { + groups = "pwm7"; + function = "pwm7"; + }; + + hg0_pins: hg0-pins { + groups = "hg0"; + function = "hg0"; + }; + + hg1_pins: hg1-pins { + groups = "hg1"; + function = "hg1"; + }; + + hg2_pins: hg2-pins { + groups = "hg2"; + function = "hg2"; + }; + + hg3_pins: hg3-pins { + groups = "hg3"; + function = "hg3"; + }; + + hg4_pins: hg4-pins { + groups = "hg4"; + function = "hg4"; + }; + + hg5_pins: hg5-pins { + groups = "hg5"; + function = "hg5"; + }; + + hg6_pins: hg6-pins { + groups = "hg6"; + function = "hg6"; + }; + + hg7_pins: hg7-pins { + groups = "hg7"; + function = "hg7"; + }; }; }; }; From patchwork Tue Dec 7 21:08:23 2021 Content-Type: text/plain; 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Wed, 8 Dec 2021 08:09:24 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1638911341; bh=n/IMLw8RlRNMl11ZPwUHyr0pgPADtPhByeB9Tw0skmg=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=FNRyavxNkzUybVYlqRDiUBF4KqPm+OMZ0TK9Q76YZWrZ9TS/zwjSQA3TJ28xp4wkU ZUjZXZqX+VWJv+xzSLgZPBdMdEOzHn28a5ncFmL4tW3tsflrdfgk4cKy+1uqOE4kBZ uD4izYA8RmvKAIyi1IDINzq3RFEiShnmjHBezw0c= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([5.146.194.160]) by mail.gmx.net (mrgmx104 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MV63q-1n1ogk3gJy-00S6Qt; Tue, 07 Dec 2021 22:09:00 +0100 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 8/8] ARM: dts: wpcm450-supermicro-x9sci-ln4f: Add GPIO LEDs and buttons Date: Tue, 7 Dec 2021 22:08:23 +0100 Message-Id: <20211207210823.1975632-9-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211207210823.1975632-1-j.neuschaefer@gmx.net> References: <20211207210823.1975632-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:w6zd2sE7qX7biDctX7/3wm69kxDwHCnk4KmUNJeio84MbEdf15g Nk4DGNQcIQZwB1WFZSh9/PQx+THVkVtuSTVWUOPwXdu90s3phD3XLmM7j3Z699COuz29WVL Cmegvh5QaJaHEs5/Gu0uKZQDHMBVmO8vmA0V439F55aZdyJdJpT5iUq6gWiNrp2G2WviA9v 3xVbF/GMsHJQpPfU/V+GQ== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1;V03:K0:bRTl+6Zn8hA=:cOkpSHY7Gl7GjEPQmOCJqG 7B3+v1lKhy9tm0z++wILvQcoyNzdflutetAfJ+8UthJc0bvDoROUhnzTQZEGCyNmWMotgMqjf zR6IqqP0rwACE2ZgvuSCIdu4yGHfO83ypsWwArlQVupPUNgqZpZhZFBfkqDlmHrai0XcK7+Bl 88YlBbmdnciBXstf3UougA7U6aAU1n7YqJsfpa1QgytE4aEjXSpbX2BP/NCWHYX9XE70R2xZD v9B8xdr+sysQgbWbVi+SbPylQd89Zm27Ss/xXifhtI+Zv6Ym8Vqy8mrOw45p7dd/QFJ23cIUy qUtLya324sAK+1BA1LIWk3DS/K+hV21ZqXQjsXguOMw90N5mldFtJye8NrGxIGi5lTGTeX/9A ruT5eZnDHlpfkoJVgS8Faa9snuAWJcuwXcXOw78j18UnP5JXydLkLxiv3ZUS2fHRXFq+H6ixp HVUb8Oc0vuhH/TDVv919SdnSfIGZNPntjcKEeZd8Affjr7BBeraZtbj2ZFa2C+XC0012qJpYF fgF13H78PgCU+aTBCrmiDPqhfiiipJ3rIRXf/xWSm5Kpz7krCZ0GoHTNbGMX/gOellWYg17U5 Ouvt7PlOr3Beitp0EzQOxHPaEx+ufSxELv5wdYYJHNhZWM2I8xfvEqRJTn8XU5nL82Hof1YDl o4Ebxzd2mDLadUxRsMG6SOrFMMhN9pz74GmYfIAWGkJl0RlYfPSHXtkKxQ3TB41ojil8e31KZ XoAp3vOIxChIPynhhaWrY7uxYn/fivj34AtOIEI9hz9jl9pvusUK2d2mQ6fNTzLnYggD/jkWS AXHWJZ5SMMNDTlcc2HeR5y39fBmf8fOnjc/WP70R9vFHqwctQqg6Npg7RA+0xmH/RnN5rZbvl qj/KmdhhinGrPfvNXbYKuPPJhMyh5gNV+m5f4iuOA50TcLvyBXLKzFyFDsVeXPA49dLs7yPGx JNTNwhGdh1Fo3wsDEBHH4iwl5Vxc6fkYOi0XiHjxoT0e6SICMiB5dVa55Qm3Sp6fQUKjQFbEo SPyIs3tEHCxtwbmy2P312zYJDleF+0es0kt40jaVbSrvGhWXLcPnUauGkyXfWwfA7j8ENrPdF CID38zHhZk82tU= X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tomer Maimon , Linus Walleij , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Rob Herring , openbmc@lists.ozlabs.org Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" The Supermicro X9SCi-LN4F server mainboard has a two LEDs and a button under the control of the BMC. This patch makes them accessible under Linux running on the BMC. Signed-off-by: Jonathan Neuschäfer --- v2: - Adjust to new GPIO controller names - Explicitly set pinmux to GPIO for GPIO keys and LEDs v1: - https://lore.kernel.org/lkml/20210602120329.2444672-9-j.neuschaefer@gmx.net/ --- .../nuvoton-wpcm450-supermicro-x9sci-ln4f.dts | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) -- 2.30.2 diff --git a/arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts b/arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts index 83f27fbf4e939..cd8d3a6bbf853 100644 --- a/arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts +++ b/arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts @@ -8,6 +8,9 @@ #include "nuvoton-wpcm450.dtsi" +#include +#include + / { model = "Supermicro X9SCi-LN4F BMC"; compatible = "supermicro,x9sci-ln4f-bmc", "nuvoton,wpcm450"; @@ -20,6 +23,46 @@ memory@0 { device_type = "memory"; reg = <0 0x08000000>; /* 128 MiB */ }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key_pins>; + + uid { + label = "UID button"; + linux,code = ; + gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + uid { + label = "UID"; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + }; + + heartbeat { + label = "heartbeat"; + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&pinctrl { + key_pins: mux_keys { + groups = "gspi", "sspi"; + function = "gpio"; + }; + + led_pins: mux_leds { + groups = "hg3", "hg0", "pwm4"; + function = "gpio"; + }; }; &serial0 {