From patchwork Thu Nov 4 09:55:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Andre Vieira (lists)" X-Patchwork-Id: 1550837 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=HKty5mvX; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4HlJvS0CSBz9sPf for ; Thu, 4 Nov 2021 20:56:50 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 80A76385802E for ; Thu, 4 Nov 2021 09:56:47 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 80A76385802E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1636019807; bh=WF4u+Z21aQvE659GXW9PccG4hK28dM4BZQZHSnnFSYk=; h=Date:To:Subject:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=HKty5mvXqYgYVWdQCtVbUNpe90KuxtSjTWCWE60zpSktSMzt53djimtFbJ6ouSSNy 9K55C4vO5r2C868GoUPmPubSHabl7GuTJHwXZ4FPuuoGwTcPb5bwGd+H8GkKiaj7US dGq/IM7CMEKR6y/Hg6Y0LEguydedGhNL4F9ofXiY= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 99524385841C for ; Thu, 4 Nov 2021 09:55:40 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 99524385841C Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3DA821063; Thu, 4 Nov 2021 02:55:40 -0700 (PDT) Received: from [10.57.26.38] (unknown [10.57.26.38]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 363CC3F719; Thu, 4 Nov 2021 02:55:39 -0700 (PDT) Message-ID: <0911f6c6-7832-026c-36c1-cbb576944a62@arm.com> Date: Thu, 4 Nov 2021 09:55:37 +0000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.2.1 Content-Language: en-US To: Richard Sandiford , Kyrylo Tkachov , "gcc-patches@gcc.gnu.org" Subject: [AArch64] Fix NEON load/store gimple lowering and big-endian testisms X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, BODY_8BITS, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_LOTSOFHASH, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "Andre Vieira \(lists\) via Gcc-patches" From: "Andre Vieira (lists)" Reply-To: "Andre Vieira \(lists\)" Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Hi, This should address the ubsan bootstrap build and big-endian testisms reported against the last NEON load/store gimple lowering patch. I also fixed a follow-up issue where the alias information was leading to a bad codegen transformation. The NEON intrinsics specifications do not forbid the use of memory accesses with different pointer types. In fact you will see intrinsic user code loading a int16x8_t vector from an int pointer, so we must make sure GCC is aware a NEON memory access of an 'int' pointer can alias with a 'short' pointer. Bootstrapped aarch64-linux-gnu (also did an ubsan bootstrap). Is this OK for trunk? gcc/ChangeLog:         * config/aarch64/aarch64-builtins.c (aarch64_general_gimple_fold_builtin): Change pointer alignment and alias. gcc/testsuite/ChangeLog:         * gcc.target/aarch64/fmla_intrinsic_1.c: Fix big-endian testism.         * gcc.target/aarch64/fmls_intrinsic_1.c: Likewise.         * gcc.target/aarch64/fmul_intrinsic_1.c: Likewise. diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c index a815e4cfbccab692ca688ba87c71b06c304abbfb..fc8fcb02c55e22963d2a3bf77b4749eb5b1c1561 100644 --- a/gcc/config/aarch64/aarch64-builtins.c +++ b/gcc/config/aarch64/aarch64-builtins.c @@ -2486,16 +2486,22 @@ aarch64_general_gimple_fold_builtin (unsigned int fcode, gcall *stmt, aarch64_simd_type_info simd_type = aarch64_simd_types[mem_type]; tree elt_ptr_type = build_pointer_type (simd_type.eltype); + elt_ptr_type = build_distinct_type_copy (elt_ptr_type); + TYPE_REF_CAN_ALIAS_ALL (elt_ptr_type) = true; tree zero = build_zero_cst (elt_ptr_type); gimple_seq stmts = NULL; tree base = gimple_convert (&stmts, elt_ptr_type, args[0]); + /* Use element type alignment. */ + tree access_type + = build_aligned_type (simd_type.itype, + TYPE_ALIGN (TREE_TYPE (simd_type.itype))); if (stmts) gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); new_stmt = gimple_build_assign (gimple_get_lhs (stmt), fold_build2 (MEM_REF, - simd_type.itype, + access_type, base, zero)); } break; @@ -2508,17 +2514,22 @@ aarch64_general_gimple_fold_builtin (unsigned int fcode, gcall *stmt, aarch64_simd_type_info simd_type = aarch64_simd_types[mem_type]; tree elt_ptr_type = build_pointer_type (simd_type.eltype); + elt_ptr_type = build_distinct_type_copy (elt_ptr_type); + TYPE_REF_CAN_ALIAS_ALL (elt_ptr_type) = true; tree zero = build_zero_cst (elt_ptr_type); gimple_seq stmts = NULL; tree base = gimple_convert (&stmts, elt_ptr_type, args[0]); + /* Use element type alignment. */ + tree access_type + = build_aligned_type (simd_type.itype, + TYPE_ALIGN (TREE_TYPE (simd_type.itype))); if (stmts) gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); new_stmt - = gimple_build_assign (fold_build2 (MEM_REF, - simd_type.itype, - base, - zero), args[1]); + = gimple_build_assign (fold_build2 (MEM_REF, access_type, + base, zero), + args[1]); } break; diff --git a/gcc/testsuite/gcc.target/aarch64/fmla_intrinsic_1.c b/gcc/testsuite/gcc.target/aarch64/fmla_intrinsic_1.c index adb787a8599af23847dd62dcd153d7cfe43dacc0..c1aeb06e74753052c2ee441b361b92148f1b4b0a 100644 --- a/gcc/testsuite/gcc.target/aarch64/fmla_intrinsic_1.c +++ b/gcc/testsuite/gcc.target/aarch64/fmla_intrinsic_1.c @@ -107,10 +107,12 @@ main (int argc, char **argv) /* vfma_lane_f64. vfma_laneq_f64. */ -/* { dg-final { scan-assembler-times "fmadd\\td\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler-times "fmadd\\td\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+" 1 { target aarch64_big_endian } } } */ +/* { dg-final { scan-assembler-times "fmadd\\td\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+" 2 { target aarch64_little_endian } } } */ /* vfmaq_lane_f64. vfmaq_laneq_f64. */ -/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.d\\\[\[0-9\]+\\\]" 2 } } */ +/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.d\\\[\[0-9\]+\\\]" 3 { target aarch64_big_endian } } } */ +/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.d\\\[\[0-9\]+\\\]" 2 { target aarch64_little_endian } } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/fmls_intrinsic_1.c b/gcc/testsuite/gcc.target/aarch64/fmls_intrinsic_1.c index 865def28c3f4d04042ab495d232bb865cabb2b50..3137ea91e809e37de589091e9bbd43bfe4d221a1 100644 --- a/gcc/testsuite/gcc.target/aarch64/fmls_intrinsic_1.c +++ b/gcc/testsuite/gcc.target/aarch64/fmls_intrinsic_1.c @@ -108,10 +108,12 @@ main (int argc, char **argv) /* vfms_lane_f64. vfms_laneq_f64. */ -/* { dg-final { scan-assembler-times "fmsub\\td\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler-times "fmsub\\td\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+" 1 { target aarch64_big_endian } } } */ +/* { dg-final { scan-assembler-times "fmsub\\td\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+" 2 { target aarch64_little_endian } } } */ /* vfmsq_lane_f64. vfmsq_laneq_f64. */ -/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.d\\\[\[0-9\]+\\\]" 2 } } */ +/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.d\\\[\[0-9\]+\\\]" 3 { target aarch64_big_endian } } } */ +/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.d\\\[\[0-9\]+\\\]" 2 { target aarch64_little_endian } } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/fmul_intrinsic_1.c b/gcc/testsuite/gcc.target/aarch64/fmul_intrinsic_1.c index d01095e81c1e45dc1da998aa337ba551b3752ebe..7d4829c40d7042226f2f09fab9fdfa7c3dd211c4 100644 --- a/gcc/testsuite/gcc.target/aarch64/fmul_intrinsic_1.c +++ b/gcc/testsuite/gcc.target/aarch64/fmul_intrinsic_1.c @@ -107,10 +107,12 @@ main (int argc, char **argv) /* vmul_lane_f64. Vmul_laneq_f64. */ -/* { dg-final { scan-assembler-times "fmul\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler-times "fmul\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 { target aarch64_big_endian } } } */ +/* { dg-final { scan-assembler-times "fmul\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 2 { target aarch64_little_endian } } } */ /* vmulq_lane_f64. vmulq_laneq_f64. */ -/* { dg-final { scan-assembler-times "fmul\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.d\\\[\[0-9\]+\\\]" 2 } } */ +/* { dg-final { scan-assembler-times "fmul\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.d\\\[\[0-9\]+\\\]" 3 { target aarch64_big_endian } } } */ +/* { dg-final { scan-assembler-times "fmul\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.d\\\[\[0-9\]+\\\]" 2 { target aarch64_little_endian } } } */