From patchwork Mon Oct 25 17:16:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 1545861 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=LKclu6Sa; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4HdM8B68d2z9tjx for ; Tue, 26 Oct 2021 04:17:14 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231686AbhJYRTg (ORCPT ); Mon, 25 Oct 2021 13:19:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51232 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231802AbhJYRTf (ORCPT ); Mon, 25 Oct 2021 13:19:35 -0400 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3331EC061745 for ; Mon, 25 Oct 2021 10:17:13 -0700 (PDT) Received: by mail-wr1-x42c.google.com with SMTP id v17so12829888wrv.9 for ; Mon, 25 Oct 2021 10:17:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0sqozBq+aXNpDnMO1F1fpUtm2LewFLxPBuJo7vey+3c=; b=LKclu6SaBqhTgfIomva1urEsQC7HK41HTgVlE4kwot0qJTvGeMcVlVPQLU4LQyazha oNfSFuchFvtCYXVFwWCCEI02XvG+EVcm1A+y2mCvZvVx/yBfaIrtZxWEP/5KQOrf/yqR ohDPDi3/DPlLYWm3IWqDBHUdTq2Lh7Obz+bo4rjKBNzwKFmmmyYcl82m0+jOVoJlFTZN hCwLRxNYchwuWlUtC0bCDMox8YfBFctk+Zu404GVZ02iOIVjBDnjZbBBEBUkcX1vQCxC mInJqpo51VhgLAdWer0ZFZDIUWRHlo3fqhX8OXHkOJYMHGGUKcpmVmnqW3LM/qV27okC u0bg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0sqozBq+aXNpDnMO1F1fpUtm2LewFLxPBuJo7vey+3c=; b=M/T8Ne9D8PO5TZ+vMW7OKwapfw4H2sZz+hmCcEWEQBRaizJ8D/FMuhVpiFrJWmTavN H3+3VPy7q50n0onKTvBEzBHOFTStqevy04aFkZbhspQjquqGP6aYRc2LUdYtVXVYEeer jt/J0b6pLA2r3Z8fuxtLmbCap6LY9TR7yxex7O3PBXFSUwdzjuKiasJw518iaRJmq6fm 3ktpu38YuMYuyuPS3lBHoGynGtlv7WAX3LAz9MQuB4i1dp6Rujw58SCxA4UZTKLx4mYt wCy74KQzOITe8Ui5SpCgiqOMl9tMtu21Zp81YkMjvzXs02j6LTcBVNACBHlpTIwESmB6 PKNg== X-Gm-Message-State: AOAM533YP8Rn2E2x3dIvuIANER0QWhDqwt2jz/dNgXwxuF9VqSVvVlxA +YlY7K5j7gXLmv3FQgcAXrJQhg== X-Google-Smtp-Source: ABdhPJz3bpjZhDyhWe1dzyBfIY5pNqjiRvc6PQoJSMRO0cS1RD5XGbNeieCgYhPK8Lq141Wpy5DjHA== X-Received: by 2002:a5d:6941:: with SMTP id r1mr13478593wrw.373.1635182231744; Mon, 25 Oct 2021 10:17:11 -0700 (PDT) Received: from srini-hackbox.lan (cpc86377-aztw32-2-0-cust226.18-1.cable.virginm.net. [92.233.226.227]) by smtp.gmail.com with ESMTPSA id r11sm5181012wrt.42.2021.10.25.10.17.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Oct 2021 10:17:11 -0700 (PDT) From: Srinivas Kandagatla To: broonie@kernel.org, bjorn.andersson@linaro.org, robh@kernel.org Cc: plai@codeaurora.org, pierre-louis.bossart@linux.intel.com, tiwai@suse.de, devicetree@vger.kernel.org, perex@perex.cz, alsa-devel@alsa-project.org, lgirdwood@gmail.com, bgoswami@codeaurora.org, Srinivas Kandagatla Subject: [PATCH v10 01/17] ASoC: dt-bindings: move LPASS dai related bindings out of q6afe Date: Mon, 25 Oct 2021 18:16:33 +0100 Message-Id: <20211025171649.17730-2-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20211025171649.17730-1-srinivas.kandagatla@linaro.org> References: <20211025171649.17730-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org q6afe (Audio Front End) is one of the DSP service that handles both LPASS (Low Power Audio SubSystem) Audio ports and LPASS clocks. As LPASS is a hardwware IP and commonly used by Qualcomm Audio DSP. In order to allow multiple DSP frameworks to use these bindings its best to move it out from the dsp specific bindings. For compatibility reasons and not breaking which is already working we still maintain same compatible string "qcom,q6afe-dais" Also as part of this change convert these LPASS dai related bindings into yaml format. Signed-off-by: Srinivas Kandagatla Reviewed-by: Rob Herring --- .../devicetree/bindings/sound/qcom,q6afe.txt | 158 ---------------- .../sound/qcom,q6dsp-lpass-ports.yaml | 178 ++++++++++++++++++ 2 files changed, 178 insertions(+), 158 deletions(-) create mode 100644 Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml diff --git a/Documentation/devicetree/bindings/sound/qcom,q6afe.txt b/Documentation/devicetree/bindings/sound/qcom,q6afe.txt index 1677448347da..fcf81058504c 100644 --- a/Documentation/devicetree/bindings/sound/qcom,q6afe.txt +++ b/Documentation/devicetree/bindings/sound/qcom,q6afe.txt @@ -12,92 +12,6 @@ used by all apr services. Must contain the following properties. from DSP. example "qcom,q6afe" -= AFE DAIs (Digital Audio Interface) -"dais" subnode of the AFE node. It represents afe dais, each afe dai is a -subnode of "dais" representing board specific dai setup. -"dais" node should have following properties followed by dai children. - -- compatible: - Usage: required - Value type: - Definition: must be "qcom,q6afe-dais" - -- #sound-dai-cells - Usage: required - Value type: - Definition: Must be 1 - -- #address-cells - Usage: required - Value type: - Definition: Must be 1 - -- #size-cells - Usage: required - Value type: - Definition: Must be 0 - -== AFE DAI is subnode of "dais" and represent a dai, it includes board specific -configuration of each dai. Must contain the following properties. - -- reg - Usage: required - Value type: - Definition: Must be dai id - -- qcom,sd-lines - Usage: required for mi2s interface - Value type: - Definition: Must be list of serial data lines used by this dai. - should be one or more of the 0-3 sd lines. - - - qcom,tdm-sync-mode: - Usage: required for tdm interface - Value type: - Definition: Synchronization mode. - 0 - Short sync bit mode - 1 - Long sync mode - 2 - Short sync slot mode - - - qcom,tdm-sync-src: - Usage: required for tdm interface - Value type: - Definition: Synchronization source. - 0 - External source - 1 - Internal source - - - qcom,tdm-data-out: - Usage: required for tdm interface - Value type: - Definition: Data out signal to drive with other masters. - 0 - Disable - 1 - Enable - - - qcom,tdm-invert-sync: - Usage: required for tdm interface - Value type: - Definition: Invert the sync. - 0 - Normal - 1 - Invert - - - qcom,tdm-data-delay: - Usage: required for tdm interface - Value type: - Definition: Number of bit clock to delay data - with respect to sync edge. - 0 - 0 bit clock cycle - 1 - 1 bit clock cycle - 2 - 2 bit clock cycle - - - qcom,tdm-data-align: - Usage: required for tdm interface - Value type: - Definition: Indicate how data is packed - within the slot. For example, 32 slot width in case of - sample bit width is 24. - 0 - MSB - 1 - LSB - = AFE CLOCKSS "clocks" subnode of the AFE node. It represents q6afe clocks "clocks" node should have following properties. @@ -122,78 +36,6 @@ apr-service@4 { compatible = "qcom,q6afe"; reg = ; - dais { - compatible = "qcom,q6afe-dais"; - #sound-dai-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - dai@1 { - reg = ; - }; - - dai@24 { - reg = ; - qcom,tdm-sync-mode = <1>: - qcom,tdm-sync-src = <1>; - qcom,tdm-data-out = <0>; - qcom,tdm-invert-sync = <1>; - qcom,tdm-data-delay = <1>; - qcom,tdm-data-align = <0>; - - }; - - dai@25 { - reg = ; - qcom,tdm-sync-mode = <1>: - qcom,tdm-sync-src = <1>; - qcom,tdm-data-out = <0>; - qcom,tdm-invert-sync = <1>; - qcom,tdm-data-delay <1>: - qcom,tdm-data-align = <0>; - }; - - dai@16 { - reg = ; - qcom,sd-lines = <0 2>; - }; - - dai@17 { - reg = ; - qcom,sd-lines = <1>; - }; - - dai@18 { - reg = ; - qcom,sd-lines = <0 3>; - }; - - dai@19 { - reg = ; - qcom,sd-lines = <1>; - }; - - dai@20 { - reg = ; - qcom,sd-lines = <1 3>; - }; - - dai@21 { - reg = ; - qcom,sd-lines = <0>; - }; - - dai@22 { - reg = ; - qcom,sd-lines = <0>; - }; - - dai@23 { - reg = ; - qcom,sd-lines = <1>; - }; - }; - clocks { compatible = "qcom,q6afe-clocks"; #clock-cells = <2>; diff --git a/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml b/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml new file mode 100644 index 000000000000..e6148c17419b --- /dev/null +++ b/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml @@ -0,0 +1,178 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/sound/qcom,q6dsp-lpass-ports.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm DSP LPASS(Low Power Audio SubSystem) Audio Ports binding + +maintainers: + - Srinivas Kandagatla + +description: | + This binding describes the Qualcomm DSP LPASS Audio ports + +properties: + compatible: + enum: + - qcom,q6afe-dais + + reg: + maxItems: 1 + + '#sound-dai-cells': + const: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +#Digital Audio Interfaces +patternProperties: + '^dai@[0-9]+$': + type: object + description: + Q6DSP Digital Audio Interfaces. + + properties: + reg: + description: + Digital Audio Interface ID + + qcom,sd-lines: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + List of serial data lines used by this dai.should be one or more of the 0-3 sd lines. + minItems: 1 + maxItems: 4 + uniqueItems: true + items: + minimum: 0 + maximum: 3 + + qcom,tdm-sync-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + description: + TDM Synchronization mode + 0 = Short sync bit mode + 1 = Long sync mode + 2 = Short sync slot mode + + qcom,tdm-sync-src: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: + TDM Synchronization source + 0 = External source + 1 = Internal source + + qcom,tdm-data-out: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: + TDM Data out signal to drive with other masters + 0 = Disable + 1 = Enable + + qcom,tdm-invert-sync: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: + TDM Invert the sync + 0 = Normal + 1 = Invert + + qcom,tdm-data-delay: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + description: + TDM Number of bit clock to delay data + 0 = 0 bit clock cycle + 1 = 1 bit clock cycle + 2 = 2 bit clock cycle + + qcom,tdm-data-align: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: + Indicate how data is packed within the slot. For example, 32 slot + width in case of sample bit width is 24TDM Invert the sync. + 0 = MSB + 1 = LSB + + required: + - reg + + allOf: + - if: + properties: + reg: + contains: + # TDM DAI ID range from PRIMARY_TDM_RX_0 - QUINARY_TDM_TX_7 + items: + minimum: 24 + maximum: 103 + then: + required: + - qcom,tdm-sync-mode + - qcom,tdm-sync-src + - qcom,tdm-data-out + - qcom,tdm-invert-sync + - qcom,tdm-data-delay + - qcom,tdm-data-align + + - if: + properties: + reg: + contains: + # MI2S DAI ID range PRIMARY_MI2S_RX - QUATERNARY_MI2S_TX and + # QUINARY_MI2S_RX - QUINARY_MI2S_TX + items: + oneOf: + - minimum: 16 + maximum: 23 + - minimum: 127 + maximum: 128 + then: + required: + - qcom,sd-lines + + additionalProperties: false + +required: + - compatible + - reg + - "#sound-dai-cells" + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + #include + #include + apr { + #address-cells = <1>; + #size-cells = <0>; + apr-service@4 { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + q6afedai@1 { + compatible = "qcom,q6afe-dais"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + + dai@22 { + reg = ; + qcom,sd-lines = <0 1 2 3>; + }; + }; + }; + }; From patchwork Mon Oct 25 17:16:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 1545862 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=ytmeHT7b; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4HdM8D0y6Gz9tk3 for ; Tue, 26 Oct 2021 04:17:16 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231802AbhJYRTh (ORCPT ); Mon, 25 Oct 2021 13:19:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51244 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232051AbhJYRTh (ORCPT ); Mon, 25 Oct 2021 13:19:37 -0400 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C864CC061767 for ; Mon, 25 Oct 2021 10:17:14 -0700 (PDT) Received: by mail-wr1-x431.google.com with SMTP id w15so10477159wra.3 for ; Mon, 25 Oct 2021 10:17:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=imP3Ut5HB4n6q2DrZyy9qRcidcMnxdcc3SMVUqr3MKw=; b=ytmeHT7b8bD7ME97opCDFy9ymvzz2JSucp5wAIyAREAmRulcGoqIU+peD/bWfwDpfL yZClh9WJRvqdxt+OkseIl+/JhiqineYwgX+ldMA8gBenYIfbycbmOH2+q9ZSMOoRzC8k r4ZYrCpFOWKNnjWJ4gsrEE08uLD4LsbCjO2I1+tgbJUeUAwJtBb6ONxCu+Z6QZDNr5/J wVCZK/AtT4hdPgM2+Qs5OcMP/L53oUD6Lzl2+DHKEWgm/2/nTiotpaYuaIsbfjmuUARG 6oJlauTUh+GsPd0GOXZ8M3Md9t3lTr90CLG3aHOzIZCkMFcvJJpc+ntXzW/MQl2HOk7l lG3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=imP3Ut5HB4n6q2DrZyy9qRcidcMnxdcc3SMVUqr3MKw=; b=h4ssf3xVN5tpmVbAHBAIjl8BS0qxLTazQVc6BhNWppTq743/lKxsDWGVO9zBTsg4vy akWRXNyXEiQFdW5K25mDxQdBaEiBPU3Kc+8YF15X3V5kTRztjtpw6jJriPjqzrZzebvT iy3ScqJqm1dmWSmvB5s8Yj0zh/6/2MZkcc8ptjkSSFYxfDaJNT/04vmo07yMlZbja0Mb VP69Q3hkzGLt/BhMr+WcpalvY5ZnQHtEHMNTK310PAUdjlT7UgqoNVxl1fyGm1idDa8t RRgOHtNMtbJ0BNleheuEnzVNVP76PdLDK6FMwOE28Zv4wBEZa3389G84576h3mqxqd7b 4PYQ== X-Gm-Message-State: AOAM5328hIAbp9OI5BT2nimZDcYAfiEQIaXyaKNdUUUtpUxvh4shPOSR vm3GGZ1idRwjupIggf0N0xc6VA== X-Google-Smtp-Source: ABdhPJzQSTTPH8B996xcbO7hA8Gu01AB4NaazJBxaMjqu5rGhZl+exkX3x2ifxKoptxXfvC1g5em3A== X-Received: by 2002:adf:a1cc:: with SMTP id v12mr25227806wrv.48.1635182232872; Mon, 25 Oct 2021 10:17:12 -0700 (PDT) Received: from srini-hackbox.lan (cpc86377-aztw32-2-0-cust226.18-1.cable.virginm.net. [92.233.226.227]) by smtp.gmail.com with ESMTPSA id r11sm5181012wrt.42.2021.10.25.10.17.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Oct 2021 10:17:12 -0700 (PDT) From: Srinivas Kandagatla To: broonie@kernel.org, bjorn.andersson@linaro.org, robh@kernel.org Cc: plai@codeaurora.org, pierre-louis.bossart@linux.intel.com, tiwai@suse.de, devicetree@vger.kernel.org, perex@perex.cz, alsa-devel@alsa-project.org, lgirdwood@gmail.com, bgoswami@codeaurora.org, Srinivas Kandagatla Subject: [PATCH v10 02/17] ASoC: dt-bindings: move LPASS clocks related bindings out of q6afe Date: Mon, 25 Oct 2021 18:16:34 +0100 Message-Id: <20211025171649.17730-3-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20211025171649.17730-1-srinivas.kandagatla@linaro.org> References: <20211025171649.17730-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org q6afe (Audio Front End) is one of the DSP service that handles both LPASS (Low Power Audio SubSystem) Audio ports and LPASS clocks. As LPASS is a hardwware IP and commonly used by Qualcomm Audio DSP. In order to allow multiple DSP frameworks to use these bindings its best to move it out from the dsp specific bindings. For compatibility reasons and not breaking which is already working we still maintain same compatible string "qcom,q6afe-clocks" Also as part of this change convert these LPASS clocks related bindings into yaml format. Signed-off-by: Srinivas Kandagatla Reviewed-by: Rob Herring --- .../devicetree/bindings/sound/qcom,q6afe.txt | 23 -------- .../sound/qcom,q6dsp-lpass-clocks.yaml | 56 +++++++++++++++++++ 2 files changed, 56 insertions(+), 23 deletions(-) create mode 100644 Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-clocks.yaml diff --git a/Documentation/devicetree/bindings/sound/qcom,q6afe.txt b/Documentation/devicetree/bindings/sound/qcom,q6afe.txt index fcf81058504c..bc6b5f1fe4f1 100644 --- a/Documentation/devicetree/bindings/sound/qcom,q6afe.txt +++ b/Documentation/devicetree/bindings/sound/qcom,q6afe.txt @@ -12,32 +12,9 @@ used by all apr services. Must contain the following properties. from DSP. example "qcom,q6afe" -= AFE CLOCKSS -"clocks" subnode of the AFE node. It represents q6afe clocks -"clocks" node should have following properties. -- compatible: - Usage: required - Value type: - Definition: must be "qcom,q6afe-clocks" - -- #clock-cells: - Usage: required - Value type: - Definition: Must be 2. Clock Id followed by - below valid clock coupling attributes. - 1 - for no coupled clock - 2 - for dividend of the coupled clock - 3 - for divisor of the coupled clock - 4 - for inverted and no couple clock - = EXAMPLE apr-service@4 { compatible = "qcom,q6afe"; reg = ; - - clocks { - compatible = "qcom,q6afe-clocks"; - #clock-cells = <2>; - }; }; diff --git a/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-clocks.yaml b/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-clocks.yaml new file mode 100644 index 000000000000..c686164732aa --- /dev/null +++ b/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-clocks.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/sound/qcom,q6dsp-lpass-clocks.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm DSP LPASS Clock Controller binding + +maintainers: + - Srinivas Kandagatla + +description: | + This binding describes the Qualcomm DSP Clock Controller + +properties: + compatible: + enum: + - qcom,q6afe-clocks + + reg: + maxItems: 1 + + '#clock-cells': + const: 2 + description: + Clock Id is followed by clock coupling attributes. + 1 = for no coupled clock + 2 = for dividend of the coupled clock + 3 = for divisor of the coupled clock + 4 = for inverted and no couple clock + +required: + - compatible + - reg + - "#clock-cells" + +additionalProperties: false + +examples: + - | + #include + #include + apr { + #address-cells = <1>; + #size-cells = <0>; + apr-service@4 { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + clock-controller@2 { + compatible = "qcom,q6afe-clocks"; + reg = <2>; + #clock-cells = <2>; + }; + }; + }; From patchwork Mon Oct 25 17:16:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 1545863 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=nxdXf7HR; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4HdM8D6K2gz9tk2 for ; Tue, 26 Oct 2021 04:17:16 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231888AbhJYRTi (ORCPT ); Mon, 25 Oct 2021 13:19:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51250 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232051AbhJYRTi (ORCPT ); Mon, 25 Oct 2021 13:19:38 -0400 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 456C1C061745 for ; Mon, 25 Oct 2021 10:17:15 -0700 (PDT) Received: by mail-wr1-x434.google.com with SMTP id m22so10803027wrb.0 for ; Mon, 25 Oct 2021 10:17:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1SYNXa9BSEU6BVfGZ3maNgsEM4Zr64CRywqKjDQaPHg=; b=nxdXf7HRhR5rWl3rO5yIIll01RAxUenIPQ2mxk4Rs/QPjIWPaT2HRX+nPRvDc/n5R6 y6f7QE4GlodBuwbIkNNP7MzhLXBwIJguL0AY3AcILptcZ+Z4KBLDhK5U+Le5WPcvcX4I ay4YPo7ai9P81Gw3DGNbGXz4YYR7EUs1iXzCtTLJRbfwc884fWZK11kXA//JRNEkWdW3 DfJggWREsRiQMDhQpHTQ8Ix7aaHezbk/EhlKbet6Bwa7rXxl93iaLGAAAT2RuWTVxMia r4daWq6xI5yCXHjNH92hcLHMnVMvx7HmjhvY/9BJdjmU2EBBejuK3uIJobMbK6QbfX1I G0XQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1SYNXa9BSEU6BVfGZ3maNgsEM4Zr64CRywqKjDQaPHg=; b=fT0YS196eX6vd+nb3BB3yLEXvmFBDFzlc6RGbnllMXhnvYxTLV4Zruje3otleKuXb6 Wtre5nYKX6mcy87f5Gi4YIDQFHu0D0ZiCEzpKRSMW9UY64xuGlm7haRMNaFSFvDSVHWs qg9iECsVw5xl60eQUwdycUcZ/QrM02JPqSZL0glXALCOqPeVOLwDPHXuIzLNM/4PFNwE sUaMl3yxqkFVVAnLRLuTowTgafcaEV55PvMYA3hL62S+ZkhQbFGkFjkcG7Z4zyu065rI vxodCdb9EQINfDo3UsMVI2mChqksT8ySnB7KzcEBTwXVh6u8p02QkE1LYfDyObaZ3OpL 5F4A== X-Gm-Message-State: AOAM530g6vXbo5qUhIeSYT/9jA8RvD7Df59UF9QHsIFldC+La0yWchHp d9qfvRAU45DsOCo2QhwIulPnkw== X-Google-Smtp-Source: ABdhPJzV06Ru5E4Ij97tuI0E40/DyuLy4YyxaqGb/s4mIOz8GF5R95omBboX0961PLrOJRV01kgfiQ== X-Received: by 2002:adf:f58c:: with SMTP id f12mr25069487wro.413.1635182233857; Mon, 25 Oct 2021 10:17:13 -0700 (PDT) Received: from srini-hackbox.lan (cpc86377-aztw32-2-0-cust226.18-1.cable.virginm.net. [92.233.226.227]) by smtp.gmail.com with ESMTPSA id r11sm5181012wrt.42.2021.10.25.10.17.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Oct 2021 10:17:13 -0700 (PDT) From: Srinivas Kandagatla To: broonie@kernel.org, bjorn.andersson@linaro.org, robh@kernel.org Cc: plai@codeaurora.org, pierre-louis.bossart@linux.intel.com, tiwai@suse.de, devicetree@vger.kernel.org, perex@perex.cz, alsa-devel@alsa-project.org, lgirdwood@gmail.com, bgoswami@codeaurora.org, Srinivas Kandagatla Subject: [PATCH v10 03/17] ASoC: dt-bindings: rename q6afe.h to q6dsp-lpass-ports.h Date: Mon, 25 Oct 2021 18:16:35 +0100 Message-Id: <20211025171649.17730-4-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20211025171649.17730-1-srinivas.kandagatla@linaro.org> References: <20211025171649.17730-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org move all LPASS audio ports defines from q6afe.h to q6dsp-lpass-ports.h as these belong to LPASS IP. Also this move helps in reusing this header across multiple audio frameworks on Qualcomm Audio DSP. This patch is split out of the dt-bindings patch to enable easy review. Signed-off-by: Srinivas Kandagatla Acked-by: Rob Herring --- include/dt-bindings/sound/qcom,q6afe.h | 203 +---------------- .../sound/qcom,q6dsp-lpass-ports.h | 208 ++++++++++++++++++ 2 files changed, 210 insertions(+), 201 deletions(-) create mode 100644 include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h diff --git a/include/dt-bindings/sound/qcom,q6afe.h b/include/dt-bindings/sound/qcom,q6afe.h index 66c21ab03eef..9d5d89cfabcf 100644 --- a/include/dt-bindings/sound/qcom,q6afe.h +++ b/include/dt-bindings/sound/qcom,q6afe.h @@ -2,207 +2,8 @@ #ifndef __DT_BINDINGS_Q6_AFE_H__ #define __DT_BINDINGS_Q6_AFE_H__ -/* Audio Front End (AFE) virtual ports IDs */ -#define HDMI_RX 1 -#define SLIMBUS_0_RX 2 -#define SLIMBUS_0_TX 3 -#define SLIMBUS_1_RX 4 -#define SLIMBUS_1_TX 5 -#define SLIMBUS_2_RX 6 -#define SLIMBUS_2_TX 7 -#define SLIMBUS_3_RX 8 -#define SLIMBUS_3_TX 9 -#define SLIMBUS_4_RX 10 -#define SLIMBUS_4_TX 11 -#define SLIMBUS_5_RX 12 -#define SLIMBUS_5_TX 13 -#define SLIMBUS_6_RX 14 -#define SLIMBUS_6_TX 15 -#define PRIMARY_MI2S_RX 16 -#define PRIMARY_MI2S_TX 17 -#define SECONDARY_MI2S_RX 18 -#define SECONDARY_MI2S_TX 19 -#define TERTIARY_MI2S_RX 20 -#define TERTIARY_MI2S_TX 21 -#define QUATERNARY_MI2S_RX 22 -#define QUATERNARY_MI2S_TX 23 -#define PRIMARY_TDM_RX_0 24 -#define PRIMARY_TDM_TX_0 25 -#define PRIMARY_TDM_RX_1 26 -#define PRIMARY_TDM_TX_1 27 -#define PRIMARY_TDM_RX_2 28 -#define PRIMARY_TDM_TX_2 29 -#define PRIMARY_TDM_RX_3 30 -#define PRIMARY_TDM_TX_3 31 -#define PRIMARY_TDM_RX_4 32 -#define PRIMARY_TDM_TX_4 33 -#define PRIMARY_TDM_RX_5 34 -#define PRIMARY_TDM_TX_5 35 -#define PRIMARY_TDM_RX_6 36 -#define PRIMARY_TDM_TX_6 37 -#define PRIMARY_TDM_RX_7 38 -#define PRIMARY_TDM_TX_7 39 -#define SECONDARY_TDM_RX_0 40 -#define SECONDARY_TDM_TX_0 41 -#define SECONDARY_TDM_RX_1 42 -#define SECONDARY_TDM_TX_1 43 -#define SECONDARY_TDM_RX_2 44 -#define SECONDARY_TDM_TX_2 45 -#define SECONDARY_TDM_RX_3 46 -#define SECONDARY_TDM_TX_3 47 -#define SECONDARY_TDM_RX_4 48 -#define SECONDARY_TDM_TX_4 49 -#define SECONDARY_TDM_RX_5 50 -#define SECONDARY_TDM_TX_5 51 -#define SECONDARY_TDM_RX_6 52 -#define SECONDARY_TDM_TX_6 53 -#define SECONDARY_TDM_RX_7 54 -#define SECONDARY_TDM_TX_7 55 -#define TERTIARY_TDM_RX_0 56 -#define TERTIARY_TDM_TX_0 57 -#define TERTIARY_TDM_RX_1 58 -#define TERTIARY_TDM_TX_1 59 -#define TERTIARY_TDM_RX_2 60 -#define TERTIARY_TDM_TX_2 61 -#define TERTIARY_TDM_RX_3 62 -#define TERTIARY_TDM_TX_3 63 -#define TERTIARY_TDM_RX_4 64 -#define TERTIARY_TDM_TX_4 65 -#define TERTIARY_TDM_RX_5 66 -#define TERTIARY_TDM_TX_5 67 -#define TERTIARY_TDM_RX_6 68 -#define TERTIARY_TDM_TX_6 69 -#define TERTIARY_TDM_RX_7 70 -#define TERTIARY_TDM_TX_7 71 -#define QUATERNARY_TDM_RX_0 72 -#define QUATERNARY_TDM_TX_0 73 -#define QUATERNARY_TDM_RX_1 74 -#define QUATERNARY_TDM_TX_1 75 -#define QUATERNARY_TDM_RX_2 76 -#define QUATERNARY_TDM_TX_2 77 -#define QUATERNARY_TDM_RX_3 78 -#define QUATERNARY_TDM_TX_3 79 -#define QUATERNARY_TDM_RX_4 80 -#define QUATERNARY_TDM_TX_4 81 -#define QUATERNARY_TDM_RX_5 82 -#define QUATERNARY_TDM_TX_5 83 -#define QUATERNARY_TDM_RX_6 84 -#define QUATERNARY_TDM_TX_6 85 -#define QUATERNARY_TDM_RX_7 86 -#define QUATERNARY_TDM_TX_7 87 -#define QUINARY_TDM_RX_0 88 -#define QUINARY_TDM_TX_0 89 -#define QUINARY_TDM_RX_1 90 -#define QUINARY_TDM_TX_1 91 -#define QUINARY_TDM_RX_2 92 -#define QUINARY_TDM_TX_2 93 -#define QUINARY_TDM_RX_3 94 -#define QUINARY_TDM_TX_3 95 -#define QUINARY_TDM_RX_4 96 -#define QUINARY_TDM_TX_4 97 -#define QUINARY_TDM_RX_5 98 -#define QUINARY_TDM_TX_5 99 -#define QUINARY_TDM_RX_6 100 -#define QUINARY_TDM_TX_6 101 -#define QUINARY_TDM_RX_7 102 -#define QUINARY_TDM_TX_7 103 -#define DISPLAY_PORT_RX 104 -#define WSA_CODEC_DMA_RX_0 105 -#define WSA_CODEC_DMA_TX_0 106 -#define WSA_CODEC_DMA_RX_1 107 -#define WSA_CODEC_DMA_TX_1 108 -#define WSA_CODEC_DMA_TX_2 109 -#define VA_CODEC_DMA_TX_0 110 -#define VA_CODEC_DMA_TX_1 111 -#define VA_CODEC_DMA_TX_2 112 -#define RX_CODEC_DMA_RX_0 113 -#define TX_CODEC_DMA_TX_0 114 -#define RX_CODEC_DMA_RX_1 115 -#define TX_CODEC_DMA_TX_1 116 -#define RX_CODEC_DMA_RX_2 117 -#define TX_CODEC_DMA_TX_2 118 -#define RX_CODEC_DMA_RX_3 119 -#define TX_CODEC_DMA_TX_3 120 -#define RX_CODEC_DMA_RX_4 121 -#define TX_CODEC_DMA_TX_4 122 -#define RX_CODEC_DMA_RX_5 123 -#define TX_CODEC_DMA_TX_5 124 -#define RX_CODEC_DMA_RX_6 125 -#define RX_CODEC_DMA_RX_7 126 -#define QUINARY_MI2S_RX 127 -#define QUINARY_MI2S_TX 128 +/* This file exists due to backward compatibility reasons, Please do not DELETE! */ -#define LPASS_CLK_ID_PRI_MI2S_IBIT 1 -#define LPASS_CLK_ID_PRI_MI2S_EBIT 2 -#define LPASS_CLK_ID_SEC_MI2S_IBIT 3 -#define LPASS_CLK_ID_SEC_MI2S_EBIT 4 -#define LPASS_CLK_ID_TER_MI2S_IBIT 5 -#define LPASS_CLK_ID_TER_MI2S_EBIT 6 -#define LPASS_CLK_ID_QUAD_MI2S_IBIT 7 -#define LPASS_CLK_ID_QUAD_MI2S_EBIT 8 -#define LPASS_CLK_ID_SPEAKER_I2S_IBIT 9 -#define LPASS_CLK_ID_SPEAKER_I2S_EBIT 10 -#define LPASS_CLK_ID_SPEAKER_I2S_OSR 11 -#define LPASS_CLK_ID_QUI_MI2S_IBIT 12 -#define LPASS_CLK_ID_QUI_MI2S_EBIT 13 -#define LPASS_CLK_ID_SEN_MI2S_IBIT 14 -#define LPASS_CLK_ID_SEN_MI2S_EBIT 15 -#define LPASS_CLK_ID_INT0_MI2S_IBIT 16 -#define LPASS_CLK_ID_INT1_MI2S_IBIT 17 -#define LPASS_CLK_ID_INT2_MI2S_IBIT 18 -#define LPASS_CLK_ID_INT3_MI2S_IBIT 19 -#define LPASS_CLK_ID_INT4_MI2S_IBIT 20 -#define LPASS_CLK_ID_INT5_MI2S_IBIT 21 -#define LPASS_CLK_ID_INT6_MI2S_IBIT 22 -#define LPASS_CLK_ID_QUI_MI2S_OSR 23 -#define LPASS_CLK_ID_PRI_PCM_IBIT 24 -#define LPASS_CLK_ID_PRI_PCM_EBIT 25 -#define LPASS_CLK_ID_SEC_PCM_IBIT 26 -#define LPASS_CLK_ID_SEC_PCM_EBIT 27 -#define LPASS_CLK_ID_TER_PCM_IBIT 28 -#define LPASS_CLK_ID_TER_PCM_EBIT 29 -#define LPASS_CLK_ID_QUAD_PCM_IBIT 30 -#define LPASS_CLK_ID_QUAD_PCM_EBIT 31 -#define LPASS_CLK_ID_QUIN_PCM_IBIT 32 -#define LPASS_CLK_ID_QUIN_PCM_EBIT 33 -#define LPASS_CLK_ID_QUI_PCM_OSR 34 -#define LPASS_CLK_ID_PRI_TDM_IBIT 35 -#define LPASS_CLK_ID_PRI_TDM_EBIT 36 -#define LPASS_CLK_ID_SEC_TDM_IBIT 37 -#define LPASS_CLK_ID_SEC_TDM_EBIT 38 -#define LPASS_CLK_ID_TER_TDM_IBIT 39 -#define LPASS_CLK_ID_TER_TDM_EBIT 40 -#define LPASS_CLK_ID_QUAD_TDM_IBIT 41 -#define LPASS_CLK_ID_QUAD_TDM_EBIT 42 -#define LPASS_CLK_ID_QUIN_TDM_IBIT 43 -#define LPASS_CLK_ID_QUIN_TDM_EBIT 44 -#define LPASS_CLK_ID_QUIN_TDM_OSR 45 -#define LPASS_CLK_ID_MCLK_1 46 -#define LPASS_CLK_ID_MCLK_2 47 -#define LPASS_CLK_ID_MCLK_3 48 -#define LPASS_CLK_ID_MCLK_4 49 -#define LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE 50 -#define LPASS_CLK_ID_INT_MCLK_0 51 -#define LPASS_CLK_ID_INT_MCLK_1 52 -#define LPASS_CLK_ID_MCLK_5 53 -#define LPASS_CLK_ID_WSA_CORE_MCLK 54 -#define LPASS_CLK_ID_WSA_CORE_NPL_MCLK 55 -#define LPASS_CLK_ID_VA_CORE_MCLK 56 -#define LPASS_CLK_ID_TX_CORE_MCLK 57 -#define LPASS_CLK_ID_TX_CORE_NPL_MCLK 58 -#define LPASS_CLK_ID_RX_CORE_MCLK 59 -#define LPASS_CLK_ID_RX_CORE_NPL_MCLK 60 -#define LPASS_CLK_ID_VA_CORE_2X_MCLK 61 - -#define LPASS_HW_AVTIMER_VOTE 101 -#define LPASS_HW_MACRO_VOTE 102 -#define LPASS_HW_DCODEC_VOTE 103 - -#define Q6AFE_MAX_CLK_ID 104 - -#define LPASS_CLK_ATTRIBUTE_INVALID 0x0 -#define LPASS_CLK_ATTRIBUTE_COUPLE_NO 0x1 -#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND 0x2 -#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR 0x3 +#include #endif /* __DT_BINDINGS_Q6_AFE_H__ */ diff --git a/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h b/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h new file mode 100644 index 000000000000..0d3276c8fc11 --- /dev/null +++ b/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h @@ -0,0 +1,208 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_Q6_AUDIO_PORTS_H__ +#define __DT_BINDINGS_Q6_AUDIO_PORTS_H__ + +/* LPASS Audio virtual ports IDs */ +#define HDMI_RX 1 +#define SLIMBUS_0_RX 2 +#define SLIMBUS_0_TX 3 +#define SLIMBUS_1_RX 4 +#define SLIMBUS_1_TX 5 +#define SLIMBUS_2_RX 6 +#define SLIMBUS_2_TX 7 +#define SLIMBUS_3_RX 8 +#define SLIMBUS_3_TX 9 +#define SLIMBUS_4_RX 10 +#define SLIMBUS_4_TX 11 +#define SLIMBUS_5_RX 12 +#define SLIMBUS_5_TX 13 +#define SLIMBUS_6_RX 14 +#define SLIMBUS_6_TX 15 +#define PRIMARY_MI2S_RX 16 +#define PRIMARY_MI2S_TX 17 +#define SECONDARY_MI2S_RX 18 +#define SECONDARY_MI2S_TX 19 +#define TERTIARY_MI2S_RX 20 +#define TERTIARY_MI2S_TX 21 +#define QUATERNARY_MI2S_RX 22 +#define QUATERNARY_MI2S_TX 23 +#define PRIMARY_TDM_RX_0 24 +#define PRIMARY_TDM_TX_0 25 +#define PRIMARY_TDM_RX_1 26 +#define PRIMARY_TDM_TX_1 27 +#define PRIMARY_TDM_RX_2 28 +#define PRIMARY_TDM_TX_2 29 +#define PRIMARY_TDM_RX_3 30 +#define PRIMARY_TDM_TX_3 31 +#define PRIMARY_TDM_RX_4 32 +#define PRIMARY_TDM_TX_4 33 +#define PRIMARY_TDM_RX_5 34 +#define PRIMARY_TDM_TX_5 35 +#define PRIMARY_TDM_RX_6 36 +#define PRIMARY_TDM_TX_6 37 +#define PRIMARY_TDM_RX_7 38 +#define PRIMARY_TDM_TX_7 39 +#define SECONDARY_TDM_RX_0 40 +#define SECONDARY_TDM_TX_0 41 +#define SECONDARY_TDM_RX_1 42 +#define SECONDARY_TDM_TX_1 43 +#define SECONDARY_TDM_RX_2 44 +#define SECONDARY_TDM_TX_2 45 +#define SECONDARY_TDM_RX_3 46 +#define SECONDARY_TDM_TX_3 47 +#define SECONDARY_TDM_RX_4 48 +#define SECONDARY_TDM_TX_4 49 +#define SECONDARY_TDM_RX_5 50 +#define SECONDARY_TDM_TX_5 51 +#define SECONDARY_TDM_RX_6 52 +#define SECONDARY_TDM_TX_6 53 +#define SECONDARY_TDM_RX_7 54 +#define SECONDARY_TDM_TX_7 55 +#define TERTIARY_TDM_RX_0 56 +#define TERTIARY_TDM_TX_0 57 +#define TERTIARY_TDM_RX_1 58 +#define TERTIARY_TDM_TX_1 59 +#define TERTIARY_TDM_RX_2 60 +#define TERTIARY_TDM_TX_2 61 +#define TERTIARY_TDM_RX_3 62 +#define TERTIARY_TDM_TX_3 63 +#define TERTIARY_TDM_RX_4 64 +#define TERTIARY_TDM_TX_4 65 +#define TERTIARY_TDM_RX_5 66 +#define TERTIARY_TDM_TX_5 67 +#define TERTIARY_TDM_RX_6 68 +#define TERTIARY_TDM_TX_6 69 +#define TERTIARY_TDM_RX_7 70 +#define TERTIARY_TDM_TX_7 71 +#define QUATERNARY_TDM_RX_0 72 +#define QUATERNARY_TDM_TX_0 73 +#define QUATERNARY_TDM_RX_1 74 +#define QUATERNARY_TDM_TX_1 75 +#define QUATERNARY_TDM_RX_2 76 +#define QUATERNARY_TDM_TX_2 77 +#define QUATERNARY_TDM_RX_3 78 +#define QUATERNARY_TDM_TX_3 79 +#define QUATERNARY_TDM_RX_4 80 +#define QUATERNARY_TDM_TX_4 81 +#define QUATERNARY_TDM_RX_5 82 +#define QUATERNARY_TDM_TX_5 83 +#define QUATERNARY_TDM_RX_6 84 +#define QUATERNARY_TDM_TX_6 85 +#define QUATERNARY_TDM_RX_7 86 +#define QUATERNARY_TDM_TX_7 87 +#define QUINARY_TDM_RX_0 88 +#define QUINARY_TDM_TX_0 89 +#define QUINARY_TDM_RX_1 90 +#define QUINARY_TDM_TX_1 91 +#define QUINARY_TDM_RX_2 92 +#define QUINARY_TDM_TX_2 93 +#define QUINARY_TDM_RX_3 94 +#define QUINARY_TDM_TX_3 95 +#define QUINARY_TDM_RX_4 96 +#define QUINARY_TDM_TX_4 97 +#define QUINARY_TDM_RX_5 98 +#define QUINARY_TDM_TX_5 99 +#define QUINARY_TDM_RX_6 100 +#define QUINARY_TDM_TX_6 101 +#define QUINARY_TDM_RX_7 102 +#define QUINARY_TDM_TX_7 103 +#define DISPLAY_PORT_RX 104 +#define WSA_CODEC_DMA_RX_0 105 +#define WSA_CODEC_DMA_TX_0 106 +#define WSA_CODEC_DMA_RX_1 107 +#define WSA_CODEC_DMA_TX_1 108 +#define WSA_CODEC_DMA_TX_2 109 +#define VA_CODEC_DMA_TX_0 110 +#define VA_CODEC_DMA_TX_1 111 +#define VA_CODEC_DMA_TX_2 112 +#define RX_CODEC_DMA_RX_0 113 +#define TX_CODEC_DMA_TX_0 114 +#define RX_CODEC_DMA_RX_1 115 +#define TX_CODEC_DMA_TX_1 116 +#define RX_CODEC_DMA_RX_2 117 +#define TX_CODEC_DMA_TX_2 118 +#define RX_CODEC_DMA_RX_3 119 +#define TX_CODEC_DMA_TX_3 120 +#define RX_CODEC_DMA_RX_4 121 +#define TX_CODEC_DMA_TX_4 122 +#define RX_CODEC_DMA_RX_5 123 +#define TX_CODEC_DMA_TX_5 124 +#define RX_CODEC_DMA_RX_6 125 +#define RX_CODEC_DMA_RX_7 126 +#define QUINARY_MI2S_RX 127 +#define QUINARY_MI2S_TX 128 + +#define LPASS_CLK_ID_PRI_MI2S_IBIT 1 +#define LPASS_CLK_ID_PRI_MI2S_EBIT 2 +#define LPASS_CLK_ID_SEC_MI2S_IBIT 3 +#define LPASS_CLK_ID_SEC_MI2S_EBIT 4 +#define LPASS_CLK_ID_TER_MI2S_IBIT 5 +#define LPASS_CLK_ID_TER_MI2S_EBIT 6 +#define LPASS_CLK_ID_QUAD_MI2S_IBIT 7 +#define LPASS_CLK_ID_QUAD_MI2S_EBIT 8 +#define LPASS_CLK_ID_SPEAKER_I2S_IBIT 9 +#define LPASS_CLK_ID_SPEAKER_I2S_EBIT 10 +#define LPASS_CLK_ID_SPEAKER_I2S_OSR 11 +#define LPASS_CLK_ID_QUI_MI2S_IBIT 12 +#define LPASS_CLK_ID_QUI_MI2S_EBIT 13 +#define LPASS_CLK_ID_SEN_MI2S_IBIT 14 +#define LPASS_CLK_ID_SEN_MI2S_EBIT 15 +#define LPASS_CLK_ID_INT0_MI2S_IBIT 16 +#define LPASS_CLK_ID_INT1_MI2S_IBIT 17 +#define LPASS_CLK_ID_INT2_MI2S_IBIT 18 +#define LPASS_CLK_ID_INT3_MI2S_IBIT 19 +#define LPASS_CLK_ID_INT4_MI2S_IBIT 20 +#define LPASS_CLK_ID_INT5_MI2S_IBIT 21 +#define LPASS_CLK_ID_INT6_MI2S_IBIT 22 +#define LPASS_CLK_ID_QUI_MI2S_OSR 23 +#define LPASS_CLK_ID_PRI_PCM_IBIT 24 +#define LPASS_CLK_ID_PRI_PCM_EBIT 25 +#define LPASS_CLK_ID_SEC_PCM_IBIT 26 +#define LPASS_CLK_ID_SEC_PCM_EBIT 27 +#define LPASS_CLK_ID_TER_PCM_IBIT 28 +#define LPASS_CLK_ID_TER_PCM_EBIT 29 +#define LPASS_CLK_ID_QUAD_PCM_IBIT 30 +#define LPASS_CLK_ID_QUAD_PCM_EBIT 31 +#define LPASS_CLK_ID_QUIN_PCM_IBIT 32 +#define LPASS_CLK_ID_QUIN_PCM_EBIT 33 +#define LPASS_CLK_ID_QUI_PCM_OSR 34 +#define LPASS_CLK_ID_PRI_TDM_IBIT 35 +#define LPASS_CLK_ID_PRI_TDM_EBIT 36 +#define LPASS_CLK_ID_SEC_TDM_IBIT 37 +#define LPASS_CLK_ID_SEC_TDM_EBIT 38 +#define LPASS_CLK_ID_TER_TDM_IBIT 39 +#define LPASS_CLK_ID_TER_TDM_EBIT 40 +#define LPASS_CLK_ID_QUAD_TDM_IBIT 41 +#define LPASS_CLK_ID_QUAD_TDM_EBIT 42 +#define LPASS_CLK_ID_QUIN_TDM_IBIT 43 +#define LPASS_CLK_ID_QUIN_TDM_EBIT 44 +#define LPASS_CLK_ID_QUIN_TDM_OSR 45 +#define LPASS_CLK_ID_MCLK_1 46 +#define LPASS_CLK_ID_MCLK_2 47 +#define LPASS_CLK_ID_MCLK_3 48 +#define LPASS_CLK_ID_MCLK_4 49 +#define LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE 50 +#define LPASS_CLK_ID_INT_MCLK_0 51 +#define LPASS_CLK_ID_INT_MCLK_1 52 +#define LPASS_CLK_ID_MCLK_5 53 +#define LPASS_CLK_ID_WSA_CORE_MCLK 54 +#define LPASS_CLK_ID_WSA_CORE_NPL_MCLK 55 +#define LPASS_CLK_ID_VA_CORE_MCLK 56 +#define LPASS_CLK_ID_TX_CORE_MCLK 57 +#define LPASS_CLK_ID_TX_CORE_NPL_MCLK 58 +#define LPASS_CLK_ID_RX_CORE_MCLK 59 +#define LPASS_CLK_ID_RX_CORE_NPL_MCLK 60 +#define LPASS_CLK_ID_VA_CORE_2X_MCLK 61 + +#define LPASS_HW_AVTIMER_VOTE 101 +#define LPASS_HW_MACRO_VOTE 102 +#define LPASS_HW_DCODEC_VOTE 103 + +#define Q6AFE_MAX_CLK_ID 104 + +#define LPASS_CLK_ATTRIBUTE_INVALID 0x0 +#define LPASS_CLK_ATTRIBUTE_COUPLE_NO 0x1 +#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND 0x2 +#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR 0x3 + +#endif /* __DT_BINDINGS_Q6_AUDIO_PORTS_H__ */ From patchwork Mon Oct 25 17:16:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 1545864 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=e6CRZxO5; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) 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[92.233.226.227]) by smtp.gmail.com with ESMTPSA id r11sm5181012wrt.42.2021.10.25.10.17.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Oct 2021 10:17:16 -0700 (PDT) From: Srinivas Kandagatla To: broonie@kernel.org, bjorn.andersson@linaro.org, robh@kernel.org Cc: plai@codeaurora.org, pierre-louis.bossart@linux.intel.com, tiwai@suse.de, devicetree@vger.kernel.org, perex@perex.cz, alsa-devel@alsa-project.org, lgirdwood@gmail.com, bgoswami@codeaurora.org, Srinivas Kandagatla Subject: [PATCH v10 06/17] ASoC: dt-bindings: q6dsp: add q6apm-lpass-dai compatible Date: Mon, 25 Oct 2021 18:16:38 +0100 Message-Id: <20211025171649.17730-7-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20211025171649.17730-1-srinivas.kandagatla@linaro.org> References: <20211025171649.17730-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org on AudioReach audio Framework access to LPASS ports is via Q6APM(Audio Process Manager) service, so add a dedicated compatible string for this. Signed-off-by: Srinivas Kandagatla Reviewed-by: Rob Herring --- .../sound/qcom,q6dsp-lpass-ports.yaml | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml b/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml index e6148c17419b..dc7fba7b92d5 100644 --- a/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml @@ -16,6 +16,7 @@ properties: compatible: enum: - qcom,q6afe-dais + - qcom,q6apm-lpass-dais reg: maxItems: 1 @@ -169,6 +170,32 @@ examples: #size-cells = <0>; #sound-dai-cells = <1>; + dai@22 { + reg = ; + qcom,sd-lines = <0 1 2 3>; + }; + }; + }; + }; + - | + #include + gpr { + compatible = "qcom,gpr"; + #address-cells = <1>; + #size-cells = <0>; + qcom,domain = ; + service@1 { + compatible = "qcom,q6apm"; + reg = ; + #address-cells = <1>; + #size-cells = <0>; + q6apmdai@1 { + compatible = "qcom,q6apm-lpass-dais"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + dai@22 { reg = ; qcom,sd-lines = <0 1 2 3>; From patchwork Mon Oct 25 17:16:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 1545865 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=c7RQ8N0F; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4HdM8K1DBwz9tk2 for ; Tue, 26 Oct 2021 04:17:21 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232260AbhJYRTm (ORCPT ); Mon, 25 Oct 2021 13:19:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51284 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230183AbhJYRTl (ORCPT ); Mon, 25 Oct 2021 13:19:41 -0400 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 54756C061745 for ; Mon, 25 Oct 2021 10:17:19 -0700 (PDT) Received: by mail-wr1-x430.google.com with SMTP id u18so10727797wrg.5 for ; Mon, 25 Oct 2021 10:17:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2dEl9+MXeU9ILc1heZjgbaev2CRPnvoQ4/YvbAvAmQM=; b=c7RQ8N0FckCPbiqFmHr2Iee9AMNPrl3pD5lRc9eL4NfuUR4tJMPIpLdgheVNyp3FAA o9FB3TUhWLz1cx7GqAhZoTqGkYiVNj/4edPQk2bu3one2Ppfr9HB38N6a6hzKYyWfQye dv93GlgjGXAWyXLfVfx99JD/Gcy5qCytQP5aXWO/eVdOSlNzLUOfYTreckiDNquPcId9 DqSyhHiwArAKvrbOPbPYrWgntQFfNa69b+Yq8klM0dF+XzRSKnmEccf+8HhAs4exaXCW QNo01v+bjebG2NUkdO5AF5SiCUWQff1GCAbuOypNPHaQgnDYjMIvsdIr0NbJY27fVb9N 7eAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2dEl9+MXeU9ILc1heZjgbaev2CRPnvoQ4/YvbAvAmQM=; b=AAve9Y+d2U1t9hcubMo21KMQ+NHaIgy2xndJneDu8O/B4XIed/HOlbKhfuFKGBMXxq z0wZrkr0RFYvzAgTE4iInuIy5aFBF8CdmLTu7cJgpNLQOGLGAi7bpVwJdGyIVCeDfOPh VRSVB1qAfw9V4TcX36Fu+mY7f/D6Y7NCnxqrEdP3p2iWiSpTCFHB6lJN5CrBiantmieL /zyTQRipeHZSa6qMsqkFL/XU9zTAsy6JU4g5VVxlC8r07He62H4M0bn6K5NQWUs0VdQx iTCrSdVztAOlbdyCGSuV574gbG6eVlSqHpoo2+ET/rs0iLlvx9ChzdikZzJtbAEEP6AZ G2pg== X-Gm-Message-State: AOAM5305/gAMnVsHruAZzPO8HHs2x/Ff1btj92KEagWAIKQ59ugFOyGa HFBd+r1z7P7FoDk4vz7dpvQmJw== X-Google-Smtp-Source: ABdhPJxasgPnoZsU+rgkUSB9kBqOkjrEXkuiCJapUg3WymuMefB64lEDzsdpNjAzVUPsD3JokBaOjQ== X-Received: by 2002:a5d:528b:: with SMTP id c11mr24672248wrv.35.1635182237960; Mon, 25 Oct 2021 10:17:17 -0700 (PDT) Received: from srini-hackbox.lan (cpc86377-aztw32-2-0-cust226.18-1.cable.virginm.net. [92.233.226.227]) by smtp.gmail.com with ESMTPSA id r11sm5181012wrt.42.2021.10.25.10.17.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Oct 2021 10:17:17 -0700 (PDT) From: Srinivas Kandagatla To: broonie@kernel.org, bjorn.andersson@linaro.org, robh@kernel.org Cc: plai@codeaurora.org, pierre-louis.bossart@linux.intel.com, tiwai@suse.de, devicetree@vger.kernel.org, perex@perex.cz, alsa-devel@alsa-project.org, lgirdwood@gmail.com, bgoswami@codeaurora.org, Srinivas Kandagatla Subject: [PATCH v10 07/17] ASoC: dt-bindings: lpass-clocks: add q6prm clocks compatible Date: Mon, 25 Oct 2021 18:16:39 +0100 Message-Id: <20211025171649.17730-8-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20211025171649.17730-1-srinivas.kandagatla@linaro.org> References: <20211025171649.17730-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On AudioReach audio Framework access to LPASS ports is via Q6PRM (Proxy Resource Manager) service, so add a dedicated lpass-clock compatible string for this. Signed-off-by: Srinivas Kandagatla Reviewed-by: Rob Herring --- .../sound/qcom,q6dsp-lpass-clocks.yaml | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-clocks.yaml b/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-clocks.yaml index c686164732aa..f83f00737a2f 100644 --- a/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-clocks.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-clocks.yaml @@ -16,6 +16,7 @@ properties: compatible: enum: - qcom,q6afe-clocks + - qcom,q6prm-lpass-clocks reg: maxItems: 1 @@ -54,3 +55,23 @@ examples: }; }; }; + + - | + #include + gpr { + compatible = "qcom,gpr"; + qcom,domain = ; + #address-cells = <1>; + #size-cells = <0>; + service@2 { + reg = ; + compatible = "qcom,q6prm"; + #address-cells = <1>; + #size-cells = <0>; + clock-controller@2 { + compatible = "qcom,q6prm-lpass-clocks"; + reg = <2>; + #clock-cells = <2>; + }; + }; + }; From patchwork Mon Oct 25 17:16:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 1545866 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=wzF5Nefa; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4HdM8K6tM6z9tjx for ; Tue, 26 Oct 2021 04:17:21 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232742AbhJYRTn (ORCPT ); Mon, 25 Oct 2021 13:19:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51292 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232410AbhJYRTm (ORCPT ); Mon, 25 Oct 2021 13:19:42 -0400 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5E9DCC061767 for ; Mon, 25 Oct 2021 10:17:20 -0700 (PDT) Received: by mail-wr1-x42f.google.com with SMTP id k7so9484455wrd.13 for ; Mon, 25 Oct 2021 10:17:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZUTQPGMld1NjfHqBeBgP6Q5d4oV2F6unCGQSSDbPgkI=; b=wzF5NefaWuJV1SiBItHQZTQ+EQ6Wii51YLv2LcaNV+DYBZcevM3rTvH9bVI7Nt1ItL TNvgVRW8Agz91hECjveULwumyf1CDpjFOsdSu/3CRZueKjvBSXkKtZmOt906+hXZaPJ8 qEqlHb0qQhYsk4jqpQQwmHQ2IMDyRXI+HMm4VpO5nSyZWWwQsUYFjjnq8ab3VGu2eflG HXURgLuGzqk9lklIpHgyudqDKK7vMs3f858vsSy7V3+yeH5I1w4kslpUaaK3Mg/6yupC Kkw8Gs92pH8tcaUcxensMMqXg94rfEsP5BA7EESEyaeHDjqayDBDsWxH5QT5/Fbe9MbU GKwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZUTQPGMld1NjfHqBeBgP6Q5d4oV2F6unCGQSSDbPgkI=; b=DKnMjA3KYDfx9qB8w7Ax2GJJCB31a9yMAD/Knsg43tp1dOeTdTrxRR3hOpBxWEYhS/ sMIJGIUwZSiEWpz73qCAJNtjZ/u0V8GDS4JN89214LC2gNlxIp6w8uO+fYoMNd9Hdfki eJDVO+ZXdxoNq4kgoV2T8/Y6quJdawgxUkTz9SUIgdBayC6xHVTn/MTcwuGDN85tUR6/ 5mhkSGaety006wnV8mcy89LLW2Xs9xwmRhD9TD1N3e8dyRv/UrFVbjQQpIThLWBDr7/4 +9Uerc1mlnD9126Tl0Huox+fKuNXFZLGvWKddDGcmPCHMfIECr4SgB5fuBE8SV0caGMy irCA== X-Gm-Message-State: AOAM5328bg8Fsl/THhCTP+5ymB9Cooe2zQAAt6et1dG+3CDRVqanSFqU xkyUc0ml/dHcHtgR+mkj9WmE3g== X-Google-Smtp-Source: ABdhPJwoWPto9WG3m61QzjZnDE2aejUvuK9tn0SIenbQwblhQt6IR2sBdd+St+GgOOSRYa4qenIoOQ== X-Received: by 2002:a5d:438b:: with SMTP id i11mr9969426wrq.188.1635182238986; Mon, 25 Oct 2021 10:17:18 -0700 (PDT) Received: from srini-hackbox.lan (cpc86377-aztw32-2-0-cust226.18-1.cable.virginm.net. [92.233.226.227]) by smtp.gmail.com with ESMTPSA id r11sm5181012wrt.42.2021.10.25.10.17.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Oct 2021 10:17:18 -0700 (PDT) From: Srinivas Kandagatla To: broonie@kernel.org, bjorn.andersson@linaro.org, robh@kernel.org Cc: plai@codeaurora.org, pierre-louis.bossart@linux.intel.com, tiwai@suse.de, devicetree@vger.kernel.org, perex@perex.cz, alsa-devel@alsa-project.org, lgirdwood@gmail.com, bgoswami@codeaurora.org, Srinivas Kandagatla Subject: [PATCH v10 08/17] ASoC: dt-bindings: add q6apm digital audio stream bindings Date: Mon, 25 Oct 2021 18:16:40 +0100 Message-Id: <20211025171649.17730-9-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20211025171649.17730-1-srinivas.kandagatla@linaro.org> References: <20211025171649.17730-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On AudioReach audio Framework, Audio Streams (PCM/Compressed) are managed by Q6APM(Audio Process Manager) service. This patch adds bindings for this DAIs exposed by the DSP. Signed-off-by: Srinivas Kandagatla Reviewed-by: Rob Herring --- Hi Rob, You might see a dt_binding_check errors as QCOM SoC relevant non-audio patches in this series have been merged into the Qualcomm drivers-for-5.16 tree, as this series depends those patches an immutable tag is available at: https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git tags/20210927135559.738-6-srinivas.kandagatla@linaro.org thanks, srini .../bindings/sound/qcom,q6apm-dai.yaml | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/qcom,q6apm-dai.yaml diff --git a/Documentation/devicetree/bindings/sound/qcom,q6apm-dai.yaml b/Documentation/devicetree/bindings/sound/qcom,q6apm-dai.yaml new file mode 100644 index 000000000000..5d972784321d --- /dev/null +++ b/Documentation/devicetree/bindings/sound/qcom,q6apm-dai.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/sound/qcom,q6apm-dai.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm Audio Process Manager Digital Audio Interfaces binding + +maintainers: + - Srinivas Kandagatla + +description: | + This binding describes the Qualcomm APM DAIs in DSP + +properties: + compatible: + const: qcom,q6apm-dais + + reg: + maxItems: 1 + + iommus: + maxItems: 1 + +required: + - compatible + - iommus + - reg + +additionalProperties: false + +examples: + - | + #include + gpr { + compatible = "qcom,gpr"; + #address-cells = <1>; + #size-cells = <0>; + qcom,domain = ; + service@1 { + compatible = "qcom,q6apm"; + reg = <1>; + + #address-cells = <1>; + #size-cells = <0>; + + apm-dai@1 { + compatible = "qcom,q6apm-dais"; + iommus = <&apps_smmu 0x1801 0x0>; + reg = <1>; + }; + }; + };