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This adds +nosve so that we always generate neon. Regtested on aarch64-none-linux-gnu and no issues. Committed under the obvious rule. Thanks, Tamar gcc/testsuite/ChangeLog: PR target/102907 * gcc.target/aarch64/shrn-combine-1.c: Disable SVE. * gcc.target/aarch64/shrn-combine-2.c: Likewise. * gcc.target/aarch64/shrn-combine-3.c: Likewise. * gcc.target/aarch64/shrn-combine-4.c: Likewise. * gcc.target/aarch64/shrn-combine-5.c: Likewise. * gcc.target/aarch64/shrn-combine-6.c: Likewise. * gcc.target/aarch64/shrn-combine-7.c: Likewise. --- inline copy of patch -- diff --git a/gcc/testsuite/gcc.target/aarch64/shrn-combine-1.c b/gcc/testsuite/gcc.target/aarch64/shrn-combine-1.c index a28524662edca8eb149e34c2242091b51a167b71..334e94aa76e030d18cfbda2febe3200f0ccb7b5e 100644 diff --git a/gcc/testsuite/gcc.target/aarch64/shrn-combine-1.c b/gcc/testsuite/gcc.target/aarch64/shrn-combine-1.c index a28524662edca8eb149e34c2242091b51a167b71..334e94aa76e030d18cfbda2febe3200f0ccb7b5e 100644 --- a/gcc/testsuite/gcc.target/aarch64/shrn-combine-1.c +++ b/gcc/testsuite/gcc.target/aarch64/shrn-combine-1.c @@ -1,6 +1,8 @@ /* { dg-do assemble } */ /* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ +#pragma GCC target "+nosve" + #define TYPE char void foo (unsigned TYPE * restrict a, TYPE * restrict d, int n) diff --git a/gcc/testsuite/gcc.target/aarch64/shrn-combine-2.c b/gcc/testsuite/gcc.target/aarch64/shrn-combine-2.c index 012135b424f98abadc480e7ef13fcab080d99c28..c90de72e9c39e2cac22264004015b4be62c38110 100644 --- a/gcc/testsuite/gcc.target/aarch64/shrn-combine-2.c +++ b/gcc/testsuite/gcc.target/aarch64/shrn-combine-2.c @@ -1,6 +1,8 @@ /* { dg-do assemble } */ /* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ +#pragma GCC target "+nosve" + #define TYPE short void foo (unsigned TYPE * restrict a, TYPE * restrict d, int n) diff --git a/gcc/testsuite/gcc.target/aarch64/shrn-combine-3.c b/gcc/testsuite/gcc.target/aarch64/shrn-combine-3.c index 8b5b360de623b0ada0da1531795ba6b428c7f9e1..a05ecbb373a55d39e07bb1d8f887485d73740638 100644 --- a/gcc/testsuite/gcc.target/aarch64/shrn-combine-3.c +++ b/gcc/testsuite/gcc.target/aarch64/shrn-combine-3.c @@ -1,6 +1,8 @@ /* { dg-do assemble } */ /* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ +#pragma GCC target "+nosve" + #define TYPE int void foo (unsigned long long * restrict a, TYPE * restrict d, int n) diff --git a/gcc/testsuite/gcc.target/aarch64/shrn-combine-4.c b/gcc/testsuite/gcc.target/aarch64/shrn-combine-4.c index fedca7621e2a82df0df9d12b91c5c0c9fd3dfc60..36ebab7b742add831403f6d2000c14f6a7714770 100644 --- a/gcc/testsuite/gcc.target/aarch64/shrn-combine-4.c +++ b/gcc/testsuite/gcc.target/aarch64/shrn-combine-4.c @@ -1,6 +1,8 @@ /* { dg-do assemble } */ /* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ +#pragma GCC target "+nosve" + #define TYPE long long void foo (unsigned TYPE * restrict a, TYPE * restrict d, int n) diff --git a/gcc/testsuite/gcc.target/aarch64/shrn-combine-5.c b/gcc/testsuite/gcc.target/aarch64/shrn-combine-5.c index 408e85535788b2c1c9b05672a269e4e6567f2683..973e577e938198fb8ab5ee8662bb16fa695a6842 100644 --- a/gcc/testsuite/gcc.target/aarch64/shrn-combine-5.c +++ b/gcc/testsuite/gcc.target/aarch64/shrn-combine-5.c @@ -1,6 +1,8 @@ /* { dg-do assemble } */ /* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ +#pragma GCC target "+nosve" + #define TYPE1 char #define TYPE2 short #define SHIFT 8 diff --git a/gcc/testsuite/gcc.target/aarch64/shrn-combine-6.c b/gcc/testsuite/gcc.target/aarch64/shrn-combine-6.c index 6211ba3e41c199f325b80217d298801767c8dad5..db36a9c421815987778d1427be232d9264bf7094 100644 --- a/gcc/testsuite/gcc.target/aarch64/shrn-combine-6.c +++ b/gcc/testsuite/gcc.target/aarch64/shrn-combine-6.c @@ -1,6 +1,8 @@ /* { dg-do assemble } */ /* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ +#pragma GCC target "+nosve" + #define TYPE1 short #define TYPE2 int #define SHIFT 16 diff --git a/gcc/testsuite/gcc.target/aarch64/shrn-combine-7.c b/gcc/testsuite/gcc.target/aarch64/shrn-combine-7.c index 56cbeacc6de54f177f5b66d26b62ba6cefb921ad..e7caf3c7587a7df15889760a2090e3fa264bc66e 100644 --- a/gcc/testsuite/gcc.target/aarch64/shrn-combine-7.c +++ b/gcc/testsuite/gcc.target/aarch64/shrn-combine-7.c @@ -1,6 +1,8 @@ /* { dg-do assemble } */ /* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ +#pragma GCC target "+nosve" + #define TYPE1 int #define TYPE2 long long #define SHIFT 32