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[176.74.57.43]) by smtp.gmail.com with ESMTPSA id k23sm8562822edv.22.2021.10.25.03.33.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Oct 2021 03:33:33 -0700 (PDT) From: Robert Foss To: robert.foss@linaro.org, todor.too@gmail.com, agross@kernel.org, bjorn.andersson@linaro.org, mchehab@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@somainline.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bryan O'Donoghue , Andrey Konovalov Subject: [PATCH v1 1/2] media: dt-bindings: media: camss: sdm845: Make clock-lanes property const Date: Mon, 25 Oct 2021 12:33:21 +0200 Message-Id: <20211025103322.160913-1-robert.foss@linaro.org> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Mistakenly only one out of four CSI ports had the clock-lane marked as const. Signed-off-by: Robert Foss --- .../devicetree/bindings/media/qcom,sdm845-camss.yaml | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/media/qcom,sdm845-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sdm845-camss.yaml index 9ca5dfa7f226..d8fb6ce1d7f9 100644 --- a/Documentation/devicetree/bindings/media/qcom,sdm845-camss.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sdm845-camss.yaml @@ -106,7 +106,8 @@ properties: properties: clock-lanes: - maxItems: 1 + items: + - const: 7 data-lanes: minItems: 1 @@ -153,7 +154,8 @@ properties: properties: clock-lanes: - maxItems: 1 + items: + - const: 7 data-lanes: minItems: 1 @@ -176,7 +178,8 @@ properties: properties: clock-lanes: - maxItems: 1 + items: + - const: 7 data-lanes: minItems: 1 From patchwork Mon Oct 25 10:33:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 1545665 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=cCBifTqp; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4HdBBX2W0nz9shn for ; Mon, 25 Oct 2021 21:33:40 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232916AbhJYKgA (ORCPT ); Mon, 25 Oct 2021 06:36:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41874 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232898AbhJYKf6 (ORCPT ); Mon, 25 Oct 2021 06:35:58 -0400 Received: from mail-ed1-x52d.google.com (mail-ed1-x52d.google.com [IPv6:2a00:1450:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 84E65C061745 for ; Mon, 25 Oct 2021 03:33:36 -0700 (PDT) Received: by mail-ed1-x52d.google.com with SMTP id n1so14490797edd.0 for ; Mon, 25 Oct 2021 03:33:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=uOI455EZK+xQ6LZy+Qgtz7hZ9+hlabcft7bqsTfsnwk=; b=cCBifTqp5lTGiiPTru5INp+kuxdIhhO+7iBanmzoNCcXsDYqhexIozh7ZJv2ObkaT7 iQD8tGoTwk9Ah7ZzYSG6LOq9Oqi6pJHeLlOpuT4kmHPywSmT6X4haChoPun5uczNeuo9 ppd4TGksPNcFIWND4+I6GduIy7Sfu0O7MxxN6/7KxoSZInnHGcl1AC6UpE4kvMPyLx5A sFD+zeZpotsV17S76X6HwWxrBrl1VhjhsY4wof4hIKLRo+3fyPze1dXUEapSF2kyjn92 iozUtCfLCUntocrXvxy1KGf6u0G0Ne//5s/TCrJd76bGT1u0QB59vxKWW6D+sumqcRWq Bbeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uOI455EZK+xQ6LZy+Qgtz7hZ9+hlabcft7bqsTfsnwk=; b=IKBpzLHYN3Ha7mii7jIpQo4YKg1F7dKbVx3Xq3D94DU2wK4Lo/fni3YL9w2jwqBSwQ uu0dF6ZQ0O5x7vS2Hv3yxLRwuactDkI05yxHquYgW2ryUboyCSaqu8h82/cBqq0yxbG0 T/GlwkYvpBD0Ozp+CWiKeYD6fBwUgz+pFiySmEep+q+4BVwqveRs7DXwntiMthvmEEpp NtC0qpf6nR22S+KZXNdcYv2DKxo+qrQggCe2iwR4qNciKcKsrsGyrd3tUA0Ma3qwuisP QVZ/ozAVX7SVhVHiYjg9CbtOYvStvA9Db/72PBboQ6n+BZlXCRGzf6/5mo9/wlv9QXqo YOpQ== X-Gm-Message-State: AOAM532gnqtxd9/2z6zcG8EzPot3zJHH1pswKtV2PD0cKCG7uuoHR+7N q3CedwwEQ3fgM54RwFmKee2+mQ== X-Google-Smtp-Source: ABdhPJzNUmre0eMFNlhEzkvE4eyV03gxzJEOFPUJNWRuPm+Xs6hWK0P9fQUQjgeQXsLQOqdeP21aag== X-Received: by 2002:a50:d4cd:: with SMTP id e13mr25234696edj.29.1635158014975; Mon, 25 Oct 2021 03:33:34 -0700 (PDT) Received: from localhost.localdomain (freifunk-gw.bsa1-cpe1.syseleven.net. [176.74.57.43]) by smtp.gmail.com with ESMTPSA id k23sm8562822edv.22.2021.10.25.03.33.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Oct 2021 03:33:34 -0700 (PDT) From: Robert Foss To: robert.foss@linaro.org, todor.too@gmail.com, agross@kernel.org, bjorn.andersson@linaro.org, mchehab@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@somainline.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bryan O'Donoghue , Andrey Konovalov Subject: [PATCH v1 2/2] media: dt-bindings: media: camss: Document clock-lanes property Date: Mon, 25 Oct 2021 12:33:22 +0200 Message-Id: <20211025103322.160913-2-robert.foss@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211025103322.160913-1-robert.foss@linaro.org> References: <20211025103322.160913-1-robert.foss@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The clock-lanes property corresponds to a hardware register field that is required to be set, in order to enable the CSI clock signal. The physical lane of the clock signal is not programmable, but only togglable On or Off, which what BIT(7) of the CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(5) register controls. Signed-off-by: Robert Foss --- .../devicetree/bindings/media/qcom,msm8996-camss.yaml | 5 +++++ .../devicetree/bindings/media/qcom,sdm660-camss.yaml | 5 +++++ .../devicetree/bindings/media/qcom,sdm845-camss.yaml | 5 +++++ 3 files changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/media/qcom,msm8996-camss.yaml b/Documentation/devicetree/bindings/media/qcom,msm8996-camss.yaml index 38be41e932f0..d4da1fad12cf 100644 --- a/Documentation/devicetree/bindings/media/qcom,msm8996-camss.yaml +++ b/Documentation/devicetree/bindings/media/qcom,msm8996-camss.yaml @@ -106,6 +106,11 @@ properties: properties: clock-lanes: + description: + The index of the clock-lane is not programmable by + the hardware, but is required to define a CSI port. + Lane 7 reflects the hardware register field that enables + the clock lane. items: - const: 7 diff --git a/Documentation/devicetree/bindings/media/qcom,sdm660-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sdm660-camss.yaml index 841a1aafdd13..f110152909b9 100644 --- a/Documentation/devicetree/bindings/media/qcom,sdm660-camss.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sdm660-camss.yaml @@ -112,6 +112,11 @@ properties: properties: clock-lanes: + description: + The index of the clock-lane is not programmable by + the hardware, but is required to define a CSI port. + Lane 7 reflects the hardware register field that enables + the clock lane. items: - const: 7 diff --git a/Documentation/devicetree/bindings/media/qcom,sdm845-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sdm845-camss.yaml index d8fb6ce1d7f9..087d5606f2be 100644 --- a/Documentation/devicetree/bindings/media/qcom,sdm845-camss.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sdm845-camss.yaml @@ -106,6 +106,11 @@ properties: properties: clock-lanes: + description: + The index of the clock-lane is not programmable by + the hardware, but is required to define a CSI port. + Lane 7 reflects the hardware register field that enables + the clock lane. items: - const: 7