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[115.64.153.41]) by smtp.gmail.com with ESMTPSA id z3sm11158058pfe.78.2021.10.02.18.22.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Oct 2021 18:22:18 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sun, 3 Oct 2021 11:22:03 +1000 Message-Id: <20211003012210.1165606-2-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20211003012210.1165606-1-npiggin@gmail.com> References: <20211003012210.1165606-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 1/8] interrupts: add_opal_interrupts avoid NULL dereference on P10 mambo X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" On P10, get_ics_phandle() calls xive2_get_phandle() directly. This results in a NULL dereference on mambo when xive2 is not set up. This was caught with the virtual memory boot patch on P10 mambo. Signed-off-by: Nicholas Piggin Reviewed-by: Cédric Le Goater --- core/interrupts.c | 7 ++++++- hw/xive2.c | 3 +++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/core/interrupts.c b/core/interrupts.c index 5d2d04db5..c39c2801c 100644 --- a/core/interrupts.c +++ b/core/interrupts.c @@ -204,10 +204,15 @@ void add_opal_interrupts(void) { struct irq_source *is; unsigned int i, ns, tns = 0, count = 0; + uint32_t parent; uint32_t isn; __be32 *irqs = NULL; char *names = NULL; + parent = get_ics_phandle(); + if (!parent) + return; + lock(&irq_lock); list_for_each(&irq_sources, is, link) { /* @@ -251,7 +256,7 @@ void add_opal_interrupts(void) /* First create the standard "interrupts" property and the * corresponding names property */ - dt_add_property_cells(opal_node, "interrupt-parent", get_ics_phandle()); + dt_add_property_cells(opal_node, "interrupt-parent", parent); dt_add_property(opal_node, "interrupts", irqs, count * 8); dt_add_property(opal_node, "opal-interrupts-names", names, tns); dt_add_property(opal_node, "interrupt-names", names, tns); diff --git a/hw/xive2.c b/hw/xive2.c index 810ab91d8..0254175a9 100644 --- a/hw/xive2.c +++ b/hw/xive2.c @@ -1977,6 +1977,9 @@ static void xive_create_mmio_dt_node(struct xive *x) uint32_t xive2_get_phandle(void) { + if (!xive_dt_node) + return 0; + return xive_dt_node->phandle; } From patchwork Sun Oct 3 01:22:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1535714 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=KYb5PaOT; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; 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[115.64.153.41]) by smtp.gmail.com with ESMTPSA id z3sm11158058pfe.78.2021.10.02.18.22.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Oct 2021 18:22:20 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sun, 3 Oct 2021 11:22:04 +1000 Message-Id: <20211003012210.1165606-3-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20211003012210.1165606-1-npiggin@gmail.com> References: <20211003012210.1165606-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 2/8] cpu: cpu_idle_job SMT priority fix X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Calling cpu_relax resets the SMT priority to medium, causing the idle loop not to run with lowest priority. Just use barrier() instead, this saves about 3 seconds on a SMT4 systemsim (mambo) boot. Signed-off-by: Nicholas Piggin --- core/cpu.c | 1 - 1 file changed, 1 deletion(-) diff --git a/core/cpu.c b/core/cpu.c index f58aeb27a..5c10fc6e8 100644 --- a/core/cpu.c +++ b/core/cpu.c @@ -547,7 +547,6 @@ void cpu_idle_job(void) while (!cpu_check_jobs(cpu)) { if (pm_enabled) break; - cpu_relax(); barrier(); } smt_medium(); From patchwork Sun Oct 3 01:22:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1535715 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=nVKRwhKu; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2404:9400:2:0:216:3eff:fee1:b9f1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4HMR121n1Vz9t0p for ; Sun, 3 Oct 2021 12:22:46 +1100 (AEDT) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4HMR120gVkz2yQB for ; Sun, 3 Oct 2021 12:22:46 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=nVKRwhKu; dkim-atps=neutral X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::436; helo=mail-pf1-x436.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=nVKRwhKu; dkim-atps=neutral Received: from mail-pf1-x436.google.com (mail-pf1-x436.google.com [IPv6:2607:f8b0:4864:20::436]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4HMR0c3d6Lz2yHW for ; Sun, 3 Oct 2021 12:22:24 +1100 (AEDT) Received: by mail-pf1-x436.google.com with SMTP id k26so11344180pfi.5 for ; Sat, 02 Oct 2021 18:22:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OVnJ1eJCKwZn4ypqqFjg1JkbIQW7bpHMIRuGDvM58Fo=; b=nVKRwhKuaWHIemyG7dPT1WunGgbg8VmOK/CYxAM1lk2WzsKQRlrX8ZWV8bVkjbzzUM riGwWrl2/yv68epJWczYQP/Iv5LtieD2g7LY1UKRIic0pNYlc8atWj7RNoSVYrLbKhQ6 WISi2Q/hhjs9iWmXOroYlarm79aPZ2nsxRnmqf+iSVyCfXYv6mZR0IU9EG2vBeRZ0odG htTIFrIxCtU2ZlxsOamCXP6uKDcD9ms2Fnj/KiwaufRRUvX9Gs0+me/yiAOU2dJitNO4 ssvAOqkoL5l8Itfbif/wA9O0tMZZY6yqv+BEy9JqgKsoj33atoUc72VarT8T6eDxivfa E1YQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OVnJ1eJCKwZn4ypqqFjg1JkbIQW7bpHMIRuGDvM58Fo=; b=n27e2er1k/7Xt3MZhTPpeiuKT9ACCdrurxmMcCxUvAt+xo45PLvQoTlxO/bUaQwwRz vzh9bwYPAkw7F58f1rxZkngUZdAizlPpKtoyv5Pkl9ZYwdgxGKw1ATB8YKL8Q3In6kXu ATlPcfjB4QEoeXIUz8bg/leLo/kReWSkgEdNjzHSHAuIFc5gBlX5QNC7xsjKqxo4r3/x YYviLUDmvuS8z/OrlLceM/Edbi4Umh+7wkzhImGrXDiwSiy1NypqBTwlEWxVY54G4iC9 qArMNGBP31mB1PR9RVNakd1M/tJPOfw5Ua4Gf7/KNCMhX8M6E7BNLR+HwxsNIN2rt24B AfmQ== X-Gm-Message-State: AOAM531j/XoG3H8mXl8A3JO34Hb7l6PWkui1ajJkUff2h4T1WORZajFO Q8bSi4JIIFYKR7RfPxKFv3wNwPtAe/s= X-Google-Smtp-Source: ABdhPJxNF3LbXE7yOSHdP5tGW/cRc8iwjoTeI29+6QGc7FTLs+9AQ21RC1uYLA6YiPhvN7+aG9aFZQ== X-Received: by 2002:a05:6a00:9a:b0:44b:b8f9:1d72 with SMTP id c26-20020a056a00009a00b0044bb8f91d72mr17902035pfj.21.1633224142109; Sat, 02 Oct 2021 18:22:22 -0700 (PDT) Received: from bobo.ibm.com (115-64-153-41.tpgi.com.au. [115.64.153.41]) by smtp.gmail.com with ESMTPSA id z3sm11158058pfe.78.2021.10.02.18.22.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Oct 2021 18:22:21 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sun, 3 Oct 2021 11:22:05 +1000 Message-Id: <20211003012210.1165606-4-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20211003012210.1165606-1-npiggin@gmail.com> References: <20211003012210.1165606-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 3/8] cpu: add debug check in cpu_relax X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" If cpu_relax() is called when not at medium SMT priority, it will lose the prior priority and return at medium. Add a debug check to catch this, which would have flagged the previous bug. Signed-off-by: Nicholas Piggin --- core/cpu.c | 6 ++++++ include/processor.h | 1 + 2 files changed, 7 insertions(+) diff --git a/core/cpu.c b/core/cpu.c index 5c10fc6e8..0f2da1524 100644 --- a/core/cpu.c +++ b/core/cpu.c @@ -80,6 +80,12 @@ unsigned long __attrconst cpu_emergency_stack_top(unsigned int pir) void __nomcount cpu_relax(void) { + if ((mfspr(SPR_PPR32) >> 18) != 0x4) { + printf("cpu_relax called when not at medium SMT priority: " + "PPR[PRI]=0x%lx\n", mfspr(SPR_PPR32) >> 18); + backtrace(); + } + /* Relax a bit to give sibling threads some breathing space */ smt_lowest(); asm volatile("nop; nop; nop; nop;\n" diff --git a/include/processor.h b/include/processor.h index 973d7e77b..7a9c49994 100644 --- a/include/processor.h +++ b/include/processor.h @@ -71,6 +71,7 @@ #define SPR_USRR1 0x1fb /* RW: Ultravisor Save/Restore Register 1 */ #define SPR_SMFCTRL 0x1ff /* RW: Secure Memory Facility Control */ #define SPR_PSSCR 0x357 /* RW: Stop status and control (ISA 3) */ +#define SPR_PPR32 0x382 #define SPR_TSCR 0x399 #define SPR_HID0 0x3f0 #define SPR_HID1 0x3f1 From patchwork Sun Oct 3 01:22:06 2021 Content-Type: text/plain; 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[115.64.153.41]) by smtp.gmail.com with ESMTPSA id z3sm11158058pfe.78.2021.10.02.18.22.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Oct 2021 18:22:23 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sun, 3 Oct 2021 11:22:06 +1000 Message-Id: <20211003012210.1165606-5-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20211003012210.1165606-1-npiggin@gmail.com> References: <20211003012210.1165606-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 4/8] asm/head: Fix P10 HILE for little endian build X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Fixes: 891ed8df67 ("Initial POWER10 enablement") Signed-off-by: Nicholas Piggin --- asm/head.S | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/asm/head.S b/asm/head.S index fa8933b14..b2755344d 100644 --- a/asm/head.S +++ b/asm/head.S @@ -829,8 +829,13 @@ init_shared_sprs: /* HID0: * Boot with PPC_BIT(5) set (dis_recovery). * Leave bit 5 set to disable recovery (due to HW570622) + * Set/clear bit 4 (HILE) depending on skiboot endian */ +#if HAVE_BIG_ENDIAN LOAD_IMM64(%r3, PPC_BIT(5)) +#else + LOAD_IMM64(%r3, PPC_BIT(5) | PPC_BIT(4)) +#endif sync mtspr SPR_HID0,%r3 isync From patchwork Sun Oct 3 01:22:07 2021 Content-Type: text/plain; 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[115.64.153.41]) by smtp.gmail.com with ESMTPSA id z3sm11158058pfe.78.2021.10.02.18.22.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Oct 2021 18:22:25 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sun, 3 Oct 2021 11:22:07 +1000 Message-Id: <20211003012210.1165606-6-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20211003012210.1165606-1-npiggin@gmail.com> References: <20211003012210.1165606-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 5/8] phb4: annotate tbl_pest with endian types X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Nicholas Piggin --- hw/phb4.c | 19 +++++++------------ include/phb4.h | 2 +- 2 files changed, 8 insertions(+), 13 deletions(-) diff --git a/hw/phb4.c b/hw/phb4.c index 8bd3aa5f5..4daad148a 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -1883,7 +1883,6 @@ static void phb4_read_phb_status(struct phb4 *p, struct OpalIoPhb4ErrorData *stat) { uint32_t i; - __be64 *pPEST; uint16_t __16; uint32_t __32; uint64_t __64; @@ -2005,17 +2004,16 @@ static void phb4_read_phb_status(struct phb4 *p, * be fetched from IODA and the left content from memory * resident tables. */ - pPEST = (__be64 *)p->tbl_pest; phb4_ioda_sel(p, IODA3_TBL_PESTA, 0, true); for (i = 0; i < p->max_num_pes; i++) { stat->pestA[i] = cpu_to_be64(phb4_read_reg_asb(p, PHB_IODA_DATA0)); - stat->pestA[i] |= pPEST[2 * i]; + stat->pestA[i] |= p->tbl_pest[2 * i]; } phb4_ioda_sel(p, IODA3_TBL_PESTB, 0, true); for (i = 0; i < p->max_num_pes; i++) { stat->pestB[i] = cpu_to_be64(phb4_read_reg_asb(p, PHB_IODA_DATA0)); - stat->pestB[i] |= pPEST[2 * i + 1]; + stat->pestB[i] |= p->tbl_pest[2 * i + 1]; } } @@ -3739,14 +3737,11 @@ static void phb4_int_mask_active(struct phb4 *p) static uint64_t phb4_get_pesta(struct phb4 *p, uint64_t pe_number) { uint64_t pesta; - __be64 *pPEST; - - pPEST = (__be64 *)p->tbl_pest; phb4_ioda_sel(p, IODA3_TBL_PESTA, pe_number, false); pesta = phb4_read_reg(p, PHB_IODA_DATA0); if (pesta & IODA3_PESTA_MMIO_FROZEN) - pesta |= be64_to_cpu(pPEST[2*pe_number]); + pesta |= be64_to_cpu(p->tbl_pest[2*pe_number]); return pesta; } @@ -5189,7 +5184,7 @@ static void phb4_init_ioda3(struct phb4 *p) /* Init_23 - Setup PEST BAR */ out_be64(p->regs + PHB_PEST_BAR, - p->tbl_pest | PHB_PEST_BAR_ENABLE); + (u64)p->tbl_pest | PHB_PEST_BAR_ENABLE); /* Init_24 - CRW Base Address Reg */ /* See enable_capi_mode() */ @@ -5712,9 +5707,9 @@ static void phb4_allocate_tables(struct phb4 *p) assert(p->tbl_peltv); memset(p->tbl_peltv, 0, p->tbl_peltv_size); - p->tbl_pest = (uint64_t)local_alloc(p->chip_id, p->tbl_pest_size, p->tbl_pest_size); + p->tbl_pest = local_alloc(p->chip_id, p->tbl_pest_size, p->tbl_pest_size); assert(p->tbl_pest); - memset((void *)p->tbl_pest, 0, p->tbl_pest_size); + memset(p->tbl_pest, 0, p->tbl_pest_size); } static void phb4_add_properties(struct phb4 *p) @@ -5822,7 +5817,7 @@ static void phb4_add_properties(struct phb4 *p) p->tbl_peltv_size); dt_add_property_cells(np, "ibm,opal-pest-table", - hi32(p->tbl_pest), lo32(p->tbl_pest), p->tbl_pest_size); + hi32((u64)p->tbl_pest), lo32((u64)p->tbl_pest), p->tbl_pest_size); dt_add_property_cells(np, "ibm,phb-diag-data-size", sizeof(struct OpalIoPhb4ErrorData)); diff --git a/include/phb4.h b/include/phb4.h index 4f1fb31c5..29864d28e 100644 --- a/include/phb4.h +++ b/include/phb4.h @@ -186,7 +186,7 @@ struct phb4 { __be16 *tbl_rtt; uint8_t *tbl_peltv; uint64_t tbl_peltv_size; - uint64_t tbl_pest; + __be64 *tbl_pest; uint64_t tbl_pest_size; bool skip_perst; /* Skip first perst */ From patchwork Sun Oct 3 01:22:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1535718 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=Nwb5Hr48; dkim-atps=neutral Authentication-Results: ozlabs.org; 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[115.64.153.41]) by smtp.gmail.com with ESMTPSA id z3sm11158058pfe.78.2021.10.02.18.22.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Oct 2021 18:22:28 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sun, 3 Oct 2021 11:22:08 +1000 Message-Id: <20211003012210.1165606-7-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20211003012210.1165606-1-npiggin@gmail.com> References: <20211003012210.1165606-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 6/8] Remove support for POWER8 DD1 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This significantly simplifies the SLW code. HILE is now always supported. Reviewed-by: Stewart Smith Signed-off-by: Nicholas Piggin --- core/cpu.c | 23 ++-- hw/phb3.c | 68 ++-------- hw/slw.c | 323 ---------------------------------------------- include/phb3.h | 2 +- include/skiboot.h | 5 - 5 files changed, 22 insertions(+), 399 deletions(-) diff --git a/core/cpu.c b/core/cpu.c index 0f2da1524..d11d7f9bc 100644 --- a/core/cpu.c +++ b/core/cpu.c @@ -35,7 +35,6 @@ unsigned int cpu_thread_count; unsigned int cpu_max_pir; struct cpu_thread *boot_cpu; static struct lock reinit_lock = LOCK_UNLOCKED; -static bool hile_supported; static bool radix_supported; static unsigned long hid0_hile; static unsigned long hid0_attn; @@ -1004,27 +1003,23 @@ void init_boot_cpu(void) case PVR_TYPE_P8E: case PVR_TYPE_P8: proc_gen = proc_gen_p8; - hile_supported = PVR_VERS_MAJ(mfspr(SPR_PVR)) >= 2; hid0_hile = SPR_HID0_POWER8_HILE; hid0_attn = SPR_HID0_POWER8_ENABLE_ATTN; break; case PVR_TYPE_P8NVL: proc_gen = proc_gen_p8; - hile_supported = true; hid0_hile = SPR_HID0_POWER8_HILE; hid0_attn = SPR_HID0_POWER8_ENABLE_ATTN; break; case PVR_TYPE_P9: case PVR_TYPE_P9P: proc_gen = proc_gen_p9; - hile_supported = true; radix_supported = true; hid0_hile = SPR_HID0_POWER9_HILE; hid0_attn = SPR_HID0_POWER9_ENABLE_ATTN; break; case PVR_TYPE_P10: proc_gen = proc_gen_p10; - hile_supported = true; radix_supported = true; hid0_hile = SPR_HID0_POWER10_HILE; hid0_attn = SPR_HID0_POWER10_ENABLE_ATTN; @@ -1061,6 +1056,11 @@ void init_boot_cpu(void) cpu_thread_count = 1; } + if (proc_gen == proc_gen_p8 && (PVR_VERS_MAJ(mfspr(SPR_PVR)) == 1)) { + prerror("CPU: POWER8 DD1 is not supported\n"); + abort(); + } + if (is_power9n(pvr) && (PVR_VERS_MAJ(pvr) == 1)) { prerror("CPU: POWER9N DD1 is not supported\n"); abort(); @@ -1602,7 +1602,7 @@ static int64_t opal_reinit_cpus(uint64_t flags) } /* * Now we need to mark ourselves "active" or we'll be skipped - * by the various "for_each_active_..." calls done by slw_reinit() + * by the various "for_each_active_..." */ this_cpu()->state = cpu_state_active; this_cpu()->in_reinit = true; @@ -1616,10 +1616,8 @@ static int64_t opal_reinit_cpus(uint64_t flags) */ cpu_cleanup_all(); - /* If HILE change via HID0 is supported ... */ - if (hile_supported && - (flags & (OPAL_REINIT_CPUS_HILE_BE | - OPAL_REINIT_CPUS_HILE_LE))) { + if (flags & (OPAL_REINIT_CPUS_HILE_BE | + OPAL_REINIT_CPUS_HILE_LE)) { bool hile = !!(flags & OPAL_REINIT_CPUS_HILE_LE); flags &= ~(OPAL_REINIT_CPUS_HILE_BE | OPAL_REINIT_CPUS_HILE_LE); @@ -1674,10 +1672,7 @@ static int64_t opal_reinit_cpus(uint64_t flags) rc = OPAL_SUCCESS; } - /* Handle P8 DD1 SLW reinit */ - if (flags != 0 && proc_gen == proc_gen_p8 && !hile_supported) - rc = slw_reinit(flags); - else if (flags != 0) + if (flags != 0) rc = OPAL_UNSUPPORTED; /* And undo the above */ diff --git a/hw/phb3.c b/hw/phb3.c index 8af6b6164..aeeb6b655 100644 --- a/hw/phb3.c +++ b/hw/phb3.c @@ -444,7 +444,6 @@ static void phb3_switch_port_init(struct phb *phb, struct pci_device *dev, int ecap, int aercap) { - struct phb3 *p = phb_to_phb3(phb); uint16_t bdfn = dev->bdfn; uint16_t val16; uint32_t val32; @@ -498,17 +497,8 @@ static void phb3_switch_port_init(struct phb *phb, PCIECAP_AER_UE_SEVERITY_INTERNAL); pci_cfg_write32(phb, bdfn, aercap + PCIECAP_AER_UE_SEVERITY, val32); - /* - * Mask various correctable errors - * - * On Murano and Venice DD1.0 we disable emission of corrected - * error messages to the PHB completely to workaround errata - * HW257476 causing the loss of tags. - */ - if (p->rev < PHB3_REV_MURANO_DD20) - val32 = 0xffffffff; - else - val32 = PCIECAP_AER_CE_MASK_ADV_NONFATAL; + /* Mask various correctable errors */ + val32 = PCIECAP_AER_CE_MASK_ADV_NONFATAL; pci_cfg_write32(phb, bdfn, aercap + PCIECAP_AER_CE_MASK, val32); /* Enable ECRC generation and disable ECRC check */ @@ -522,7 +512,6 @@ static void phb3_endpoint_init(struct phb *phb, struct pci_device *dev, int ecap, int aercap) { - struct phb3 *p = phb_to_phb3(phb); uint16_t bdfn = dev->bdfn; uint16_t val16; uint32_t val32; @@ -544,15 +533,6 @@ static void phb3_endpoint_init(struct phb *phb, val16 &= ~PCICAP_EXP_DEVCTL_CE_REPORT; pci_cfg_write16(phb, bdfn, ecap + PCICAP_EXP_DEVCTL, val16); - /* - * On Murano and Venice DD1.0 we disable emission of corrected - * error messages to the PHB completely to workaround errata - * HW257476 causing the loss of tags. - */ - if (p->rev < PHB3_REV_MURANO_DD20) - pci_cfg_write32(phb, bdfn, aercap + PCIECAP_AER_CE_MASK, - 0xffffffff); - /* Enable ECRC generation and check */ pci_cfg_read32(phb, bdfn, aercap + PCIECAP_AER_CAPCTL, &val32); val32 |= (PCIECAP_AER_CAPCTL_ECRCG_EN | @@ -855,11 +835,9 @@ static int64_t phb3_ioda_reset(struct phb *phb, bool purge) out_be64(p->regs + PHB_TCE_KILL, PHB_TCE_KILL_ALL); /* Clear RBA */ - if (p->rev >= PHB3_REV_MURANO_DD20) { - phb3_ioda_sel(p, IODA2_TBL_RBA, 0, true); - for (i = 0; i < 32; i++) - out_be64(p->regs + PHB_IODA_DATA0, 0x0ul); - } + phb3_ioda_sel(p, IODA2_TBL_RBA, 0, true); + for (i = 0; i < 32; i++) + out_be64(p->regs + PHB_IODA_DATA0, 0x0ul); /* Clear PEST & PEEV */ for (i = 0; i < PHB3_MAX_PE_NUM; i++) { @@ -3926,11 +3904,7 @@ static void phb3_init_ioda2(struct phb3 *p) /* DD2.0 or the subsequent chips don't have memory * resident RBA. */ - if (p->rev >= PHB3_REV_MURANO_DD20) - out_be64(p->regs + PHB_RBA_BAR, 0x0ul); - else - out_be64(p->regs + PHB_RBA_BAR, - p->tbl_rba | PHB_RBA_BAR_ENABLE); + out_be64(p->regs + PHB_RBA_BAR, 0x0ul); /* Init_18..21 - Setup M32 */ out_be64(p->regs + PHB_M32_BASE_ADDR, p->mm1_base); @@ -3952,7 +3926,7 @@ static void phb3_init_ioda2(struct phb3 *p) else if (p->rev >= PHB3_REV_MURANO_DD20) out_be64(p->regs + PHB_INTREP_TIMER, 0x0004000000000000UL); else - out_be64(p->regs + PHB_INTREP_TIMER, 0); + assert(0); // DD1 not supported /* Init_25 - PHB3 Configuration Register. Clear TCE cache then * configure the PHB @@ -4225,16 +4199,7 @@ static void phb3_init_errors(struct phb3 *p) out_be64(p->regs + PHB_INB_ERR1_STATUS, 0x0000000000000000UL); out_be64(p->regs + PHB_INB_ERR_LEM_ENABLE, 0xffffffffffffffffUL); - /* - * Workaround for errata HW257476, turn correctable messages into - * ER freezes on Murano and Venice DD1.0 - */ - if (p->rev < PHB3_REV_MURANO_DD20) - out_be64(p->regs + PHB_INB_ERR_FREEZE_ENABLE, - 0x0000600000000070UL); - else - out_be64(p->regs + PHB_INB_ERR_FREEZE_ENABLE, - 0x0000600000000060UL); + out_be64(p->regs + PHB_INB_ERR_FREEZE_ENABLE, 0x0000600000000060UL); out_be64(p->regs + PHB_INB_ERR_AIB_FENCE_ENABLE, 0xfcff80fbff7ff08cUL); out_be64(p->regs + PHB_INB_ERR_LOG_0, 0x0000000000000000UL); @@ -4381,12 +4346,10 @@ static void phb3_init_hw(struct phb3 *p, bool first_init) * Enable IVC for Murano DD2.0 or later one */ #ifdef IVT_TABLE_IVE_16B - val = 0xf3a80e4b00000000UL; + val = 0xf3a80e5b00000000UL; #else - val = 0xf3a80ecb00000000UL; + val = 0xf3a80edb00000000UL; #endif - if (p->rev >= PHB3_REV_MURANO_DD20) - val |= 0x0000010000000000UL; if (first_init && p->rev >= PHB3_REV_NAPLES_DD10) { /* Enable 32-bit bypass support on Naples and tell the OS * about it @@ -4451,10 +4414,7 @@ static void phb3_init_hw(struct phb3 *p, bool first_init) * Murano DD2.0 and later but lacks sufficient testing. We will re-enable * it once that has been done. */ - if (p->rev >= PHB3_REV_MURANO_DD20) - out_be64(p->regs + PHB_TCE_SPEC_CTL, 0xf000000000000000UL); - else - out_be64(p->regs + PHB_TCE_SPEC_CTL, 0x0ul); + out_be64(p->regs + PHB_TCE_SPEC_CTL, 0xf000000000000000UL); /* Errata#20131017: avoid TCE queue overflow */ if (p->rev == PHB3_REV_MURANO_DD20) @@ -4508,10 +4468,6 @@ static void phb3_allocate_tables(struct phb3 *p) p->tbl_ivt = (uint64_t)local_alloc(p->chip_id, IVT_TABLE_SIZE, IVT_TABLE_SIZE); assert(p->tbl_ivt); memset((void *)p->tbl_ivt, 0, IVT_TABLE_SIZE); - - p->tbl_rba = (uint64_t)local_alloc(p->chip_id, RBA_TABLE_SIZE, RBA_TABLE_SIZE); - assert(p->tbl_rba); - memset((void *)p->tbl_rba, 0, RBA_TABLE_SIZE); } static void phb3_add_properties(struct phb3 *p) @@ -4610,7 +4566,7 @@ static void phb3_add_properties(struct phb3 *p) dt_add_property_cells(np, "ibm,opal-ive-stride", IVT_TABLE_STRIDE); dt_add_property_cells(np, "ibm,opal-rba-table", - hi32(p->tbl_rba), lo32(p->tbl_rba), RBA_TABLE_SIZE); + 0, 0, 0); dt_add_property_cells(np, "ibm,phb-diag-data-size", sizeof(struct OpalIoPhb3ErrorData)); diff --git a/hw/slw.c b/hw/slw.c index 56ba05b0a..178ee4f85 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -29,10 +29,6 @@ #include #include -static uint32_t slw_saved_reset[0x100]; - -static bool slw_current_le = false; - enum wakeup_engine_states wakeup_engine_state = WAKEUP_ENGINE_NOT_PRESENT; bool has_deep_states = false; @@ -52,125 +48,6 @@ DEFINE_LOG_ENTRY(OPAL_RC_SLW_REG, OPAL_PLATFORM_ERR_EVT, OPAL_SLW, OPAL_PLATFORM_FIRMWARE, OPAL_INFO, OPAL_NA); -static void slw_do_rvwinkle(void *data) -{ - struct cpu_thread *cpu = this_cpu(); - struct cpu_thread *master = data; - uint64_t lpcr = mfspr(SPR_LPCR); - struct proc_chip *chip; - - /* Setup our ICP to receive IPIs */ - icp_prep_for_pm(); - - /* Setup LPCR to wakeup on external interrupts only */ - mtspr(SPR_LPCR, ((lpcr & ~SPR_LPCR_P8_PECE) | SPR_LPCR_P8_PECE2)); - isync(); - - prlog(PR_DEBUG, "SLW: CPU PIR 0x%04x going to rvwinkle...\n", - cpu->pir); - - /* Tell that we got it */ - cpu->state = cpu_state_rvwinkle; - - enter_p8_pm_state(1); - - /* Restore SPRs */ - init_shared_sprs(); - init_replicated_sprs(); - - /* Ok, it's ours again */ - cpu->state = cpu_state_active; - - prlog(PR_DEBUG, "SLW: CPU PIR 0x%04x woken up !\n", cpu->pir); - - /* Cleanup our ICP */ - reset_cpu_icp(); - - /* Resync timebase */ - chiptod_wakeup_resync(); - - /* Restore LPCR */ - mtspr(SPR_LPCR, lpcr); - isync(); - - /* If we are passed a master pointer we are the designated - * waker, let's proceed. If not, return, we are finished. - */ - if (!master) - return; - - prlog(PR_DEBUG, "SLW: CPU PIR 0x%04x waiting for master...\n", - cpu->pir); - - /* Allriiiight... now wait for master to go down */ - while(master->state != cpu_state_rvwinkle) - sync(); - - /* XXX Wait one second ! (should check xscom state ? ) */ - time_wait_ms(1000); - - for_each_chip(chip) { - struct cpu_thread *c; - uint64_t tmp; - for_each_available_core_in_chip(c, chip->id) { - xscom_read(chip->id, - XSCOM_ADDR_P8_EX_SLAVE(pir_to_core_id(c->pir), - EX_PM_IDLE_STATE_HISTORY_PHYP), - &tmp); - prlog(PR_TRACE, "SLW: core %x:%x" - " history: 0x%016llx (mid2)\n", - chip->id, pir_to_core_id(c->pir), - tmp); - } - } - - prlog(PR_DEBUG, "SLW: Waking master (PIR 0x%04x)...\n", master->pir); - - /* Now poke all the secondary threads on the master's core */ - for_each_cpu(cpu) { - if (!cpu_is_sibling(cpu, master) || (cpu == master)) - continue; - icp_kick_cpu(cpu); - - /* Wait for it to claim to be back (XXX ADD TIMEOUT) */ - while(cpu->state != cpu_state_active) - sync(); - } - - /* Now poke the master and be gone */ - icp_kick_cpu(master); -} - -static void slw_patch_reset(void) -{ - uint32_t *src, *dst, *sav; - - src = &reset_patch_start; - dst = (uint32_t *)0x100; - sav = slw_saved_reset; - while(src < &reset_patch_end) { - *(sav++) = *(dst); - *(dst++) = *(src++); - } - sync_icache(); -} - -static void slw_unpatch_reset(void) -{ - extern uint32_t reset_patch_start; - extern uint32_t reset_patch_end; - uint32_t *src, *dst, *sav; - - src = &reset_patch_start; - dst = (uint32_t *)0x100; - sav = slw_saved_reset; - while(src < &reset_patch_end) { - *(dst++) = *(sav++); - src++; - } - sync_icache(); -} - static bool slw_general_init(struct proc_chip *chip, struct cpu_thread *c) { uint32_t core = pir_to_core_id(c->pir); @@ -274,15 +151,6 @@ static bool slw_set_overrides_p9(struct proc_chip *chip, struct cpu_thread *c) return true; } -static bool slw_unset_overrides(struct proc_chip *chip, struct cpu_thread *c) -{ - uint32_t core = pir_to_core_id(c->pir); - - /* XXX FIXME: Save and restore the overrides */ - prlog(PR_DEBUG, "SLW: slw_unset_overrides %x:%x\n", chip->id, core); - return true; -} - static bool slw_set_idle_mode(struct proc_chip *chip, struct cpu_thread *c) { uint32_t core = pir_to_core_id(c->pir); @@ -1201,197 +1069,6 @@ void add_cpu_idle_state_properties(void) free(pm_ctrl_reg_mask_buf); } -static void slw_cleanup_core(struct proc_chip *chip, struct cpu_thread *c) -{ - uint64_t tmp; - int rc; - - /* Display history to check transition */ - rc = xscom_read(chip->id, - XSCOM_ADDR_P8_EX_SLAVE(pir_to_core_id(c->pir), - EX_PM_IDLE_STATE_HISTORY_PHYP), - &tmp); - if (rc) { - log_simple_error(&e_info(OPAL_RC_SLW_GET), - "SLW: Failed to read PM_IDLE_STATE_HISTORY\n"); - /* XXX error handling ? return false; */ - } - - prlog(PR_DEBUG, "SLW: core %x:%x history: 0x%016llx (new1)\n", - chip->id, pir_to_core_id(c->pir), tmp); - - rc = xscom_read(chip->id, - XSCOM_ADDR_P8_EX_SLAVE(pir_to_core_id(c->pir), - EX_PM_IDLE_STATE_HISTORY_PHYP), - &tmp); - if (rc) { - log_simple_error(&e_info(OPAL_RC_SLW_GET), - "SLW: Failed to read PM_IDLE_STATE_HISTORY\n"); - /* XXX error handling ? return false; */ - } - - prlog(PR_DEBUG, "SLW: core %x:%x history: 0x%016llx (new2)\n", - chip->id, pir_to_core_id(c->pir), tmp); - - /* - * XXX FIXME: Error out if the transition didn't reach rvwinkle ? - */ - - /* - * XXX FIXME: We should restore a bunch of the EX bits we - * overwrite to sane values here - */ - slw_unset_overrides(chip, c); -} - -static void slw_cleanup_chip(struct proc_chip *chip) -{ - struct cpu_thread *c; - - for_each_available_core_in_chip(c, chip->id) - slw_cleanup_core(chip, c); -} - -static void slw_patch_scans(struct proc_chip *chip, bool le_mode) -{ - int64_t rc; - uint64_t old_val, new_val; - - rc = sbe_xip_get_scalar((void *)chip->slw_base, - "skip_ex_override_ring_scans", &old_val); - if (rc) { - log_simple_error(&e_info(OPAL_RC_SLW_REG), - "SLW: Failed to read scan override on chip %d\n", - chip->id); - return; - } - - new_val = le_mode ? 0 : 1; - - prlog(PR_TRACE, "SLW: Chip %d, LE value was: %lld, setting to %lld\n", - chip->id, old_val, new_val); - - rc = sbe_xip_set_scalar((void *)chip->slw_base, - "skip_ex_override_ring_scans", new_val); - if (rc) { - log_simple_error(&e_info(OPAL_RC_SLW_REG), - "SLW: Failed to set LE mode on chip %d\n", chip->id); - return; - } -} - -int64_t slw_reinit(uint64_t flags) -{ - struct proc_chip *chip; - struct cpu_thread *cpu; - bool has_waker = false; - bool target_le = slw_current_le; - - if (flags & OPAL_REINIT_CPUS_HILE_BE) - target_le = false; - if (flags & OPAL_REINIT_CPUS_HILE_LE) - target_le = true; - - prlog(PR_TRACE, "SLW Reinit from CPU PIR 0x%04x," - " HILE set to %s endian...\n", - this_cpu()->pir, - target_le ? "little" : "big"); - - /* Prepare chips/cores for rvwinkle */ - for_each_chip(chip) { - if (!chip->slw_base) { - log_simple_error(&e_info(OPAL_RC_SLW_INIT), - "SLW: Not found on chip %d\n", chip->id); - return OPAL_HARDWARE; - } - - slw_patch_scans(chip, target_le); - } - slw_current_le = target_le; - - /* XXX Save HIDs ? Or do that in head.S ... */ - - slw_patch_reset(); - - /* rvwinkle everybody and pick one to wake me once I rvwinkle myself */ - for_each_available_cpu(cpu) { - struct cpu_thread *master = NULL; - - if (cpu == this_cpu()) - continue; - - /* Pick up a waker for myself: it must not be a sibling of - * the current CPU and must be a thread 0 (so it gets to - * sync its timebase before doing time_wait_ms() - */ - if (!has_waker && !cpu_is_sibling(cpu, this_cpu()) && - cpu_is_thread0(cpu)) { - has_waker = true; - master = this_cpu(); - } - __cpu_queue_job(cpu, "slw_do_rvwinkle", - slw_do_rvwinkle, master, true); - - /* Wait for it to claim to be down */ - while(cpu->state != cpu_state_rvwinkle) - sync(); - } - - /* XXX Wait one second ! (should check xscom state ? ) */ - prlog(PR_TRACE, "SLW: Waiting one second...\n"); - time_wait_ms(1000); - prlog(PR_TRACE, "SLW: Done.\n"); - - for_each_chip(chip) { - struct cpu_thread *c; - uint64_t tmp; - for_each_available_core_in_chip(c, chip->id) { - xscom_read(chip->id, - XSCOM_ADDR_P8_EX_SLAVE(pir_to_core_id(c->pir), - EX_PM_IDLE_STATE_HISTORY_PHYP), - &tmp); - prlog(PR_DEBUG, "SLW: core %x:%x" - " history: 0x%016llx (mid)\n", - chip->id, pir_to_core_id(c->pir), tmp); - } - } - - - /* Wake everybody except on my core */ - for_each_cpu(cpu) { - if (cpu->state != cpu_state_rvwinkle || - cpu_is_sibling(cpu, this_cpu())) - continue; - icp_kick_cpu(cpu); - - /* Wait for it to claim to be back (XXX ADD TIMEOUT) */ - while(cpu->state != cpu_state_active) - sync(); - } - - /* Did we find a waker ? If we didn't, that means we had no - * other core in the system, we can't do it - */ - if (!has_waker) { - prlog(PR_TRACE, "SLW: No candidate waker, giving up !\n"); - return OPAL_HARDWARE; - } - - /* Our siblings are rvwinkling, and our waker is waiting for us - * so let's just go down now - */ - slw_do_rvwinkle(NULL); - - slw_unpatch_reset(); - - for_each_chip(chip) - slw_cleanup_chip(chip); - - prlog(PR_TRACE, "SLW Reinit complete !\n"); - - return OPAL_SUCCESS; -} - static void slw_patch_regs(struct proc_chip *chip) { struct cpu_thread *c; diff --git a/include/phb3.h b/include/phb3.h index c8a605f11..447e667cd 100644 --- a/include/phb3.h +++ b/include/phb3.h @@ -122,6 +122,7 @@ /* RBA Table : 256 bytes - Reject Bit Array * * 2048 interrupts, 1 bit each, indiates the reject state of interrupts + * Not used (Murano / Venice DD1 only) */ #define RBA_TABLE_SIZE 0x100 @@ -217,7 +218,6 @@ struct phb3 { uint64_t tbl_peltv; uint64_t tbl_pest; uint64_t tbl_ivt; - uint64_t tbl_rba; bool skip_perst; /* Skip first perst */ bool has_link; diff --git a/include/skiboot.h b/include/skiboot.h index df11934f6..abb1ab71c 100644 --- a/include/skiboot.h +++ b/include/skiboot.h @@ -310,11 +310,6 @@ extern enum wakeup_engine_states wakeup_engine_state; extern bool has_deep_states; extern void nx_p9_rng_late_init(void); - - -/* SLW reinit function for switching core settings */ -extern int64_t slw_reinit(uint64_t flags); - /* Patch SPR in SLW image */ extern int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val); From patchwork Sun Oct 3 01:22:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1535719 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=e0NVl4sz; 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[115.64.153.41]) by smtp.gmail.com with ESMTPSA id z3sm11158058pfe.78.2021.10.02.18.22.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Oct 2021 18:22:30 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sun, 3 Oct 2021 11:22:09 +1000 Message-Id: <20211003012210.1165606-8-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20211003012210.1165606-1-npiggin@gmail.com> References: <20211003012210.1165606-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 7/8] phb3: make endian-clean X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Convert phb3 dt construction and in-memory hardware tables to use explicit endian conversions. Signed-off-by: Nicholas Piggin --- hw/phb3.c | 317 +++++++++++++++++++++++++------------------------ include/phb3.h | 12 +- 2 files changed, 165 insertions(+), 164 deletions(-) diff --git a/hw/phb3.c b/hw/phb3.c index aeeb6b655..09255a0a6 100644 --- a/hw/phb3.c +++ b/hw/phb3.c @@ -134,7 +134,7 @@ static int64_t phb3_pcicfg_check(struct phb3 *p, uint32_t bdfn, return OPAL_HARDWARE; /* Fetch the PE# from cache */ - *pe = p->rte_cache[bdfn]; + *pe = be16_to_cpu(p->rte_cache[bdfn]); return OPAL_SUCCESS; } @@ -714,7 +714,6 @@ static int64_t phb3_pci_reinit(struct phb *phb, uint64_t scope, uint64_t data) static void phb3_init_ioda_cache(struct phb3 *p) { uint32_t i; - uint64_t *data64; /* * RTT and PELTV. RTE should be 0xFF's to indicate @@ -737,21 +736,26 @@ static void phb3_init_ioda_cache(struct phb3 *p) * for EEH etc... (HW278969). */ for (i = 0; i < ARRAY_SIZE(p->rte_cache); i++) - p->rte_cache[i] = PHB3_RESERVED_PE_NUM; + p->rte_cache[i] = cpu_to_be16(PHB3_RESERVED_PE_NUM); memset(p->peltv_cache, 0x0, sizeof(p->peltv_cache)); /* Disable all LSI */ for (i = 0; i < ARRAY_SIZE(p->lxive_cache); i++) { - data64 = &p->lxive_cache[i]; - *data64 = SETFIELD(IODA2_LXIVT_PRIORITY, 0ul, 0xff); - *data64 = SETFIELD(IODA2_LXIVT_SERVER, *data64, 0x0); + uint64_t val; + + val = SETFIELD(IODA2_LXIVT_PRIORITY, 0ul, 0xff); + val = SETFIELD(IODA2_LXIVT_SERVER, val, 0x0); + p->lxive_cache[i] = val; } /* Diable all MSI */ for (i = 0; i < ARRAY_SIZE(p->ive_cache); i++) { - data64 = &p->ive_cache[i]; - *data64 = SETFIELD(IODA2_IVT_PRIORITY, 0ul, 0xff); - *data64 = SETFIELD(IODA2_IVT_SERVER, *data64, 0x0); + uint64_t val; + + val = SETFIELD(IODA2_IVT_PRIORITY, 0ul, 0xff); + val = SETFIELD(IODA2_IVT_SERVER, val, 0x0); + + p->ive_cache[i] = cpu_to_be64(val); } /* Clear TVT */ @@ -776,7 +780,7 @@ static int64_t phb3_ioda_reset(struct phb *phb, bool purge) { struct phb3 *p = phb_to_phb3(phb); uint64_t server, prio; - uint64_t *pdata64, data64; + uint64_t data64; uint32_t i; if (purge) { @@ -818,15 +822,14 @@ static int64_t phb3_ioda_reset(struct phb *phb, bool purge) /* Load RTE, PELTV */ if (p->tbl_rtt) - memcpy((void *)p->tbl_rtt, p->rte_cache, RTT_TABLE_SIZE); + memcpy(p->tbl_rtt, p->rte_cache, RTT_TABLE_SIZE); if (p->tbl_peltv) - memcpy((void *)p->tbl_peltv, p->peltv_cache, PELTV_TABLE_SIZE); + memcpy(p->tbl_peltv, p->peltv_cache, PELTV_TABLE_SIZE); /* Load IVT */ if (p->tbl_ivt) { - pdata64 = (uint64_t *)p->tbl_ivt; for (i = 0; i < IVT_TABLE_ENTRIES; i++) - pdata64[i * IVT_TABLE_STRIDE] = p->ive_cache[i]; + p->tbl_ivt[i * IVT_TABLE_STRIDE] = p->ive_cache[i]; } /* Invalidate RTE, IVE, TCE cache */ @@ -1212,11 +1215,12 @@ static int64_t phb3_map_pe_dma_window_real(struct phb *phb, static bool phb3_pci_msi_check_q(struct phb3 *p, uint32_t ive_num) { - uint64_t ive, ivc, ffi, state; + uint64_t ivc, ffi, state; + void *ive; uint8_t *q_byte; /* Each IVE has 16-bytes or 128-bytes */ - ive = p->tbl_ivt + (ive_num * IVT_TABLE_STRIDE * 8); + ive = p->tbl_ivt + (ive_num * IVT_TABLE_STRIDE); q_byte = (uint8_t *)(ive + 5); /* @@ -1273,8 +1277,9 @@ static int64_t phb3_pci_msi_eoi(struct phb *phb, uint32_t hwirq) { struct phb3 *p = phb_to_phb3(phb); + void *ive; uint32_t ive_num = PHB3_IRQ_NUM(hwirq); - uint64_t ive, ivc; + uint64_t ivc; uint8_t *p_byte, gp, gen, newgen; /* OS might not configure IVT yet */ @@ -1282,7 +1287,7 @@ static int64_t phb3_pci_msi_eoi(struct phb *phb, return OPAL_HARDWARE; /* Each IVE has 16-bytes or 128-bytes */ - ive = p->tbl_ivt + (ive_num * IVT_TABLE_STRIDE * 8); + ive = p->tbl_ivt + (ive_num * IVT_TABLE_STRIDE); p_byte = (uint8_t *)(ive + 4); /* Read generation and P */ @@ -1336,8 +1341,9 @@ static int64_t phb3_set_ive_pe(struct phb *phb, uint32_t ive_num) { struct phb3 *p = phb_to_phb3(phb); - uint64_t *cache, ivep, data64; - uint16_t *pe_word; + void *ivep; + uint64_t data64; + __be16 *pe_word; /* OS should enable the BAR in advance */ if (!p->tbl_ivt) @@ -1349,13 +1355,14 @@ static int64_t phb3_set_ive_pe(struct phb *phb, return OPAL_PARAMETER; /* Update IVE cache */ - cache = &p->ive_cache[ive_num]; - *cache = SETFIELD(IODA2_IVT_PE, *cache, pe_number); + data64 = be64_to_cpu(p->ive_cache[ive_num]); + data64 = SETFIELD(IODA2_IVT_PE, data64, pe_number); + p->ive_cache[ive_num] = cpu_to_be64(data64); /* Update in-memory IVE without clobbering P and Q */ - ivep = p->tbl_ivt + (ive_num * IVT_TABLE_STRIDE * 8); - pe_word = (uint16_t *)(ivep + 6); - *pe_word = pe_number; + ivep = p->tbl_ivt + (ive_num * IVT_TABLE_STRIDE); + pe_word = ivep + 6; + *pe_word = cpu_to_be16(pe_number); /* Invalidate IVC */ data64 = SETFIELD(PHB_IVC_INVALIDATE_SID, 0ul, ive_num); @@ -1628,17 +1635,18 @@ static void phb3_err_ER_clear(struct phb3 *p) static void phb3_read_phb_status(struct phb3 *p, struct OpalIoPhb3ErrorData *stat) { - uint16_t val; - uint64_t *pPEST; uint64_t val64 = 0; uint32_t i; + uint16_t __16; + uint32_t __32; + uint64_t __64; memset(stat, 0, sizeof(struct OpalIoPhb3ErrorData)); /* Error data common part */ - stat->common.version = OPAL_PHB_ERROR_DATA_VERSION_1; - stat->common.ioType = OPAL_PHB_ERROR_DATA_TYPE_PHB3; - stat->common.len = sizeof(struct OpalIoPhb3ErrorData); + stat->common.version = cpu_to_be32(OPAL_PHB_ERROR_DATA_VERSION_1); + stat->common.ioType = cpu_to_be32(OPAL_PHB_ERROR_DATA_TYPE_PHB3); + stat->common.len = cpu_to_be32(sizeof(struct OpalIoPhb3ErrorData)); /* * We read some registers using config space through AIB. @@ -1651,104 +1659,107 @@ static void phb3_read_phb_status(struct phb3 *p, p->flags |= PHB3_CFG_USE_ASB; /* Grab RC bridge control, make it 32-bit */ - phb3_pcicfg_read16(&p->phb, 0, PCI_CFG_BRCTL, &val); - stat->brdgCtl = val; + phb3_pcicfg_read16(&p->phb, 0, PCI_CFG_BRCTL, &__16); + stat->brdgCtl = cpu_to_be32(__16); /* Grab UTL status registers */ - stat->portStatusReg = hi32(phb3_read_reg_asb(p, UTL_PCIE_PORT_STATUS)); - stat->rootCmplxStatus = hi32(phb3_read_reg_asb(p, UTL_RC_STATUS)); - stat->busAgentStatus = hi32(phb3_read_reg_asb(p, UTL_SYS_BUS_AGENT_STATUS)); + stat->portStatusReg = cpu_to_be32(hi32(phb3_read_reg_asb(p, UTL_PCIE_PORT_STATUS))); + stat->rootCmplxStatus = cpu_to_be32(hi32(phb3_read_reg_asb(p, UTL_RC_STATUS))); + stat->busAgentStatus = cpu_to_be32(hi32(phb3_read_reg_asb(p, UTL_SYS_BUS_AGENT_STATUS))); /* * Grab various RC PCIe capability registers. All device, slot * and link status are 16-bit, so we grab the pair control+status * for each of them */ - phb3_pcicfg_read32(&p->phb, 0, p->ecap + PCICAP_EXP_DEVCTL, - &stat->deviceStatus); - phb3_pcicfg_read32(&p->phb, 0, p->ecap + PCICAP_EXP_SLOTCTL, - &stat->slotStatus); - phb3_pcicfg_read32(&p->phb, 0, p->ecap + PCICAP_EXP_LCTL, - &stat->linkStatus); + phb3_pcicfg_read32(&p->phb, 0, p->ecap + PCICAP_EXP_DEVCTL, &__32); + stat->deviceStatus = cpu_to_be32(__32); + phb3_pcicfg_read32(&p->phb, 0, p->ecap + PCICAP_EXP_SLOTCTL, &__32); + stat->slotStatus = cpu_to_be32(__32); + phb3_pcicfg_read32(&p->phb, 0, p->ecap + PCICAP_EXP_LCTL, &__32); + stat->linkStatus = cpu_to_be32(__32); /* * I assume those are the standard config space header, cmd & status * together makes 32-bit. Secondary status is 16-bit so I'll clear * the top on that one */ - phb3_pcicfg_read32(&p->phb, 0, PCI_CFG_CMD, &stat->devCmdStatus); - phb3_pcicfg_read16(&p->phb, 0, PCI_CFG_SECONDARY_STATUS, &val); - stat->devSecStatus = val; + phb3_pcicfg_read32(&p->phb, 0, PCI_CFG_CMD, &__32); + stat->devCmdStatus = cpu_to_be32(__32); + phb3_pcicfg_read16(&p->phb, 0, PCI_CFG_SECONDARY_STATUS, &__16); + stat->devSecStatus = cpu_to_be32(__16); /* Grab a bunch of AER regs */ - phb3_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_RERR_STA, - &stat->rootErrorStatus); - phb3_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_UE_STATUS, - &stat->uncorrErrorStatus); - phb3_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_CE_STATUS, - &stat->corrErrorStatus); - phb3_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_HDR_LOG0, - &stat->tlpHdr1); - phb3_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_HDR_LOG1, - &stat->tlpHdr2); - phb3_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_HDR_LOG2, - &stat->tlpHdr3); - phb3_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_HDR_LOG3, - &stat->tlpHdr4); - phb3_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_SRCID, - &stat->sourceId); + phb3_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_RERR_STA, &__32); + stat->rootErrorStatus = cpu_to_be32(__32); + phb3_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_UE_STATUS, &__32); + stat->uncorrErrorStatus = cpu_to_be32(__32); + phb3_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_CE_STATUS, &__32); + stat->corrErrorStatus = cpu_to_be32(__32); + phb3_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_HDR_LOG0, &__32); + stat->tlpHdr1 = cpu_to_be32(__32); + phb3_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_HDR_LOG1, &__32); + stat->tlpHdr2 = cpu_to_be32(__32); + phb3_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_HDR_LOG2, &__32); + stat->tlpHdr3 = cpu_to_be32(__32); + phb3_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_HDR_LOG3, &__32); + stat->tlpHdr4 = cpu_to_be32(__32); + phb3_pcicfg_read32(&p->phb, 0, p->aercap + PCIECAP_AER_SRCID, &__32); + stat->sourceId = cpu_to_be32(__32); /* Restore to AIB */ p->flags &= ~PHB3_CFG_USE_ASB; /* PEC NFIR */ - xscom_read(p->chip_id, p->pe_xscom + 0x0, &stat->nFir); - xscom_read(p->chip_id, p->pe_xscom + 0x3, &stat->nFirMask); - xscom_read(p->chip_id, p->pe_xscom + 0x8, &stat->nFirWOF); + xscom_read(p->chip_id, p->pe_xscom + 0x0, &__64); + stat->nFir = cpu_to_be64(__64); + xscom_read(p->chip_id, p->pe_xscom + 0x3, &__64); + stat->nFirMask = cpu_to_be64(__64); + xscom_read(p->chip_id, p->pe_xscom + 0x8, &__64); + stat->nFirWOF = cpu_to_be64(__64); /* PHB3 inbound and outbound error Regs */ - stat->phbPlssr = phb3_read_reg_asb(p, PHB_CPU_LOADSTORE_STATUS); - stat->phbCsr = phb3_read_reg_asb(p, PHB_DMA_CHAN_STATUS); - stat->lemFir = phb3_read_reg_asb(p, PHB_LEM_FIR_ACCUM); - stat->lemErrorMask = phb3_read_reg_asb(p, PHB_LEM_ERROR_MASK); - stat->lemWOF = phb3_read_reg_asb(p, PHB_LEM_WOF); - stat->phbErrorStatus = phb3_read_reg_asb(p, PHB_ERR_STATUS); - stat->phbFirstErrorStatus = phb3_read_reg_asb(p, PHB_ERR1_STATUS); - stat->phbErrorLog0 = phb3_read_reg_asb(p, PHB_ERR_LOG_0); - stat->phbErrorLog1 = phb3_read_reg_asb(p, PHB_ERR_LOG_1); - stat->mmioErrorStatus = phb3_read_reg_asb(p, PHB_OUT_ERR_STATUS); - stat->mmioFirstErrorStatus = phb3_read_reg_asb(p, PHB_OUT_ERR1_STATUS); - stat->mmioErrorLog0 = phb3_read_reg_asb(p, PHB_OUT_ERR_LOG_0); - stat->mmioErrorLog1 = phb3_read_reg_asb(p, PHB_OUT_ERR_LOG_1); - stat->dma0ErrorStatus = phb3_read_reg_asb(p, PHB_INA_ERR_STATUS); - stat->dma0FirstErrorStatus = phb3_read_reg_asb(p, PHB_INA_ERR1_STATUS); - stat->dma0ErrorLog0 = phb3_read_reg_asb(p, PHB_INA_ERR_LOG_0); - stat->dma0ErrorLog1 = phb3_read_reg_asb(p, PHB_INA_ERR_LOG_1); - stat->dma1ErrorStatus = phb3_read_reg_asb(p, PHB_INB_ERR_STATUS); - stat->dma1FirstErrorStatus = phb3_read_reg_asb(p, PHB_INB_ERR1_STATUS); - stat->dma1ErrorLog0 = phb3_read_reg_asb(p, PHB_INB_ERR_LOG_0); - stat->dma1ErrorLog1 = phb3_read_reg_asb(p, PHB_INB_ERR_LOG_1); + stat->phbPlssr = cpu_to_be64(phb3_read_reg_asb(p, PHB_CPU_LOADSTORE_STATUS)); + stat->phbCsr = cpu_to_be64(phb3_read_reg_asb(p, PHB_DMA_CHAN_STATUS)); + stat->lemFir = cpu_to_be64(phb3_read_reg_asb(p, PHB_LEM_FIR_ACCUM)); + stat->lemErrorMask = cpu_to_be64(phb3_read_reg_asb(p, PHB_LEM_ERROR_MASK)); + stat->lemWOF = cpu_to_be64(phb3_read_reg_asb(p, PHB_LEM_WOF)); + stat->phbErrorStatus = cpu_to_be64(phb3_read_reg_asb(p, PHB_ERR_STATUS)); + stat->phbFirstErrorStatus = cpu_to_be64(phb3_read_reg_asb(p, PHB_ERR1_STATUS)); + stat->phbErrorLog0 = cpu_to_be64(phb3_read_reg_asb(p, PHB_ERR_LOG_0)); + stat->phbErrorLog1 = cpu_to_be64(phb3_read_reg_asb(p, PHB_ERR_LOG_1)); + stat->mmioErrorStatus = cpu_to_be64(phb3_read_reg_asb(p, PHB_OUT_ERR_STATUS)); + stat->mmioFirstErrorStatus = cpu_to_be64(phb3_read_reg_asb(p, PHB_OUT_ERR1_STATUS)); + stat->mmioErrorLog0 = cpu_to_be64(phb3_read_reg_asb(p, PHB_OUT_ERR_LOG_0)); + stat->mmioErrorLog1 = cpu_to_be64(phb3_read_reg_asb(p, PHB_OUT_ERR_LOG_1)); + stat->dma0ErrorStatus = cpu_to_be64(phb3_read_reg_asb(p, PHB_INA_ERR_STATUS)); + stat->dma0FirstErrorStatus = cpu_to_be64(phb3_read_reg_asb(p, PHB_INA_ERR1_STATUS)); + stat->dma0ErrorLog0 = cpu_to_be64(phb3_read_reg_asb(p, PHB_INA_ERR_LOG_0)); + stat->dma0ErrorLog1 = cpu_to_be64(phb3_read_reg_asb(p, PHB_INA_ERR_LOG_1)); + stat->dma1ErrorStatus = cpu_to_be64(phb3_read_reg_asb(p, PHB_INB_ERR_STATUS)); + stat->dma1FirstErrorStatus = cpu_to_be64(phb3_read_reg_asb(p, PHB_INB_ERR1_STATUS)); + stat->dma1ErrorLog0 = cpu_to_be64(phb3_read_reg_asb(p, PHB_INB_ERR_LOG_0)); + stat->dma1ErrorLog1 = cpu_to_be64(phb3_read_reg_asb(p, PHB_INB_ERR_LOG_1)); /* * Grab PESTA & B content. The error bit (bit#0) should * be fetched from IODA and the left content from memory * resident tables. */ - pPEST = (uint64_t *)p->tbl_pest; val64 = PHB_IODA_AD_AUTOINC; val64 = SETFIELD(PHB_IODA_AD_TSEL, val64, IODA2_TBL_PESTA); phb3_write_reg_asb(p, PHB_IODA_ADDR, val64); for (i = 0; i < OPAL_PHB3_NUM_PEST_REGS; i++) { - stat->pestA[i] = phb3_read_reg_asb(p, PHB_IODA_DATA0); - stat->pestA[i] |= pPEST[2 * i]; + stat->pestA[i] = cpu_to_be64(phb3_read_reg_asb(p, PHB_IODA_DATA0)); + stat->pestA[i] |= p->tbl_pest[2 * i]; } val64 = PHB_IODA_AD_AUTOINC; val64 = SETFIELD(PHB_IODA_AD_TSEL, val64, IODA2_TBL_PESTB); phb3_write_reg_asb(p, PHB_IODA_ADDR, val64); for (i = 0; i < OPAL_PHB3_NUM_PEST_REGS; i++) { - stat->pestB[i] = phb3_read_reg_asb(p, PHB_IODA_DATA0); - stat->pestB[i] |= pPEST[2 * i + 1]; + stat->pestB[i] = cpu_to_be64(phb3_read_reg_asb(p, PHB_IODA_DATA0)); + stat->pestB[i] |= p->tbl_pest[2 * i + 1]; } } @@ -1792,10 +1803,10 @@ static void phb3_eeh_dump_regs(struct phb3 *p, struct OpalIoPhb3ErrorData *regs) PHBERR(p, " uncorrErrorStatus = %08x\n", s->uncorrErrorStatus); /* Byte swap TLP headers so they are the same as the PCIe spec */ - PHBERR(p, " tlpHdr1 = %08x\n", bswap_32(s->tlpHdr1)); - PHBERR(p, " tlpHdr2 = %08x\n", bswap_32(s->tlpHdr2)); - PHBERR(p, " tlpHdr3 = %08x\n", bswap_32(s->tlpHdr3)); - PHBERR(p, " tlpHdr4 = %08x\n", bswap_32(s->tlpHdr4)); + PHBERR(p, " tlpHdr1 = %08x\n", cpu_to_le32(be32_to_cpu((s->tlpHdr1)))); + PHBERR(p, " tlpHdr2 = %08x\n", cpu_to_le32(be32_to_cpu((s->tlpHdr2)))); + PHBERR(p, " tlpHdr3 = %08x\n", cpu_to_le32(be32_to_cpu((s->tlpHdr3)))); + PHBERR(p, " tlpHdr4 = %08x\n", cpu_to_le32(be32_to_cpu((s->tlpHdr4)))); PHBERR(p, " sourceId = %08x\n", s->sourceId); PHBERR(p, " nFir = %016llx\n", s->nFir); @@ -1858,7 +1869,7 @@ static int64_t phb3_msi_get_xive(struct irq_source *is, uint32_t isn, * Each IVE has 16 bytes in cache. Note that the kernel * should strip the link bits from server field. */ - ive = p->ive_cache[irq]; + ive = be64_to_cpu(p->ive_cache[irq]); *server = GETFIELD(IODA2_IVT_SERVER, ive); *prio = GETFIELD(IODA2_IVT_PRIORITY, ive); @@ -1870,8 +1881,8 @@ static int64_t phb3_msi_set_xive(struct irq_source *is, uint32_t isn, { struct phb3 *p = is->data; uint32_t chip, index; - uint64_t *cache, ive_num, data64, m_server, m_prio, ivc; - uint32_t *ive; + uint64_t ive_num, data64, m_server, m_prio, ivc; + __be32 *ive; chip = p8_irq_to_chip(isn); index = p8_irq_to_phb(isn); @@ -1896,15 +1907,16 @@ static int64_t phb3_msi_set_xive(struct irq_source *is, uint32_t isn, m_server = server; m_prio = prio; - cache = &p->ive_cache[ive_num]; - *cache = SETFIELD(IODA2_IVT_SERVER, *cache, m_server); - *cache = SETFIELD(IODA2_IVT_PRIORITY, *cache, m_prio); + data64 = be64_to_cpu(p->ive_cache[ive_num]); + data64 = SETFIELD(IODA2_IVT_SERVER, data64, m_server); + data64 = SETFIELD(IODA2_IVT_PRIORITY, data64, m_prio); + p->ive_cache[ive_num] = cpu_to_be64(data64);; /* * Update IVT and IVC. We need use IVC update register * to do that. Each IVE in the table has 128 bytes */ - ive = (uint32_t *)(p->tbl_ivt + ive_num * IVT_TABLE_STRIDE * 8); + ive = (__be32 *)(p->tbl_ivt + ive_num * IVT_TABLE_STRIDE); data64 = PHB_IVC_UPDATE_ENABLE_SERVER | PHB_IVC_UPDATE_ENABLE_PRI; data64 = SETFIELD(PHB_IVC_UPDATE_SID, data64, ive_num); data64 = SETFIELD(PHB_IVC_UPDATE_SERVER, data64, m_server); @@ -1914,7 +1926,7 @@ static int64_t phb3_msi_set_xive(struct irq_source *is, uint32_t isn, * We don't use SETFIELD because we are doing a 32-bit access * in order to avoid touching the P and Q bits */ - *ive = (m_server << 8) | m_prio; + *ive = cpu_to_be32((m_server << 8) | m_prio); out_be64(p->regs + PHB_IVC_UPDATE, data64); if (prio != 0xff) { @@ -1933,7 +1945,7 @@ static int64_t phb3_msi_set_xive(struct irq_source *is, uint32_t isn, sync(); /* Clear P, Q and Gen, preserve PE# */ - ive[1] &= 0x0000ffff; + ive[1] &= cpu_to_be32(0x0000ffff); /* * Update the IVC with a match against the old gen @@ -2079,7 +2091,6 @@ static int64_t phb3_set_pe(struct phb *phb, struct phb3 *p = phb_to_phb3(phb); uint64_t mask, val, tmp, idx; int32_t all = 0; - uint16_t *rte; /* Sanity check */ if (!p->tbl_rtt) @@ -2121,22 +2132,21 @@ static int64_t phb3_set_pe(struct phb *phb, if (all == 0x7) { if (action == OPAL_MAP_PE) { for (idx = 0; idx < RTT_TABLE_ENTRIES; idx++) - p->rte_cache[idx] = pe_number; + p->rte_cache[idx] = cpu_to_be16(pe_number); } else { - for ( idx = 0; idx < ARRAY_SIZE(p->rte_cache); idx++) - p->rte_cache[idx] = PHB3_RESERVED_PE_NUM; + for (idx = 0; idx < ARRAY_SIZE(p->rte_cache); idx++) + p->rte_cache[idx] = cpu_to_be16(PHB3_RESERVED_PE_NUM); } - memcpy((void *)p->tbl_rtt, p->rte_cache, RTT_TABLE_SIZE); + memcpy(p->tbl_rtt, p->rte_cache, RTT_TABLE_SIZE); } else { - rte = (uint16_t *)p->tbl_rtt; - for (idx = 0; idx < RTT_TABLE_ENTRIES; idx++, rte++) { + for (idx = 0; idx < RTT_TABLE_ENTRIES; idx++) { if ((idx & mask) != val) continue; if (action == OPAL_MAP_PE) - p->rte_cache[idx] = pe_number; + p->rte_cache[idx] = cpu_to_be16(pe_number); else - p->rte_cache[idx] = PHB3_RESERVED_PE_NUM; - *rte = p->rte_cache[idx]; + p->rte_cache[idx] = cpu_to_be16(PHB3_RESERVED_PE_NUM); + p->tbl_rtt[idx] = p->rte_cache[idx]; } } @@ -2152,7 +2162,6 @@ static int64_t phb3_set_peltv(struct phb *phb, uint8_t state) { struct phb3 *p = phb_to_phb3(phb); - uint8_t *peltv; uint32_t idx, mask; /* Sanity check */ @@ -2166,13 +2175,11 @@ static int64_t phb3_set_peltv(struct phb *phb, idx += (child_pe / 8); mask = 0x1 << (7 - (child_pe % 8)); - peltv = (uint8_t *)p->tbl_peltv; - peltv += idx; if (state) { - *peltv |= mask; + p->tbl_peltv[idx] |= mask; p->peltv_cache[idx] |= mask; } else { - *peltv &= ~mask; + p->tbl_peltv[idx] &= ~mask; p->peltv_cache[idx] &= ~mask; } @@ -3148,14 +3155,14 @@ static int64_t phb3_err_inject_mem64(struct phb3 *p, uint64_t pe_number, s_index = 0; e_index = ARRAY_SIZE(p->m64b_cache) - 2; for (index = 0; index < RTT_TABLE_ENTRIES; index++) { - if (p->rte_cache[index] != pe_number) + if (be16_to_cpu(p->rte_cache[index]) != pe_number) continue; if (index + 8 >= RTT_TABLE_ENTRIES) break; /* PCI bus dependent PE */ - if (p->rte_cache[index + 8] == pe_number) { + if (be16_to_cpu(p->rte_cache[index + 8]) == pe_number) { s_index = e_index = ARRAY_SIZE(p->m64b_cache) - 1; break; } @@ -3233,13 +3240,13 @@ static int64_t phb3_err_inject_cfg(struct phb3 *p, uint64_t pe_number, prefer = 0xffffull; m = PHB_PAPR_ERR_INJ_MASK_CFG_ALL; for (bdfn = 0; bdfn < RTT_TABLE_ENTRIES; bdfn++) { - if (p->rte_cache[bdfn] != pe_number) + if (be16_to_cpu(p->rte_cache[bdfn]) != pe_number) continue; /* The PE can be associated with PCI bus or device */ is_bus_pe = false; if ((bdfn + 8) < RTT_TABLE_ENTRIES && - p->rte_cache[bdfn + 8] == pe_number) + be16_to_cpu(p->rte_cache[bdfn + 8]) == pe_number) is_bus_pe = true; /* Figure out the PCI config address */ @@ -3895,11 +3902,11 @@ static void phb3_init_ioda2(struct phb3 *p) * Init_17 - PELT-V BAR */ out_be64(p->regs + PHB_RTT_BAR, - p->tbl_rtt | PHB_RTT_BAR_ENABLE); + (u64)p->tbl_rtt | PHB_RTT_BAR_ENABLE); out_be64(p->regs + PHB_PELTV_BAR, - p->tbl_peltv | PHB_PELTV_BAR_ENABLE); + (u64)p->tbl_peltv | PHB_PELTV_BAR_ENABLE); out_be64(p->regs + PHB_IVT_BAR, - p->tbl_ivt | 0x800 | PHB_IVT_BAR_ENABLE); + (u64)p->tbl_ivt | 0x800 | PHB_IVT_BAR_ENABLE); /* DD2.0 or the subsequent chips don't have memory * resident RBA. @@ -3913,7 +3920,7 @@ static void phb3_init_ioda2(struct phb3 *p) /* Init_22 - Setup PEST BAR */ out_be64(p->regs + PHB_PEST_BAR, - p->tbl_pest | PHB_PEST_BAR_ENABLE); + (u64)p->tbl_pest | PHB_PEST_BAR_ENABLE); /* Init_23 - PCIE Outbound upper address */ out_be64(p->regs + PHB_M64_UPPER_BITS, 0); @@ -4442,7 +4449,6 @@ static void phb3_init_hw(struct phb3 *p, bool first_init) static void phb3_allocate_tables(struct phb3 *p) { - uint16_t *rte; uint32_t i; /* XXX Our current memalign implementation sucks, @@ -4451,23 +4457,22 @@ static void phb3_allocate_tables(struct phb3 *p) * the memory and wastes space by always allocating twice * as much as requested (size + alignment) */ - p->tbl_rtt = (uint64_t)local_alloc(p->chip_id, RTT_TABLE_SIZE, RTT_TABLE_SIZE); + p->tbl_rtt = local_alloc(p->chip_id, RTT_TABLE_SIZE, RTT_TABLE_SIZE); assert(p->tbl_rtt); - rte = (uint16_t *)(p->tbl_rtt); - for (i = 0; i < RTT_TABLE_ENTRIES; i++, rte++) - *rte = PHB3_RESERVED_PE_NUM; + for (i = 0; i < RTT_TABLE_ENTRIES; i++) + p->tbl_rtt[i] = cpu_to_be16(PHB3_RESERVED_PE_NUM); - p->tbl_peltv = (uint64_t)local_alloc(p->chip_id, PELTV_TABLE_SIZE, PELTV_TABLE_SIZE); + p->tbl_peltv = local_alloc(p->chip_id, PELTV_TABLE_SIZE, PELTV_TABLE_SIZE); assert(p->tbl_peltv); - memset((void *)p->tbl_peltv, 0, PELTV_TABLE_SIZE); + memset(p->tbl_peltv, 0, PELTV_TABLE_SIZE); - p->tbl_pest = (uint64_t)local_alloc(p->chip_id, PEST_TABLE_SIZE, PEST_TABLE_SIZE); + p->tbl_pest = local_alloc(p->chip_id, PEST_TABLE_SIZE, PEST_TABLE_SIZE); assert(p->tbl_pest); - memset((void *)p->tbl_pest, 0, PEST_TABLE_SIZE); + memset(p->tbl_pest, 0, PEST_TABLE_SIZE); - p->tbl_ivt = (uint64_t)local_alloc(p->chip_id, IVT_TABLE_SIZE, IVT_TABLE_SIZE); + p->tbl_ivt = local_alloc(p->chip_id, IVT_TABLE_SIZE, IVT_TABLE_SIZE); assert(p->tbl_ivt); - memset((void *)p->tbl_ivt, 0, IVT_TABLE_SIZE); + memset(p->tbl_ivt, 0, IVT_TABLE_SIZE); } static void phb3_add_properties(struct phb3 *p) @@ -4556,13 +4561,13 @@ static void phb3_add_properties(struct phb3 *p) /* Indicators for variable tables */ dt_add_property_cells(np, "ibm,opal-rtt-table", - hi32(p->tbl_rtt), lo32(p->tbl_rtt), RTT_TABLE_SIZE); + hi32((u64)p->tbl_rtt), lo32((u64)p->tbl_rtt), RTT_TABLE_SIZE); dt_add_property_cells(np, "ibm,opal-peltv-table", - hi32(p->tbl_peltv), lo32(p->tbl_peltv), PELTV_TABLE_SIZE); + hi32((u64)p->tbl_peltv), lo32((u64)p->tbl_peltv), PELTV_TABLE_SIZE); dt_add_property_cells(np, "ibm,opal-pest-table", - hi32(p->tbl_pest), lo32(p->tbl_pest), PEST_TABLE_SIZE); + hi32((u64)p->tbl_pest), lo32((u64)p->tbl_pest), PEST_TABLE_SIZE); dt_add_property_cells(np, "ibm,opal-ivt-table", - hi32(p->tbl_ivt), lo32(p->tbl_ivt), IVT_TABLE_SIZE); + hi32((u64)p->tbl_ivt), lo32((u64)p->tbl_ivt), IVT_TABLE_SIZE); dt_add_property_cells(np, "ibm,opal-ive-stride", IVT_TABLE_STRIDE); dt_add_property_cells(np, "ibm,opal-rba-table", @@ -4581,11 +4586,11 @@ static bool phb3_calculate_windows(struct phb3 *p) "ibm,mmio-window", -1); assert(prop->len >= (2 * sizeof(uint64_t))); - p->mm0_base = ((const uint64_t *)prop->prop)[0]; - p->mm0_size = ((const uint64_t *)prop->prop)[1]; + p->mm0_base = be64_to_cpu(((__be64 *)prop->prop)[0]); + p->mm0_size = be64_to_cpu(((__be64 *)prop->prop)[1]); if (prop->len > 16) { - p->mm1_base = ((const uint64_t *)prop->prop)[2]; - p->mm1_size = ((const uint64_t *)prop->prop)[3]; + p->mm1_base = be64_to_cpu(((__be64 *)prop->prop)[2]); + p->mm1_size = be64_to_cpu(((__be64 *)prop->prop)[3]); } /* Sort them so that 0 is big and 1 is small */ @@ -4683,9 +4688,9 @@ static void phb3_create(struct dt_node *np) /* Get the various XSCOM register bases from the device-tree */ prop = dt_require_property(np, "ibm,xscom-bases", 3 * sizeof(uint32_t)); - p->pe_xscom = ((const uint32_t *)prop->prop)[0]; - p->spci_xscom = ((const uint32_t *)prop->prop)[1]; - p->pci_xscom = ((const uint32_t *)prop->prop)[2]; + p->pe_xscom = be32_to_cpu(((__be32 *)prop->prop)[0]); + p->spci_xscom = be32_to_cpu(((__be32 *)prop->prop)[1]); + p->pci_xscom = be32_to_cpu(((__be32 *)prop->prop)[2]); /* * We skip the initial PERST assertion requested by the generic code @@ -4809,8 +4814,7 @@ static void phb3_probe_pbcq(struct dt_node *pbcq) uint64_t val, phb_bar, bar_en; uint64_t mmio0_bar, mmio0_bmask, mmio0_sz; uint64_t mmio1_bar, mmio1_bmask, mmio1_sz; - uint64_t reg[2]; - uint64_t mmio_win[4]; + __be64 mmio_win[4]; unsigned int mmio_win_sz; struct dt_node *np; char *path; @@ -4895,13 +4899,13 @@ static void phb3_probe_pbcq(struct dt_node *pbcq) /* Build MMIO windows list */ mmio_win_sz = 0; if (mmio0_bar) { - mmio_win[mmio_win_sz++] = mmio0_bar; - mmio_win[mmio_win_sz++] = mmio0_sz; + mmio_win[mmio_win_sz++] = cpu_to_be64(mmio0_bar); + mmio_win[mmio_win_sz++] = cpu_to_be64(mmio0_sz); bar_en |= 0x8000000000000000ul; } if (mmio1_bar) { - mmio_win[mmio_win_sz++] = mmio1_bar; - mmio_win[mmio_win_sz++] = mmio1_sz; + mmio_win[mmio_win_sz++] = cpu_to_be64(mmio1_bar); + mmio_win[mmio_win_sz++] = cpu_to_be64(mmio1_sz); bar_en |= 0x4000000000000000ul; } @@ -4940,17 +4944,14 @@ static void phb3_probe_pbcq(struct dt_node *pbcq) gcid, pno, val); /* Create PHB node */ - reg[0] = phb_bar; - reg[1] = 0x1000; - - np = dt_new_addr(dt_root, "pciex", reg[0]); + np = dt_new_addr(dt_root, "pciex", phb_bar); if (!np) return; dt_add_property_strings(np, "compatible", "ibm,power8-pciex", "ibm,ioda2-phb"); dt_add_property_strings(np, "device_type", "pciex"); - dt_add_property(np, "reg", reg, sizeof(reg)); + dt_add_property_u64s(np, "reg", phb_bar, 0x1000); /* Everything else is handled later by skiboot, we just * stick a few hints here diff --git a/include/phb3.h b/include/phb3.h index 447e667cd..be9f4cbbb 100644 --- a/include/phb3.h +++ b/include/phb3.h @@ -214,10 +214,10 @@ struct phb3 { uint32_t base_lsi; /* SkiBoot owned in-memory tables */ - uint64_t tbl_rtt; - uint64_t tbl_peltv; - uint64_t tbl_pest; - uint64_t tbl_ivt; + __be16 *tbl_rtt; + uint8_t *tbl_peltv; + __be64 *tbl_pest; + __be64 *tbl_ivt; bool skip_perst; /* Skip first perst */ bool has_link; @@ -227,10 +227,10 @@ struct phb3 { unsigned int max_link_speed; uint32_t no_ecrc_devs; - uint16_t rte_cache[RTT_TABLE_ENTRIES]; + __be16 rte_cache[RTT_TABLE_ENTRIES]; uint8_t peltv_cache[PELTV_TABLE_SIZE]; uint64_t lxive_cache[8]; - uint64_t ive_cache[IVT_TABLE_ENTRIES]; + __be64 ive_cache[IVT_TABLE_ENTRIES]; uint64_t tve_cache[512]; uint64_t m32d_cache[256]; uint64_t m64b_cache[16]; From patchwork Sun Oct 3 01:22:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1535720 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=Q8TQxGVX; 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[115.64.153.41]) by smtp.gmail.com with ESMTPSA id z3sm11158058pfe.78.2021.10.02.18.22.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Oct 2021 18:22:32 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sun, 3 Oct 2021 11:22:10 +1000 Message-Id: <20211003012210.1165606-9-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20211003012210.1165606-1-npiggin@gmail.com> References: <20211003012210.1165606-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 8/8] flash: AST BMC endian fixes X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Fix endian for the 4-byte LPC copy similarly to other flash drivers. This allows flash to be detected on POWER8 AST BMC systems with a LE skiboot. Fix incorrect comments in those other drivers while we're here. Signed-off-by: Nicholas Piggin --- hw/ast-bmc/ast-sf-ctrl.c | 14 +++++++++++--- libflash/ipmi-hiomap.c | 2 +- libflash/mbox-flash.c | 2 +- 3 files changed, 13 insertions(+), 5 deletions(-) diff --git a/hw/ast-bmc/ast-sf-ctrl.c b/hw/ast-bmc/ast-sf-ctrl.c index 03cc44318..c3a32134e 100644 --- a/hw/ast-bmc/ast-sf-ctrl.c +++ b/hw/ast-bmc/ast-sf-ctrl.c @@ -77,8 +77,11 @@ static int ast_copy_to_ahb(uint32_t reg, const void *src, uint32_t len) while(len) { /* Chose access size */ if (len > 3 && !(off & 3)) { + /* endian swap: see ast_copy_from_ahb */ + uint32_t dat = be32_to_cpu(*(__be32 *)src); + rc = lpc_write(OPAL_LPC_FW, off, - *(uint32_t *)src, 4); + dat, 4); chunk = 4; } else { rc = lpc_write(OPAL_LPC_FW, off, @@ -119,8 +122,13 @@ static int ast_copy_from_ahb(void *dst, uint32_t reg, uint32_t len) /* Chose access size */ if (len > 3 && !(off & 3)) { rc = lpc_read(OPAL_LPC_FW, off, &dat, 4); - if (!rc) - *(uint32_t *)dst = dat; + if (!rc) { + /* + * lpc_read swaps to CPU endian but it's not + * really a 32-bit value, so convert back. + */ + *(__be32 *)dst = cpu_to_be32(dat); + } chunk = 4; } else { rc = lpc_read(OPAL_LPC_FW, off, &dat, 1); diff --git a/libflash/ipmi-hiomap.c b/libflash/ipmi-hiomap.c index c889d6316..29355d666 100644 --- a/libflash/ipmi-hiomap.c +++ b/libflash/ipmi-hiomap.c @@ -620,7 +620,7 @@ static int lpc_window_write(struct ipmi_hiomap *ctx, uint32_t pos, uint32_t chunk; if (len > 3 && !(off & 3)) { - /* endian swap: see lpc_window_write */ + /* endian swap: see lpc_window_read */ uint32_t dat = be32_to_cpu(*(__be32 *)buf); rc = lpc_write(OPAL_LPC_FW, off, dat, 4); diff --git a/libflash/mbox-flash.c b/libflash/mbox-flash.c index 6da77d7fc..4c20f15f2 100644 --- a/libflash/mbox-flash.c +++ b/libflash/mbox-flash.c @@ -199,7 +199,7 @@ static int lpc_window_write(struct mbox_flash_data *mbox_flash, uint32_t pos, uint32_t chunk; if (len > 3 && !(off & 3)) { - /* endian swap: see lpc_window_write */ + /* endian swap: see lpc_window_read */ uint32_t dat = be32_to_cpu(*(__be32 *)buf); rc = lpc_write(OPAL_LPC_FW, off, dat, 4);