From patchwork Thu Feb 1 17:49:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 868317 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zXSL11wQlz9t4B for ; Fri, 2 Feb 2018 04:49:29 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751567AbeBARt2 (ORCPT ); Thu, 1 Feb 2018 12:49:28 -0500 Received: from metis.ext.pengutronix.de ([85.220.165.71]:54705 "EHLO metis.ext.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752611AbeBARt1 (ORCPT ); Thu, 1 Feb 2018 12:49:27 -0500 Received: from dude.hi.pengutronix.de ([2001:67c:670:100:1d::7] helo=dude.pengutronix.de.) by metis.ext.pengutronix.de with esmtp (Exim 4.89) (envelope-from ) id 1ehIzE-0005xQ-2e; Thu, 01 Feb 2018 18:49:24 +0100 From: Lucas Stach To: Linus Walleij , Rob Herring Cc: Mark Rutland , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, "A . s . Dong" , linux-imx@nxp.com, kernel@pengutronix.de, patchwork-lst@pengutronix.de Subject: [PATCH v2 1/3] dt-bindings: add binding for i.MX8MQ IOMUXC Date: Thu, 1 Feb 2018 18:49:21 +0100 Message-Id: <20180201174923.7385-1-l.stach@pengutronix.de> X-Mailer: git-send-email 2.15.1 X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::7 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-gpio@vger.kernel.org Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This adds the binding for the i.MX8MQ pin controller, in the same fashion as earlier i.MX SoCs. Signed-off-by: Lucas Stach --- v2: switch to generic pinconf properties --- .../bindings/pinctrl/fsl,imx8mq-pinctrl.txt | 39 ++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt new file mode 100644 index 000000000000..5c5d2d835d05 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt @@ -0,0 +1,39 @@ +* Freescale IMX8MQ IOMUX Controller + +Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory +for common binding part and usage. + +=== Pin Controller Node === + +Required properties: +- compatible: "fsl,imx8mq-iomuxc" +- reg: Must contain the base physical address and size of the iomuxc registers. + +=== Pin Configuration Node === +Required properties: +- pinmux: Array of integersy, representing a group of pins mux setting. + The format is pinmux = , PIN_FUNC_ID is a pin working on + a specific function. + + Refer to imx8mq-pinfunc.h in device tree source folder for all available + imx8mq PIN_FUNC_ID. + +Optional Properties: +- drive-strength Integer: controls Drive Strength + 0: driver disabled + 1: 255 Ohm + 2: 105 Ohm + 3: 75 Ohm + 4: 85 Ohm + 5: 65 Ohm + 6: 45 Ohm + 7: 40 Ohm +- slew-rate: Integer: controls Slew Rate + 0: Slow + 1: Medium + 2: Fast + 3: Maximum +- drive-open-drain Bool: enable Open-drian +- bias-pull-up Bool: enable Pull-up +- input-schmitt-enable Bool: enable schmitt-trigger +- input-enable Bool: enable input, overriding module settings From patchwork Thu Feb 1 17:49:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 868316 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zXSL046b3z9t45 for ; Fri, 2 Feb 2018 04:49:28 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752712AbeBARt1 (ORCPT ); Thu, 1 Feb 2018 12:49:27 -0500 Received: from metis.ext.pengutronix.de ([85.220.165.71]:53007 "EHLO metis.ext.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751567AbeBARt1 (ORCPT ); Thu, 1 Feb 2018 12:49:27 -0500 Received: from dude.hi.pengutronix.de ([2001:67c:670:100:1d::7] helo=dude.pengutronix.de.) by metis.ext.pengutronix.de with esmtp (Exim 4.89) (envelope-from ) id 1ehIzE-0005xQ-54; Thu, 01 Feb 2018 18:49:24 +0100 From: Lucas Stach To: Linus Walleij , Rob Herring Cc: Mark Rutland , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, "A . s . Dong" , linux-imx@nxp.com, kernel@pengutronix.de, patchwork-lst@pengutronix.de Subject: [PATCH v2 2/3] pinctrl: imx: allow to configure SION with generic pinconf Date: Thu, 1 Feb 2018 18:49:22 +0100 Message-Id: <20180201174923.7385-2-l.stach@pengutronix.de> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180201174923.7385-1-l.stach@pengutronix.de> References: <20180201174923.7385-1-l.stach@pengutronix.de> X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::7 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-gpio@vger.kernel.org Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The SION bit force enables the input buffer, overriding the configuration driven by the muxed module. It is not located in the pad config register, but in the mux register and thus needs special handling. Signed-off-by: Lucas Stach --- v2: new patch in v2 --- drivers/pinctrl/freescale/pinctrl-imx.c | 19 +++++++------------ drivers/pinctrl/freescale/pinctrl-imx.h | 4 ++++ 2 files changed, 11 insertions(+), 12 deletions(-) diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index 24aaddd760a0..c976ffe7d47b 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -31,10 +31,6 @@ #include "../pinmux.h" #include "pinctrl-imx.h" -/* The bits in CONFIG cell defined in binding doc*/ -#define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */ -#define IMX_PAD_SION 0x40000000 /* set SION */ - static inline const struct group_desc *imx_pinctrl_find_group_by_name( struct pinctrl_dev *pctldev, const char *name) @@ -509,18 +505,17 @@ static int imx_pinctrl_parse_groups(struct device_node *np, pin->mux_mode = be32_to_cpu(*list++); pin->input_val = be32_to_cpu(*list++); - if (info->generic_pinconf) { + if (info->generic_pinconf) /* generic pin config decoded */ pin->config = config; - } else { + else /* legacy pin config read from devicetree */ - config = be32_to_cpu(*list++); + pin->config = be32_to_cpu(*list++); - /* SION bit is in mux register */ - if (config & IMX_PAD_SION) - pin->mux_mode |= IOMUXC_CONFIG_SION; - pin->config = config & ~IMX_PAD_SION; - } + /* SION bit is in mux register */ + if (pin->config & IMX_PAD_SION) + pin->mux_mode |= IOMUXC_CONFIG_SION; + pin->config = pin->config & ~IMX_PAD_SION; dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name, pin->mux_mode, pin->config); diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h index 038e8c0e5b96..8e74ddc9cd8a 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.h +++ b/drivers/pinctrl/freescale/pinctrl-imx.h @@ -18,6 +18,10 @@ #include #include +/* The bits in CONFIG cell defined in binding doc*/ +#define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */ +#define IMX_PAD_SION 0x40000000 /* set SION */ + struct platform_device; extern struct pinmux_ops imx_pmx_ops; From patchwork Thu Feb 1 17:49:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 868318 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zXSL20SCkz9t3R for ; Fri, 2 Feb 2018 04:49:30 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752722AbeBARt2 (ORCPT ); Thu, 1 Feb 2018 12:49:28 -0500 Received: from metis.ext.pengutronix.de ([85.220.165.71]:58663 "EHLO metis.ext.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752646AbeBARt1 (ORCPT ); Thu, 1 Feb 2018 12:49:27 -0500 Received: from dude.hi.pengutronix.de ([2001:67c:670:100:1d::7] helo=dude.pengutronix.de.) by metis.ext.pengutronix.de with esmtp (Exim 4.89) (envelope-from ) id 1ehIzE-0005xQ-7K; Thu, 01 Feb 2018 18:49:24 +0100 From: Lucas Stach To: Linus Walleij , Rob Herring Cc: Mark Rutland , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, "A . s . Dong" , linux-imx@nxp.com, kernel@pengutronix.de, patchwork-lst@pengutronix.de Subject: [PATCH v2 3/3] pinctrl: imx: add driver for i.MX8MQ Date: Thu, 1 Feb 2018 18:49:23 +0100 Message-Id: <20180201174923.7385-3-l.stach@pengutronix.de> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180201174923.7385-1-l.stach@pengutronix.de> References: <20180201174923.7385-1-l.stach@pengutronix.de> X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::7 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-gpio@vger.kernel.org Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The i.MX8MQ pincontrol works in a similar way to the earlier i.MX SoCs. This driver builds on top of the generic pinconf handling introduced with the i.MX7ULP pinctrl driver. Signed-off-by: Lucas Stach --- v2: - declare config structures as const - switch to generic pinconf --- drivers/pinctrl/freescale/Kconfig | 7 + drivers/pinctrl/freescale/Makefile | 1 + drivers/pinctrl/freescale/pinctrl-imx8mq.c | 368 +++++++++++++++++++++++++++++ 3 files changed, 376 insertions(+) create mode 100644 drivers/pinctrl/freescale/pinctrl-imx8mq.c diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig index 4dbc576ae27c..b0b62964e8ac 100644 --- a/drivers/pinctrl/freescale/Kconfig +++ b/drivers/pinctrl/freescale/Kconfig @@ -110,6 +110,13 @@ config PINCTRL_IMX7ULP help Say Y here to enable the imx7ulp pinctrl driver +config PINCTRL_IMX8MQ + bool "IMX8MQ pinctrl driver" + depends on SOC_IMX8MQ + select PINCTRL_IMX + help + Say Y here to enable the imx8mq pinctrl driver + config PINCTRL_VF610 bool "Freescale Vybrid VF610 pinctrl driver" depends on SOC_VF610 diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile index 19bb9a55a567..2b2b89bb8454 100644 --- a/drivers/pinctrl/freescale/Makefile +++ b/drivers/pinctrl/freescale/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_PINCTRL_IMX6SX) += pinctrl-imx6sx.o obj-$(CONFIG_PINCTRL_IMX6UL) += pinctrl-imx6ul.o obj-$(CONFIG_PINCTRL_IMX7D) += pinctrl-imx7d.o obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o +obj-$(CONFIG_PINCTRL_IMX8MQ) += pinctrl-imx8mq.o obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o diff --git a/drivers/pinctrl/freescale/pinctrl-imx8mq.c b/drivers/pinctrl/freescale/pinctrl-imx8mq.c new file mode 100644 index 000000000000..e6af506dfb60 --- /dev/null +++ b/drivers/pinctrl/freescale/pinctrl-imx8mq.c @@ -0,0 +1,368 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * Copyright (C) 2018 Pengutronix, Lucas Stach + */ + +#include +#include +#include +#include +#include +#include + +#include "pinctrl-imx.h" + +enum imx8mq_pads { + MX8MQ_PAD_RESERVE0 = 0, + MX8MQ_PAD_RESERVE1 = 1, + MX8MQ_PAD_RESERVE2 = 2, + MX8MQ_PAD_RESERVE3 = 3, + MX8MQ_PAD_RESERVE4 = 4, + MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX = 5, + MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX = 6, + MX8MQ_IOMUXC_ONOFF_SNVSMIX = 7, + MX8MQ_IOMUXC_POR_B_SNVSMIX = 8, + MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX = 9, + MX8MQ_IOMUXC_GPIO1_IO00 = 10, + MX8MQ_IOMUXC_GPIO1_IO01 = 11, + MX8MQ_IOMUXC_GPIO1_IO02 = 12, + MX8MQ_IOMUXC_GPIO1_IO03 = 13, + MX8MQ_IOMUXC_GPIO1_IO04 = 14, + MX8MQ_IOMUXC_GPIO1_IO05 = 15, + MX8MQ_IOMUXC_GPIO1_IO06 = 16, + MX8MQ_IOMUXC_GPIO1_IO07 = 17, + MX8MQ_IOMUXC_GPIO1_IO08 = 18, + MX8MQ_IOMUXC_GPIO1_IO09 = 19, + MX8MQ_IOMUXC_GPIO1_IO10 = 20, + MX8MQ_IOMUXC_GPIO1_IO11 = 21, + MX8MQ_IOMUXC_GPIO1_IO12 = 22, + MX8MQ_IOMUXC_GPIO1_IO13 = 23, + MX8MQ_IOMUXC_GPIO1_IO14 = 24, + MX8MQ_IOMUXC_GPIO1_IO15 = 25, + MX8MQ_IOMUXC_ENET_MDC = 26, + MX8MQ_IOMUXC_ENET_MDIO = 27, + MX8MQ_IOMUXC_ENET_TD3 = 28, + MX8MQ_IOMUXC_ENET_TD2 = 29, + MX8MQ_IOMUXC_ENET_TD1 = 30, + MX8MQ_IOMUXC_ENET_TD0 = 31, + MX8MQ_IOMUXC_ENET_TX_CTL = 32, + MX8MQ_IOMUXC_ENET_TXC = 33, + MX8MQ_IOMUXC_ENET_RX_CTL = 34, + MX8MQ_IOMUXC_ENET_RXC = 35, + MX8MQ_IOMUXC_ENET_RD0 = 36, + MX8MQ_IOMUXC_ENET_RD1 = 37, + MX8MQ_IOMUXC_ENET_RD2 = 38, + MX8MQ_IOMUXC_ENET_RD3 = 39, + MX8MQ_IOMUXC_SD1_CLK = 40, + MX8MQ_IOMUXC_SD1_CMD = 41, + MX8MQ_IOMUXC_SD1_DATA0 = 42, + MX8MQ_IOMUXC_SD1_DATA1 = 43, + MX8MQ_IOMUXC_SD1_DATA2 = 44, + MX8MQ_IOMUXC_SD1_DATA3 = 45, + MX8MQ_IOMUXC_SD1_DATA4 = 46, + MX8MQ_IOMUXC_SD1_DATA5 = 47, + MX8MQ_IOMUXC_SD1_DATA6 = 48, + MX8MQ_IOMUXC_SD1_DATA7 = 49, + MX8MQ_IOMUXC_SD1_RESET_B = 50, + MX8MQ_IOMUXC_SD1_STROBE = 51, + MX8MQ_IOMUXC_SD2_CD_B = 52, + MX8MQ_IOMUXC_SD2_CLK = 53, + MX8MQ_IOMUXC_SD2_CMD = 54, + MX8MQ_IOMUXC_SD2_DATA0 = 55, + MX8MQ_IOMUXC_SD2_DATA1 = 56, + MX8MQ_IOMUXC_SD2_DATA2 = 57, + MX8MQ_IOMUXC_SD2_DATA3 = 58, + MX8MQ_IOMUXC_SD2_RESET_B = 59, + MX8MQ_IOMUXC_SD2_WP = 60, + MX8MQ_IOMUXC_NAND_ALE = 61, + MX8MQ_IOMUXC_NAND_CE0_B = 62, + MX8MQ_IOMUXC_NAND_CE1_B = 63, + MX8MQ_IOMUXC_NAND_CE2_B = 64, + MX8MQ_IOMUXC_NAND_CE3_B = 65, + MX8MQ_IOMUXC_NAND_CLE = 66, + MX8MQ_IOMUXC_NAND_DATA00 = 67, + MX8MQ_IOMUXC_NAND_DATA01 = 68, + MX8MQ_IOMUXC_NAND_DATA02 = 69, + MX8MQ_IOMUXC_NAND_DATA03 = 70, + MX8MQ_IOMUXC_NAND_DATA04 = 71, + MX8MQ_IOMUXC_NAND_DATA05 = 72, + MX8MQ_IOMUXC_NAND_DATA06 = 73, + MX8MQ_IOMUXC_NAND_DATA07 = 74, + MX8MQ_IOMUXC_NAND_DQS = 75, + MX8MQ_IOMUXC_NAND_RE_B = 76, + MX8MQ_IOMUXC_NAND_READY_B = 77, + MX8MQ_IOMUXC_NAND_WE_B = 78, + MX8MQ_IOMUXC_NAND_WP_B = 79, + MX8MQ_IOMUXC_SAI5_RXFS = 80, + MX8MQ_IOMUXC_SAI5_RXC = 81, + MX8MQ_IOMUXC_SAI5_RXD0 = 82, + MX8MQ_IOMUXC_SAI5_RXD1 = 83, + MX8MQ_IOMUXC_SAI5_RXD2 = 84, + MX8MQ_IOMUXC_SAI5_RXD3 = 85, + MX8MQ_IOMUXC_SAI5_MCLK = 86, + MX8MQ_IOMUXC_SAI1_RXFS = 87, + MX8MQ_IOMUXC_SAI1_RXC = 88, + MX8MQ_IOMUXC_SAI1_RXD0 = 89, + MX8MQ_IOMUXC_SAI1_RXD1 = 90, + MX8MQ_IOMUXC_SAI1_RXD2 = 91, + MX8MQ_IOMUXC_SAI1_RXD3 = 92, + MX8MQ_IOMUXC_SAI1_RXD4 = 93, + MX8MQ_IOMUXC_SAI1_RXD5 = 94, + MX8MQ_IOMUXC_SAI1_RXD6 = 95, + MX8MQ_IOMUXC_SAI1_RXD7 = 96, + MX8MQ_IOMUXC_SAI1_TXFS = 97, + MX8MQ_IOMUXC_SAI1_TXC = 98, + MX8MQ_IOMUXC_SAI1_TXD0 = 99, + MX8MQ_IOMUXC_SAI1_TXD1 = 100, + MX8MQ_IOMUXC_SAI1_TXD2 = 101, + MX8MQ_IOMUXC_SAI1_TXD3 = 102, + MX8MQ_IOMUXC_SAI1_TXD4 = 103, + MX8MQ_IOMUXC_SAI1_TXD5 = 104, + MX8MQ_IOMUXC_SAI1_TXD6 = 105, + MX8MQ_IOMUXC_SAI1_TXD7 = 106, + MX8MQ_IOMUXC_SAI1_MCLK = 107, + MX8MQ_IOMUXC_SAI2_RXFS = 108, + MX8MQ_IOMUXC_SAI2_RXC = 109, + MX8MQ_IOMUXC_SAI2_RXD0 = 110, + MX8MQ_IOMUXC_SAI2_TXFS = 111, + MX8MQ_IOMUXC_SAI2_TXC = 112, + MX8MQ_IOMUXC_SAI2_TXD0 = 113, + MX8MQ_IOMUXC_SAI2_MCLK = 114, + MX8MQ_IOMUXC_SAI3_RXFS = 115, + MX8MQ_IOMUXC_SAI3_RXC = 116, + MX8MQ_IOMUXC_SAI3_RXD = 117, + MX8MQ_IOMUXC_SAI3_TXFS = 118, + MX8MQ_IOMUXC_SAI3_TXC = 119, + MX8MQ_IOMUXC_SAI3_TXD = 120, + MX8MQ_IOMUXC_SAI3_MCLK = 121, + MX8MQ_IOMUXC_SPDIF_TX = 122, + MX8MQ_IOMUXC_SPDIF_RX = 123, + MX8MQ_IOMUXC_SPDIF_EXT_CLK = 124, + MX8MQ_IOMUXC_ECSPI1_SCLK = 125, + MX8MQ_IOMUXC_ECSPI1_MOSI = 126, + MX8MQ_IOMUXC_ECSPI1_MISO = 127, + MX8MQ_IOMUXC_ECSPI1_SS0 = 128, + MX8MQ_IOMUXC_ECSPI2_SCLK = 129, + MX8MQ_IOMUXC_ECSPI2_MOSI = 130, + MX8MQ_IOMUXC_ECSPI2_MISO = 131, + MX8MQ_IOMUXC_ECSPI2_SS0 = 132, + MX8MQ_IOMUXC_I2C1_SCL = 133, + MX8MQ_IOMUXC_I2C1_SDA = 134, + MX8MQ_IOMUXC_I2C2_SCL = 135, + MX8MQ_IOMUXC_I2C2_SDA = 136, + MX8MQ_IOMUXC_I2C3_SCL = 137, + MX8MQ_IOMUXC_I2C3_SDA = 138, + MX8MQ_IOMUXC_I2C4_SCL = 139, + MX8MQ_IOMUXC_I2C4_SDA = 140, + MX8MQ_IOMUXC_UART1_RXD = 141, + MX8MQ_IOMUXC_UART1_TXD = 142, + MX8MQ_IOMUXC_UART2_RXD = 143, + MX8MQ_IOMUXC_UART2_TXD = 144, + MX8MQ_IOMUXC_UART3_RXD = 145, + MX8MQ_IOMUXC_UART3_TXD = 146, + MX8MQ_IOMUXC_UART4_RXD = 147, + MX8MQ_IOMUXC_UART4_TXD = 148, +}; + +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc imx8mq_pinctrl_pads[] = { + IMX_PINCTRL_PIN(MX8MQ_PAD_RESERVE0), + IMX_PINCTRL_PIN(MX8MQ_PAD_RESERVE1), + IMX_PINCTRL_PIN(MX8MQ_PAD_RESERVE2), + IMX_PINCTRL_PIN(MX8MQ_PAD_RESERVE3), + IMX_PINCTRL_PIN(MX8MQ_PAD_RESERVE4), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ONOFF_SNVSMIX), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_POR_B_SNVSMIX), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO00), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO01), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO02), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO03), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO04), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO05), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO06), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO07), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO08), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO09), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO10), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO11), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO12), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO13), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO14), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO15), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_MDC), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_MDIO), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_TD3), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_TD2), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_TD1), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_TD0), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_TX_CTL), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_TXC), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_RX_CTL), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_RXC), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_RD0), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_RD1), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_RD2), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_RD3), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_CLK), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_CMD), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA0), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA1), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA2), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA3), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA4), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA5), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA6), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA7), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_RESET_B), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_STROBE), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_CD_B), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_CLK), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_CMD), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_DATA0), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_DATA1), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_DATA2), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_DATA3), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_RESET_B), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_WP), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_ALE), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_CE0_B), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_CE1_B), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_CE2_B), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_CE3_B), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_CLE), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA00), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA01), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA02), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA03), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA04), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA05), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA06), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA07), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DQS), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_RE_B), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_READY_B), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_WE_B), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_WP_B), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_RXFS), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_RXC), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_RXD0), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_RXD1), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_RXD2), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_RXD3), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_MCLK), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXFS), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXC), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD0), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD1), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD2), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD3), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD4), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD5), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD6), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD7), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXFS), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXC), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD0), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD1), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD2), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD3), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD4), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD5), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD6), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD7), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_MCLK), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_RXFS), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_RXC), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_RXD0), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_TXFS), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_TXC), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_TXD0), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_MCLK), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_RXFS), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_RXC), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_RXD), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_TXFS), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_TXC), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_TXD), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_MCLK), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SPDIF_TX), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SPDIF_RX), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SPDIF_EXT_CLK), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI1_SCLK), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI1_MOSI), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI1_MISO), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI1_SS0), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI2_SCLK), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI2_MOSI), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI2_MISO), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI2_SS0), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C1_SCL), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C1_SDA), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C2_SCL), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C2_SDA), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C3_SCL), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C3_SDA), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C4_SCL), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C4_SDA), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART1_RXD), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART1_TXD), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART2_RXD), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART2_TXD), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART3_RXD), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART3_TXD), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART4_RXD), + IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART4_TXD), +}; + +static const struct imx_cfg_params_decode imx8mq_cfg_decodes[] = { + IMX_CFG_PARAMS_DECODE(PIN_CONFIG_DRIVE_STRENGTH, 0x07, 0), + IMX_CFG_PARAMS_DECODE(PIN_CONFIG_SLEW_RATE, 0x18, 3), + IMX_CFG_PARAMS_DECODE_INVERT(PIN_CONFIG_DRIVE_OPEN_DRAIN, 0x20, 5), + IMX_CFG_PARAMS_DECODE(PIN_CONFIG_BIAS_PULL_UP, 0x40, 6), + IMX_CFG_PARAMS_DECODE(PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0x80, 7), + IMX_CFG_PARAMS_DECODE(PIN_CONFIG_INPUT_ENABLE, IMX_PAD_SION, 30), +}; + +static const struct imx_pinctrl_soc_info imx8mq_pinctrl_info = { + .pins = imx8mq_pinctrl_pads, + .npins = ARRAY_SIZE(imx8mq_pinctrl_pads), + .gpr_compatible = "fsl,imx8mq-iomuxc-gpr", + .generic_pinconf = true, + .decodes = imx8mq_cfg_decodes, + .num_decodes = ARRAY_SIZE(imx8mq_cfg_decodes), +}; + +static const struct of_device_id imx8mq_pinctrl_of_match[] = { + { .compatible = "fsl,imx8mq-iomuxc", .data = &imx8mq_pinctrl_info, }, + { /* sentinel */ } +}; + +static int imx8mq_pinctrl_probe(struct platform_device *pdev) +{ + const struct imx_pinctrl_soc_info *pinctrl_info; + + pinctrl_info = of_device_get_match_data(&pdev->dev); + if (!pinctrl_info) + return -ENODEV; + + return imx_pinctrl_probe(pdev, pinctrl_info); +} + +static struct platform_driver imx8mq_pinctrl_driver = { + .driver = { + .name = "imx8mq-pinctrl", + .of_match_table = of_match_ptr(imx8mq_pinctrl_of_match), + }, + .probe = imx8mq_pinctrl_probe, +}; + +static int __init imx8mq_pinctrl_init(void) +{ + return platform_driver_register(&imx8mq_pinctrl_driver); +} +arch_initcall(imx8mq_pinctrl_init);