From patchwork Thu Sep 30 13:28:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kavyasree Kotagiri X-Patchwork-Id: 1534821 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=DUxPqSh4; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4HKvFq0l84z9sRf for ; Thu, 30 Sep 2021 23:28:31 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351362AbhI3NaL (ORCPT ); Thu, 30 Sep 2021 09:30:11 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:17432 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351386AbhI3NaJ (ORCPT ); Thu, 30 Sep 2021 09:30:09 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1633008506; x=1664544506; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=tBS5epH0q6eCvymRi9e0lXppg+w8SolCNJJHP6DNxCY=; b=DUxPqSh45zmfMdRHSWUTDAtR0uX6ExL0D8edborTvYOzLFvN7tFeMvrJ 9NYx6PskA4q15gSeW9N9PnMzBxH0eMFFEpOO53tVe0aGii4pxiEys1N38 5yWUawRr6MiFNckHWuZBrnG/qBENT2oA7bNAy3N8KlEc/bZ3cZUE1nGk8 DIMobdqZYEWHrPhZyeIUcmuv3LsqyIFmiNv3LomIYwruJBrRViOEXXQx4 lojeKFCAJoH6HsjwXQmvukwkrywE/nO8TxHft1WRq/CiMZ+Vc3YXrgkOl r+30PZ3Z33RLzfsllOLBKoIobVflsn+kM5tlUgb6/MAv2p956CwDqiwSY Q==; IronPort-SDR: e7FsoVLbCnl2ytg+8TVTCsTYap2FRNCxWhr93aw5K72dG/dBJbvdeSJ0DkHrdl9Vkes4WlLKtq boIbwpUlkgAIe/wm+j9WYlq4Mg1KAJ5yQU6qvIXhWN65P067CnD9/A6hyNwZiCZkpJOyQedU2t FbdYWSPuBrcsCmut/Qz9zNu8JdH0G7HMq/JvVaZzvxm8sIiNOFusamALoibwh5qVrNuFY+AbpY FDulzckyj+Ke896HDiBrUqcALUOYLlzAtTgK/YeGY56rW6UrAAAcDd4m+leqJA7W44xOGPjgGN Dicmk1NxTc0UBx8yYb3BhqgA X-IronPort-AV: E=Sophos;i="5.85,336,1624345200"; d="scan'208";a="131255631" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 30 Sep 2021 06:28:26 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Thu, 30 Sep 2021 06:28:25 -0700 Received: from kavya-HP-Compaq-6000-Pro-SFF-PC.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Thu, 30 Sep 2021 06:28:22 -0700 From: Kavyasree Kotagiri To: , , CC: , , , , , , Subject: [PATCH v7 1/3] dt-bindings: clock: lan966x: Add binding includes for lan966x SoC clock IDs Date: Thu, 30 Sep 2021 18:58:13 +0530 Message-ID: <20210930132815.15353-2-kavyasree.kotagiri@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210930132815.15353-1-kavyasree.kotagiri@microchip.com> References: <20210930132815.15353-1-kavyasree.kotagiri@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org LAN966X supports 14 clock outputs for its peripherals. This include file is introduced to use identifiers for clocks. Signed-off-by: Kavyasree Kotagiri Acked-by: Rob Herring --- v6 -> v7: - No changes. v5 -> v6: - Added Acked-by. v4 -> v5: - No changes. v3 -> v4: - No changes. v2 -> v3: - No changes. v1 -> v2: - Updated license. include/dt-bindings/clock/microchip,lan966x.h | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 include/dt-bindings/clock/microchip,lan966x.h diff --git a/include/dt-bindings/clock/microchip,lan966x.h b/include/dt-bindings/clock/microchip,lan966x.h new file mode 100644 index 000000000000..fe36ed6d8b5f --- /dev/null +++ b/include/dt-bindings/clock/microchip,lan966x.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021 Microchip Inc. + * + * Author: Kavyasree Kotagiri + */ + +#ifndef _DT_BINDINGS_CLK_LAN966X_H +#define _DT_BINDINGS_CLK_LAN966X_H + +#define GCK_ID_QSPI0 0 +#define GCK_ID_QSPI1 1 +#define GCK_ID_QSPI2 2 +#define GCK_ID_SDMMC0 3 +#define GCK_ID_PI 4 +#define GCK_ID_MCAN0 5 +#define GCK_ID_MCAN1 6 +#define GCK_ID_FLEXCOM0 7 +#define GCK_ID_FLEXCOM1 8 +#define GCK_ID_FLEXCOM2 9 +#define GCK_ID_FLEXCOM3 10 +#define GCK_ID_FLEXCOM4 11 +#define GCK_ID_TIMER 12 +#define GCK_ID_USB_REFCLK 13 + +#define N_CLOCKS 14 + +#endif From patchwork Thu Sep 30 13:28:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kavyasree Kotagiri X-Patchwork-Id: 1534822 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=QeXkDVNR; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4HKvGB4np8z9sRf for ; Thu, 30 Sep 2021 23:28:50 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351437AbhI3Nab (ORCPT ); Thu, 30 Sep 2021 09:30:31 -0400 Received: from esa.microchip.iphmx.com ([68.232.153.233]:49540 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351433AbhI3NaY (ORCPT ); Thu, 30 Sep 2021 09:30:24 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1633008521; x=1664544521; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=s0z56KhLKO6MbP32TRs2TV8dX8ToFoXdejyMjuyrdXM=; b=QeXkDVNRGHohkVZLhDYqOjGqt4f5f2BsAfZYxUS7JyYkyn8TiSVMUipj gr5NgGLmp+jEf+3zISIItN6xLADUvmhJ65K8xWxrS/umrEsQv71kcqVuX 5SwvnO8pAlQQ2MrPWWEHIJ4snOW1g4hRU6yG1a3amgdN7wYqD+lwwng1o pRZPIHkJdmH8cjIZ4JcJAqQhYHawKuhPnTIhdlHgEh6Q6tkefKqLX+y2b QaGmlG8jhakuJoyoy9SNVFzxK+jfpd9t8qabbBA78jmRDOHdmAKPX0Kfn idrLkZqlJMvbYphqChJGMlr0nB0PsoJZieaoiKBoTgRwq9JS0ysaYUrDP A==; IronPort-SDR: 74ILhevK+Z8BzRYW72P8iiBRkxJE+TBIJzvTpBFI0yBRydAZy6+PSAx6MYmc5RscymafWxJhkU kfvRBF5gKzRipvh2jGvIZTirT6Jm1kXoVBBtfzCtHzGDbTa3W2AmkpHdhNehx9Djurb6N4SSlv GX1BfDWGfpMkfx4D6HIRs2nOM+bT/87YDHfZeaz3QVVf2PVxGKENgOrGds7TQUtIyGpximdQEk qEvQ3uWN8joYV7LbIwFqygsIHntGpRyiq5S0TnxcM6/eyiZVob0FobUobVHhaY9a/oahPMEW7X /B3t2puJ7ZJN+Au05lyNhBMC X-IronPort-AV: E=Sophos;i="5.85,336,1624345200"; d="scan'208";a="146266145" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 30 Sep 2021 06:28:30 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Thu, 30 Sep 2021 06:28:30 -0700 Received: from kavya-HP-Compaq-6000-Pro-SFF-PC.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Thu, 30 Sep 2021 06:28:27 -0700 From: Kavyasree Kotagiri To: , , CC: , , , , , , Subject: [PATCH v7 2/3] dt-bindings: clock: lan966x: Add LAN966X Clock Controller Date: Thu, 30 Sep 2021 18:58:14 +0530 Message-ID: <20210930132815.15353-3-kavyasree.kotagiri@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210930132815.15353-1-kavyasree.kotagiri@microchip.com> References: <20210930132815.15353-1-kavyasree.kotagiri@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds the DT bindings documentation for lan966x SoC generic clock controller. Signed-off-by: Kavyasree Kotagiri Reviewed-by: Rob Herring --- v6 -> v7: - No changes. v5 -> v6: - Removed "_clk" in clock-names. - Added Reviewed-by. v4 -> v5: - In v4 dt-bindings, missed adding "clock-names" in required properties and example. So, added them. v3 -> v4: - Updated "clocks" description. - Added "clock-names". v2 -> v3: - Fixed dt_binding_check errors. v1 -> v2: - Updated example provided for clk controller DT node. .../bindings/clock/microchip,lan966x-gck.yaml | 57 +++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml diff --git a/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml b/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml new file mode 100644 index 000000000000..fca83bd68e26 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/microchip,lan966x-gck.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip LAN966X Generic Clock Controller + +maintainers: + - Kavyasree Kotagiri + +description: | + The LAN966X Generic clock controller contains 3 PLLs - cpu_clk, + ddr_clk and sys_clk. This clock controller generates and supplies + clock to various peripherals within the SoC. + +properties: + compatible: + const: microchip,lan966x-gck + + reg: + maxItems: 1 + + clocks: + items: + - description: CPU clock source + - description: DDR clock source + - description: System clock source + + clock-names: + items: + - const: cpu + - const: ddr + - const: sys + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clks: clock-controller@e00c00a8 { + compatible = "microchip,lan966x-gck"; + #clock-cells = <1>; + clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>; + clock-names = "cpu", "ddr", "sys"; + reg = <0xe00c00a8 0x38>; + }; +...