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Thu, 23 Sep 2021 07:01:22 -0700 (PDT) From: Oleksandr Suvorov To: u-boot@lists.denx.de Cc: Ye Li , Jorge Ramirez-Ortiz , Ricardo Salveti , Oleksandr Suvorov , Fabio Estevam , Harald Seiler , "NXP i.MX U-Boot Team" , Simon Glass , Stefano Babic Subject: [PATCH 1/1] mx7ulp: Update wdog disable sequence Date: Thu, 23 Sep 2021 17:01:15 +0300 Message-Id: <20210923140116.60318-2-oleksandr.suvorov@foundries.io> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210923140116.60318-1-oleksandr.suvorov@foundries.io> References: <20210923140116.60318-1-oleksandr.suvorov@foundries.io> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean From: Ye Li Update the mx7ulp wdog disable sequence to avoid potential reset issue in unlock or refresh sequence. Both sequence need two words write to wdog CNT register in 16 bus clocks window, if miss the window, the write will cause violation in wdog and reset the chip. Current u-boot code is using writel() function which has a DMB barrier to order the memory access. The DMB between two words write may introduce some delay in certain circumstance, causing the wdog reset due to 16 bus clock window requirement. Also, WDOG1 might have been enabled already depending on FUSE hence we need to be as close as possible to its reconfiguration timing requirement of 128 bus clock limit. This patch replaces writel() function by __raw_writel() to avoid such issue, and improve to check if watchdog is already disabled or unlocked. Signed-off-by: Ye Li Co-developed-by: Jorge Ramirez-Ortiz Signed-off-by: Jorge Ramirez-Ortiz Co-developed-by: Ricardo Salveti Signed-off-by: Ricardo Salveti Signed-off-by: Oleksandr Suvorov --- arch/arm/mach-imx/mx7ulp/soc.c | 31 ++++++++++++++++++++++++------- 1 file changed, 24 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c index 320f24dd29..7f097d6850 100644 --- a/arch/arm/mach-imx/mx7ulp/soc.c +++ b/arch/arm/mach-imx/mx7ulp/soc.c @@ -93,14 +93,31 @@ int board_postclk_init(void) static void disable_wdog(u32 wdog_base) { - writel(UNLOCK_WORD0, (wdog_base + 0x04)); - writel(UNLOCK_WORD1, (wdog_base + 0x04)); - writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */ - writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */ - writel(0x120, (wdog_base + 0x00)); /* Disable it and set update */ + u32 val_cs = readl(wdog_base + 0x00); - writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */ - writel(REFRESH_WORD1, (wdog_base + 0x04)); + if (!(val_cs & 0x80)) + return; + + dmb(); + __raw_writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */ + __raw_writel(REFRESH_WORD1, (wdog_base + 0x04)); + dmb(); + + if (!(val_cs & 800)) { + dmb(); + __raw_writel(UNLOCK_WORD0, (wdog_base + 0x04)); + __raw_writel(UNLOCK_WORD1, (wdog_base + 0x04)); + dmb(); + + while (!(readl(wdog_base + 0x00) & 0x800)); + } + dmb(); + __raw_writel(0x0, wdog_base + 0x0C); /* Set WIN to 0 */ + __raw_writel(0x400, wdog_base + 0x08); /* Set timeout to default 0x400 */ + __raw_writel(0x120, wdog_base + 0x00); /* Disable it and set update */ + dmb(); + + while (!(readl(wdog_base + 0x00) & 0x400)); } void init_wdog(void)