From patchwork Thu Sep 23 02:28:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Liang X-Patchwork-Id: 1531522 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=SYZUEL6K; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org; envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=) Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:e::133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4HFJyV60x9z9sW8 for ; Thu, 23 Sep 2021 12:29:22 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=D5S7apAw2lgIkC1oP9ka3umbG8H6qbTtOMXgTCHAv9c=; b=SYZUEL6KUGBgVF xOd1DHHevXd+zkrvnc/fna7ITsjk47+YGAEjJj86ZsRD8n1gSq9EEq0Qgg+7ZyYyNijCgw5yct8aF gwyfp5qsLWWB0RJheqXZ1/jICrhKAJS3RhoFunY1DA2WuPajbVExrtrqXh4P1Lxc3M+JXRfW2wOqD RYtXmKq15uii1u90KCypSrUHMMReY6IhuTPLBkRHP9cMjA5sbe+x53GZ6R+1w4Qg1VpVP0i6iNCnI lgK7S6UN44YF57b8UiNuewtZDMSDAVknMcH5qKl+ej5Wouhec2riz58cNKaDhcxHZP79AMiprTavR Rf71yqs6VYdaf8TNXsuQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mTEU3-00A6kW-LL; Thu, 23 Sep 2021 02:29:11 +0000 Received: from atcsqr.andestech.com ([60.248.187.195]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mTEU0-00A6k2-3v for opensbi@lists.infradead.org; Thu, 23 Sep 2021 02:29:09 +0000 Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id 18N2SmhV032385; Thu, 23 Sep 2021 10:28:48 +0800 (GMT-8) (envelope-from ycliang@andestech.com) Received: from atcfdc88.andestech.com (10.0.15.120) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Thu, 23 Sep 2021 10:28:44 +0800 From: Leo Yu-Chi Liang To: , , CC: , Leo Yu-Chi Liang Subject: [PATCH 1/2] lib: sbi: Introduce early hart initialization scheme Date: Thu, 23 Sep 2021 10:28:39 +0800 Message-ID: <20210923022839.17777-1-ycliang@andestech.com> X-Mailer: git-send-email 2.17.0 MIME-Version: 1.0 X-Originating-IP: [10.0.15.120] X-DNSRBL: X-MAIL: ATCSQR.andestech.com 18N2SmhV032385 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210922_192908_452378_893F5F72 X-CRM114-Status: UNSURE ( 5.96 ) X-CRM114-Notice: Please train this message. X-Spam-Score: 0.0 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: Referencing U-Boot (edd9ad81 riscv: cpu: Add callback to init each core) Introduce a callback function for each hart to do its own initialization as early as possible. Signed-off-by: Leo Yu-Chi Liang --- firmware/fw_base.S | 6 ++++++ lib/sbi/sbi_init.c | 4 ++++ 2 files changed, 10 insertions(+) Content analysis details: (0.0 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Referencing U-Boot (edd9ad81 riscv: cpu: Add callback to init each core) Introduce a callback function for each hart to do its own initialization as early as possible. Signed-off-by: Leo Yu-Chi Liang --- firmware/fw_base.S | 6 ++++++ lib/sbi/sbi_init.c | 4 ++++ 2 files changed, 10 insertions(+) diff --git a/firmware/fw_base.S b/firmware/fw_base.S index 1569e60..dfbe7d7 100644 --- a/firmware/fw_base.S +++ b/firmware/fw_base.S @@ -47,6 +47,12 @@ .globl _start .globl _start_warm _start: + /* Setup temporary stack */ + lla s4, _fw_end + li s5, (SBI_SCRATCH_SIZE * 2) + add sp, s4, s5 + /* call harts_early_init */ + call harts_early_init /* Find preferred boot HART id */ MOV_3R s0, a0, s1, a1, s2, a2 call fw_boot_hart diff --git a/lib/sbi/sbi_init.c b/lib/sbi/sbi_init.c index 6ef8742..02acac0 100644 --- a/lib/sbi/sbi_init.c +++ b/lib/sbi/sbi_init.c @@ -536,3 +536,7 @@ void __noreturn sbi_exit(struct sbi_scratch *scratch) sbi_hsm_exit(scratch); } + +__attribute__((weak)) void harts_early_init(void) +{ +} From patchwork Thu Sep 23 02:29:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Liang X-Patchwork-Id: 1531523 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Authentication-Results: ozlabs.org; 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Thu, 23 Sep 2021 10:30:04 +0800 (GMT-8) (envelope-from ycliang@andestech.com) Received: from atcfdc88.andestech.com (10.0.15.120) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Thu, 23 Sep 2021 10:30:04 +0800 From: Leo Yu-Chi Liang To: , , CC: , Leo Yu-Chi Liang Subject: [PATCH 2/2] platform/ae350: Initialize Coherent Manager as early as possible Date: Thu, 23 Sep 2021 10:29:57 +0800 Message-ID: <20210923022957.17840-1-ycliang@andestech.com> X-Mailer: git-send-email 2.17.0 MIME-Version: 1.0 X-Originating-IP: [10.0.15.120] X-DNSRBL: X-MAIL: ATCSQR.andestech.com 18N2U4Ow033460 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210923_033028_350206_B84FA2E9 X-CRM114-Status: GOOD ( 11.01 ) X-Spam-Score: 0.8 (/) X-Spam-Report: Spam detection software, running on the system "desiato.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: Coherent Manager will guarantee cache coherency as well as the correctness of atomic extension instruction on Andes 45 series on ae350. This feature needs to be enabled before the first A extension instruction, thus initialize it as early as possible. Content analysis details: (0.8 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record 0.8 UPPERCASE_50_75 message body is 50-75% uppercase X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Coherent Manager will guarantee cache coherency as well as the correctness of atomic extension instruction on Andes 45 series on ae350. This feature needs to be enabled before the first A extension instruction, thus initialize it as early as possible. Signed-off-by: Leo Yu-Chi Liang --- platform/andes/ae350/platform.c | 32 ++++++++++++++++++ platform/andes/ae350/platform.h | 60 ++++++++++++++++++--------------- 2 files changed, 64 insertions(+), 28 deletions(-) diff --git a/platform/andes/ae350/platform.c b/platform/andes/ae350/platform.c index ae4ef71..f7d18d7 100644 --- a/platform/andes/ae350/platform.c +++ b/platform/andes/ae350/platform.c @@ -28,6 +28,38 @@ static struct plic_data plic = { .num_src = AE350_PLIC_NUM_SOURCES, }; +static bool is_andestar45_series(void) +{ + uintptr_t marchid = csr_read(CSR_MARCHID); + + return ((marchid & 0xF0) >> 4 == 4 && + (marchid & 0xF) == 5) ? true : false; +} + +/* per harts early initialization */ +void harts_early_init(void) +{ + uintptr_t mcache_ctl_val = csr_read(CSR_MCACHECTL); + + if (is_andestar45_series()) { + if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN)) + mcache_ctl_val |= V5_MCACHE_CTL_DC_COHEN_EN; + + csr_write(CSR_MCACHECTL, mcache_ctl_val); + + /* + * Check DC_COHEN_EN, if cannot write to mcache_ctl, + * we assume this bitmap not support L2 CM + */ + mcache_ctl_val = csr_read(CSR_MCACHECTL); + if ((mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN)) { + /* Wait for DC_COHSTA bit be set */ + while (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHSTA_EN)) + mcache_ctl_val = csr_read(CSR_MCACHECTL); + } + } +} + /* Platform final initialization. */ static int ae350_final_init(bool cold_boot) { diff --git a/platform/andes/ae350/platform.h b/platform/andes/ae350/platform.h index f34ca0f..10ffaf0 100644 --- a/platform/andes/ae350/platform.h +++ b/platform/andes/ae350/platform.h @@ -30,11 +30,11 @@ #define AE350_UART_REG_WIDTH 0 /*Memory and Miscellaneous Registers*/ -#define CSR_MILMB 0x7c0 -#define CSR_MDLMB 0x7c1 +#define CSR_MILMB 0x7c0 +#define CSR_MDLMB 0x7c1 #define CSR_MECC_CDOE 0x7c2 -#define CSR_MNVEC 0x7c3 -#define CSR_MPFTCTL 0x7c5 +#define CSR_MNVEC 0x7c3 +#define CSR_MPFTCTL 0x7c5 #define CSR_MCACHECTL 0x7ca #define CSR_MCCTLBEGINADDR 0x7cb #define CSR_MCCTLCOMMAND 0x7cc @@ -62,42 +62,42 @@ enum sbi_ext_andes_fid { #define V5_MMISC_CTL_BRPE_OFFSET 3 #define V5_MMISC_CTL_MSA_OR_UNA_OFFSET 6 #define V5_MMISC_CTL_NON_BLOCKING_OFFSET 8 -#define V5_MCACHE_CTL_L1I_PREFETCH_OFFSET 9 -#define V5_MCACHE_CTL_L1D_PREFETCH_OFFSET 10 -#define V5_MCACHE_CTL_DC_WAROUND_OFFSET_1 13 -#define V5_MCACHE_CTL_DC_WAROUND_OFFSET_2 14 #define V5_MMISC_CTL_VEC_PLIC_EN (1UL << V5_MMISC_CTL_VEC_PLIC_OFFSET) #define V5_MMISC_CTL_RVCOMPM_EN (1UL << V5_MMISC_CTL_RVCOMPM_OFFSET) #define V5_MMISC_CTL_BRPE_EN (1UL << V5_MMISC_CTL_BRPE_OFFSET) #define V5_MMISC_CTL_MSA_OR_UNA_EN (1UL << V5_MMISC_CTL_MSA_OR_UNA_OFFSET) #define V5_MMISC_CTL_NON_BLOCKING_EN (1UL << V5_MMISC_CTL_NON_BLOCKING_OFFSET) -#define V5_MCACHE_CTL_L1I_PREFETCH_EN (1UL << V5_MCACHE_CTL_L1I_PREFETCH_OFFSET) -#define V5_MCACHE_CTL_L1D_PREFETCH_EN (1UL << V5_MCACHE_CTL_L1D_PREFETCH_OFFSET) -#define V5_MCACHE_CTL_DC_WAROUND_1_EN (1UL << V5_MCACHE_CTL_DC_WAROUND_OFFSET_1) -#define V5_MCACHE_CTL_DC_WAROUND_2_EN (1UL << V5_MCACHE_CTL_DC_WAROUND_OFFSET_2) #define V5_MMISC_CTL_MASK (V5_MMISC_CTL_VEC_PLIC_EN | V5_MMISC_CTL_RVCOMPM_EN \ | V5_MMISC_CTL_BRPE_EN | V5_MMISC_CTL_MSA_OR_UNA_EN | V5_MMISC_CTL_NON_BLOCKING_EN) /* nds mcache_ctl register*/ -#define V5_MCACHE_CTL_IC_EN_OFFSET 0 -#define V5_MCACHE_CTL_DC_EN_OFFSET 1 -#define V5_MCACHE_CTL_IC_ECCEN_OFFSET 2 -#define V5_MCACHE_CTL_DC_ECCEN_OFFSET 4 -#define V5_MCACHE_CTL_IC_RWECC_OFFSET 6 -#define V5_MCACHE_CTL_DC_RWECC_OFFSET 7 -#define V5_MCACHE_CTL_CCTL_SUEN_OFFSET 8 - -/*nds cctl command*/ -#define V5_UCCTL_L1D_WBINVAL_ALL 6 -#define V5_UCCTL_L1D_WB_ALL 7 +#define V5_MCACHE_CTL_IC_EN_OFFSET 0 +#define V5_MCACHE_CTL_DC_EN_OFFSET 1 +#define V5_MCACHE_CTL_IC_ECCEN_OFFSET 2 +#define V5_MCACHE_CTL_DC_ECCEN_OFFSET 4 +#define V5_MCACHE_CTL_IC_RWECC_OFFSET 6 +#define V5_MCACHE_CTL_DC_RWECC_OFFSET 7 +#define V5_MCACHE_CTL_CCTL_SUEN_OFFSET 8 +#define V5_MCACHE_CTL_L1I_PREFETCH_OFFSET 9 +#define V5_MCACHE_CTL_L1D_PREFETCH_OFFSET 10 +#define V5_MCACHE_CTL_DC_WAROUND_OFFSET_1 13 +#define V5_MCACHE_CTL_DC_WAROUND_OFFSET_2 14 +#define V5_MCACHE_CTL_DC_COHEN_OFFSET 19 +#define V5_MCACHE_CTL_DC_COHSTA_OFFSET 20 -#define V5_MCACHE_CTL_IC_EN (1UL << V5_MCACHE_CTL_IC_EN_OFFSET) -#define V5_MCACHE_CTL_DC_EN (1UL << V5_MCACHE_CTL_DC_EN_OFFSET) -#define V5_MCACHE_CTL_IC_RWECC (1UL << V5_MCACHE_CTL_IC_RWECC_OFFSET) -#define V5_MCACHE_CTL_DC_RWECC (1UL << V5_MCACHE_CTL_DC_RWECC_OFFSET) -#define V5_MCACHE_CTL_CCTL_SUEN (1UL << V5_MCACHE_CTL_CCTL_SUEN_OFFSET) +#define V5_MCACHE_CTL_L1I_PREFETCH_EN (1UL << V5_MCACHE_CTL_L1I_PREFETCH_OFFSET) +#define V5_MCACHE_CTL_L1D_PREFETCH_EN (1UL << V5_MCACHE_CTL_L1D_PREFETCH_OFFSET) +#define V5_MCACHE_CTL_DC_WAROUND_1_EN (1UL << V5_MCACHE_CTL_DC_WAROUND_OFFSET_1) +#define V5_MCACHE_CTL_DC_WAROUND_2_EN (1UL << V5_MCACHE_CTL_DC_WAROUND_OFFSET_2) +#define V5_MCACHE_CTL_DC_COHEN_EN (1UL << V5_MCACHE_CTL_DC_COHEN_OFFSET) +#define V5_MCACHE_CTL_DC_COHSTA_EN (1UL << V5_MCACHE_CTL_DC_COHSTA_OFFSET) +#define V5_MCACHE_CTL_IC_EN (1UL << V5_MCACHE_CTL_IC_EN_OFFSET) +#define V5_MCACHE_CTL_DC_EN (1UL << V5_MCACHE_CTL_DC_EN_OFFSET) +#define V5_MCACHE_CTL_IC_RWECC (1UL << V5_MCACHE_CTL_IC_RWECC_OFFSET) +#define V5_MCACHE_CTL_DC_RWECC (1UL << V5_MCACHE_CTL_DC_RWECC_OFFSET) +#define V5_MCACHE_CTL_CCTL_SUEN (1UL << V5_MCACHE_CTL_CCTL_SUEN_OFFSET) #define V5_MCACHE_CTL_MASK (V5_MCACHE_CTL_IC_EN | V5_MCACHE_CTL_DC_EN \ | V5_MCACHE_CTL_IC_RWECC | V5_MCACHE_CTL_DC_RWECC \ @@ -105,6 +105,10 @@ enum sbi_ext_andes_fid { | V5_MCACHE_CTL_L1D_PREFETCH_EN | V5_MCACHE_CTL_DC_WAROUND_1_EN \ | V5_MCACHE_CTL_DC_WAROUND_2_EN) +/*nds cctl command*/ +#define V5_UCCTL_L1D_WBINVAL_ALL 6 +#define V5_UCCTL_L1D_WB_ALL 7 + #define V5_L2C_CTL_OFFSET 0x8 #define V5_L2C_CTL_ENABLE_OFFSET 0 #define V5_L2C_CTL_IPFDPT_OFFSET 3