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Violators will be prosecuted; Tue, 30 Jan 2018 17:43:22 -0500 Received: from b01ledav006.gho.pok.ibm.com (b01ledav006.gho.pok.ibm.com [9.57.199.111]) by b01cxnp23034.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w0UMhLDC46923850; Tue, 30 Jan 2018 22:43:21 GMT Received: from b01ledav006.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 417E9AC03A; Tue, 30 Jan 2018 17:44:40 -0500 (EST) Received: from [9.10.86.107] (unknown [9.10.86.107]) by b01ledav006.gho.pok.ibm.com (Postfix) with ESMTP id 01D7BAC03F; Tue, 30 Jan 2018 17:44:39 -0500 (EST) Subject: [PATCH, rs6000] Fix VSX/altivec assumptions in altivec-13.c testcase From: Will Schmidt Reply-To: will_schmidt@vnet.ibm.com To: gcc-patches@gcc.gnu.org Cc: Segher Boessenkool , David Edelsohn , Bill Schmidt Date: Tue, 30 Jan 2018 16:43:20 -0600 Mime-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 18013022-0052-0000-0000-000002ABEAF8 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00008454; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000248; SDB=6.00982717; UDB=6.00498329; IPR=6.00761999; BA=6.00005802; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00019296; XFM=3.00000015; UTC=2018-01-30 22:43:23 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18013022-0053-0000-0000-0000536A4681 Message-Id: <1517352200.11602.244.camel@brimstone.rchland.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-01-30_08:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1011 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1801300276 X-IsSubscribed: yes Hi, Some VSX function has previosly crept into the altivec-13 testcase. In particular, anything 'vector long long' and 'vector double', causing issues on platforms without VSX support. So, break that content out into it's own testcase, allowing better testcase coverage. Sniff-tested on Power6, altivec-13.c test now passes there, where it used to fail. Still plan to do a sniff-test on AIX, but have expectations that this should help. OK for trunk? Thanks, -Will [testsuite] 2018-01-30 Will Schmidt * gcc.target/powerpc/altivec-13.c: Remove VSX-requiring built-ins. * gcc.target/powerpc/vsx-13.c: New. diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-13.c b/gcc/testsuite/gcc.target/powerpc/altivec-13.c index 2315f6e..31ff509 100644 --- a/gcc/testsuite/gcc.target/powerpc/altivec-13.c +++ b/gcc/testsuite/gcc.target/powerpc/altivec-13.c @@ -6,54 +6,47 @@ /* This test case exercises intrinsic/argument combinations that, while not in the Motorola AltiVec PIM, have nevertheless crept into the AltiVec vernacular over the years. */ +/* Tests requiring VSX support (vector long long and vector double) have + been moved over to vsx-13.c. */ + #include -void foo (void) +void foo (void) { vector bool int boolVec1 = (vector bool int) vec_splat_u32(3); vector bool short boolVec2 = (vector bool short) vec_splat_u16(3); vector bool char boolVec3 = (vector bool char) vec_splat_u8(3); vector signed char vsc1, vsc2, vscz; vector unsigned char vuc1, vuc2, vucz; vector signed short int vssi1, vssi2, vssiz; vector signed int vsi1, vsi2, vsiz; vector unsigned int vui1, vui2, vuiz; vector unsigned short int vusi1, vusi2, vusiz; - vector bool long long vubll1, vubll2, vubllz; - vector signed int long long vsill1, vsill2, vsillz; - vector unsigned int long long vuill1, vuill2, vuillz; vector pixel vp1, vp2, vpz; vector float vf1, vf2, vfz; - vector double vd1, vd2, vdz; boolVec1 = vec_sld( boolVec1, boolVec1, 4 ); boolVec2 = vec_sld( boolVec2, boolVec2, 2 ); boolVec3 = vec_sld( boolVec3, boolVec3, 1 ); vscz = vec_sld( vsc1, vsc2, 1 ); vucz = vec_sld( vuc1, vuc2, 1 ); vsiz = vec_sld( vsi1, vsi2, 1 ); vuiz = vec_sld( vui1, vui2, 1 ); - vubllz = vec_sld( vubll1, vubll2, 1 ); - vsillz = vec_sld( vsill1, vsill2, 1 ); - vuillz = vec_sld( vuill1, vuill2, 1 ); vssiz = vec_sld( vssi1, vssi2, 1 ); vusiz = vec_sld( vusi1, vusi2, 1 ); vfz = vec_sld( vf1, vf2, 1 ); - vdz = vec_sld( vd1, vd2, 1 ); vpz = vec_sld( vp1, vp2, 1 ); vucz = vec_srl(vuc1, vuc2); vsiz = vec_srl(vsi1, vuc2); vuiz = vec_srl(vui1, vuc2); - vsillz = vec_srl(vsill1, vuc2); - vuillz = vec_srl(vuill1, vuc2); vpz = vec_srl(vp1, vuc2); vssiz = vec_srl(vssi1, vuc2); vusiz = vec_srl(vusi1, vuc2); vscz = vec_sro(vsc1, vsc2); @@ -62,14 +55,10 @@ void foo (void) vucz = vec_sro(vuc1, vuc2); vsiz = vec_sro(vsi1, vsc2); vsiz = vec_sro(vsi1, vuc2); vuiz = vec_sro(vui1, vsc2); vuiz = vec_sro(vui1, vuc2); - vsillz = vec_sro(vsill1, vsc2); - vsillz = vec_sro(vsill1, vuc2); - vuillz = vec_sro(vuill1, vsc2); - vuillz = vec_sro(vuill1, vuc2); vpz = vec_sro(vp1, vsc2); vpz = vec_sro(vp1, vuc2); vssiz = vec_sro(vssi1, vsc2); vssiz = vec_sro(vssi1, vuc2); vusiz = vec_sro(vusi1, vsc2); @@ -81,8 +70,8 @@ void foo (void) /* Expected results: vec_sld vsldoi vec_srl vsr vec_sro vsro */ -/* { dg-final { scan-assembler-times "vsldoi" 15 } } */ -/* { dg-final { scan-assembler-times "vsr " 8 } } */ -/* { dg-final { scan-assembler-times "vsro" 20 } } */ +/* { dg-final { scan-assembler-times "vsldoi" 11 } } */ +/* { dg-final { scan-assembler-times "vsr " 6 } } */ +/* { dg-final { scan-assembler-times "vsro" 16 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-13.c b/gcc/testsuite/gcc.target/powerpc/vsx-13.c new file mode 100644 index 0000000..5b4eb68 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-13.c @@ -0,0 +1,42 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx" } */ + +/* Variations of tests that require VSX support. This is a variation of + the altivec-13.c testcase. */ + +#include + +void foo (void) +{ + + vector signed char vsc1, vsc2, vscz; + vector unsigned char vuc1, vuc2, vucz; + vector bool long long vubll1, vubll2, vubllz; + vector signed int long long vsill1, vsill2, vsillz; + vector unsigned int long long vuill1, vuill2, vuillz; + vector double vd1, vd2, vdz; + + vubllz = vec_sld( vubll1, vubll2, 1 ); + vsillz = vec_sld( vsill1, vsill2, 1 ); + vuillz = vec_sld( vuill1, vuill2, 1 ); + + vsillz = vec_srl(vsill1, vuc2); + vuillz = vec_srl(vuill1, vuc2); + + vsillz = vec_sro(vsill1, vsc2); + vsillz = vec_sro(vsill1, vuc2); + vuillz = vec_sro(vuill1, vsc2); + vuillz = vec_sro(vuill1, vuc2); + + vdz = vec_sld( vd1, vd2, 1 ); +} + +/* Expected results: + vec_sld vsldoi + vec_srl vsr + vec_sro vsro */ + +/* { dg-final { scan-assembler-times "vsldoi" 4 } } */ +/* { dg-final { scan-assembler-times "vsr " 2 } } */ +/* { dg-final { scan-assembler-times "vsro" 4 } } */