From patchwork Mon Sep 6 10:40:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Earnshaw X-Patchwork-Id: 1524890 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=qXG1xlAg; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4H34h85ZCGz9sRf for ; Mon, 6 Sep 2021 20:41:27 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A2AA63858414 for ; Mon, 6 Sep 2021 10:41:24 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A2AA63858414 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1630924884; bh=dosV9IbzNB5qeRudi30N2KuIE/ay+LC/Ton7OESsqkY=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=qXG1xlAgXbNIEdmYO8Fsns2qT8dhCQRSBaPiEVQ9jL7uK37O2iLpmjdsinp3Zh3Su gwWI7YMwvrQU/niFepeSYdPPARoZ1WUcj4+Odc9fcCS5mQNqZWZO2diu674yge3Cl5 QHciLuljtSMYAq0R/3SyNLe2e5wWrAkLyMGubSSM= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 633CE385841E for ; Mon, 6 Sep 2021 10:40:43 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 633CE385841E Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 078A2D6E; Mon, 6 Sep 2021 03:40:43 -0700 (PDT) Received: from e126323.arm.com (unknown [10.57.39.244]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 448D73F73D; Mon, 6 Sep 2021 03:40:42 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH 1/3] rtl: allow forming subregs of already unaligned mems [PR102125] Date: Mon, 6 Sep 2021 11:40:16 +0100 Message-Id: <20210906104018.2697413-2-rearnsha@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210906104018.2697413-1-rearnsha@arm.com> References: <20210906104018.2697413-1-rearnsha@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Earnshaw via Gcc-patches From: Richard Earnshaw Reply-To: Richard Earnshaw Cc: bernd.edlinger@hotmail.de, Richard Earnshaw Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" GCC was recently changed to prevent simplify_subreg from simplifying a subreg of a mem when the mode of the new mem would have stricter alignment constraints than the inner mem already has when the target requires STRICT_ALIGNMENT. However, such targets may have specialist patterns that can handle unaligned accesses and this restriction turns out to be unduly restrictive. So limit this restriction to only apply when the inner mem is naturally aligned to the inner mode. gcc/ChangeLog: PR target/102125 * simplify-rtx.c (simplify_context::simplify_subreg): Allow simplifying (subreg (mem())) when the inner mem is already misaligned for its type. --- gcc/simplify-rtx.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c index ebad5cb5a79..1baa50cb1b9 100644 --- a/gcc/simplify-rtx.c +++ b/gcc/simplify-rtx.c @@ -7317,7 +7317,11 @@ simplify_context::simplify_subreg (machine_mode outermode, rtx op, have instruction to move the whole thing. */ && (! MEM_VOLATILE_P (op) || ! have_insn_for (SET, innermode)) - && !(STRICT_ALIGNMENT && MEM_ALIGN (op) < GET_MODE_ALIGNMENT (outermode)) + /* On STRICT_ALIGNMENT targets, don't allow the alignment to be increased + if the inner object is already naturally aligned. */ + && !(STRICT_ALIGNMENT + && MEM_ALIGN (op) >= GET_MODE_ALIGNMENT (innermode) + && MEM_ALIGN (op) < GET_MODE_ALIGNMENT (outermode)) && known_le (outersize, innersize)) return adjust_address_nv (op, outermode, byte); From patchwork Mon Sep 6 10:40:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Earnshaw X-Patchwork-Id: 1524895 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=eyI8wZN6; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4H34ky4NJjz9sRf for ; Mon, 6 Sep 2021 20:43:54 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id F0F56383940B for ; Mon, 6 Sep 2021 10:43:51 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org F0F56383940B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1630925032; bh=OvrqDh3OIbbttIUwRYsrarpLCmn7fepOIEX49uuqXHg=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=eyI8wZN6XJQkWnvIw0jKXGS/qoMwk6s5fr0rKSuRMzlsoGbL5jhUvKyEd/g7Ymphi mdZPDVAXOOBcpOJ/Ryz+I2eLWakHsithiabCPdNNFbyZ+2kvUhnV57mu/DDeA4ZCnD 5p97kum+Xv8gr9MAsh0HkCQE60bbBit8J4JurMSw= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 2226E3858427 for ; Mon, 6 Sep 2021 10:40:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 2226E3858427 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BC9AE1063; Mon, 6 Sep 2021 03:40:43 -0700 (PDT) Received: from e126323.arm.com (unknown [10.57.39.244]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 40DDD3F73D; Mon, 6 Sep 2021 03:40:43 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH 2/3] arm: expand handling of movmisalign for DImode [PR102125] Date: Mon, 6 Sep 2021 11:40:17 +0100 Message-Id: <20210906104018.2697413-3-rearnsha@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210906104018.2697413-1-rearnsha@arm.com> References: <20210906104018.2697413-1-rearnsha@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Earnshaw via Gcc-patches From: Richard Earnshaw Reply-To: Richard Earnshaw Cc: Richard Earnshaw Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" DImode is currently handled only for machines with vector modes enabled, but this is unduly restrictive and is generally better done in core registers. gcc/ChangeLog: PR target/102125 * config/arm/arm.md (movmisaligndi): New define_expand. * config/arm/vec-common.md (movmisalign): Iterate over VDQ mode. --- gcc/config/arm/arm.md | 34 ++++++++++++++++++++++++++++++++++ gcc/config/arm/vec-common.md | 4 ++-- 2 files changed, 36 insertions(+), 2 deletions(-) diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 5d3f21b91c4..f66ed7da012 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -12617,6 +12617,40 @@ (define_expand "copysigndf3" }" ) +;; movmisalign for DImode +(define_expand "movmisaligndi" + [(match_operand:DI 0 "general_operand") + (match_operand:DI 1 "general_operand")] + "unaligned_access" +{ + /* Avoid breaking up an aligned load or store, this avoids problems if + that operand might be volatile. */ + if (MEM_P (operands[0]) + && MEM_ALIGN (operands[0]) >= GET_MODE_ALIGNMENT (DImode)) + { + rtx tmp = gen_reg_rtx (DImode); + emit_insn (gen_movmisaligndi (tmp, operands[1])); + emit_insn (gen_movdi (operands[0], tmp)); + DONE; + } + else if (MEM_P (operands[1]) + && MEM_ALIGN (operands[1]) >= GET_MODE_ALIGNMENT (DImode)) + { + rtx tmp = gen_reg_rtx (DImode); + emit_insn (gen_movdi (tmp, operands[1])); + operands[1] = tmp; + } + + rtx lo_op0 = gen_lowpart (SImode, operands[0]); + rtx lo_op1 = gen_lowpart (SImode, operands[1]); + rtx hi_op0 = gen_highpart_mode (SImode, DImode, operands[0]); + rtx hi_op1 = gen_highpart_mode (SImode, DImode, operands[1]); + + emit_insn (gen_movmisalignsi (lo_op0, lo_op1)); + emit_insn (gen_movmisalignsi (hi_op0, hi_op1)); + DONE; +}) + ;; movmisalign patterns for HImode and SImode. (define_expand "movmisalign" [(match_operand:HSI 0 "general_operand") diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md index 68de4f0f943..e71d9b3811f 100644 --- a/gcc/config/arm/vec-common.md +++ b/gcc/config/arm/vec-common.md @@ -281,8 +281,8 @@ (define_expand "cml4" }) (define_expand "movmisalign" - [(set (match_operand:VDQX 0 "neon_perm_struct_or_reg_operand") - (unspec:VDQX [(match_operand:VDQX 1 "neon_perm_struct_or_reg_operand")] + [(set (match_operand:VDQ 0 "neon_perm_struct_or_reg_operand") + (unspec:VDQ [(match_operand:VDQ 1 "neon_perm_struct_or_reg_operand")] UNSPEC_MISALIGNED_ACCESS))] "ARM_HAVE__LDST && !BYTES_BIG_ENDIAN && unaligned_access && !TARGET_REALLY_IWMMXT" From patchwork Mon Sep 6 10:40:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Earnshaw X-Patchwork-Id: 1524893 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=d1ZaToO8; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4H34jC4hfCz9sRf for ; Mon, 6 Sep 2021 20:42:23 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E79273857425 for ; Mon, 6 Sep 2021 10:42:20 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E79273857425 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1630924940; bh=7La20y+UO+UeYcbihQ5owF3LoLwgjLqgZmHz4CgE90o=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=d1ZaToO8fzGxKrbLmhcUS4GgMYYJV7MvepuevNq8zNVJyv3TKl3zELGTx/Vag2Au7 vgIAglSGR5UMj90d92A2BLd6IaP/9lpHc3uIACEoxoPZe47mnrD4oJUelCzOVqmYTq +9rr85+CSMp7gF2EEMsqnXRtVdK8C0iYa02N/T/0= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id E9AC3385841E for ; Mon, 6 Sep 2021 10:40:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E9AC3385841E Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9AE31D6E; Mon, 6 Sep 2021 03:40:44 -0700 (PDT) Received: from e126323.arm.com (unknown [10.57.39.244]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 00D9E3F73D; Mon, 6 Sep 2021 03:40:43 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [PATCH 3/3] gimple: allow more folding of memcpy [PR102125] Date: Mon, 6 Sep 2021 11:40:18 +0100 Message-Id: <20210906104018.2697413-4-rearnsha@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210906104018.2697413-1-rearnsha@arm.com> References: <20210906104018.2697413-1-rearnsha@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Earnshaw via Gcc-patches From: Richard Earnshaw Reply-To: Richard Earnshaw Cc: Richard Earnshaw Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" The current restriction on folding memcpy to a single element of size MOVE_MAX is excessively cautious on most machines and limits some significant further optimizations. So relax the restriction provided the copy size does not exceed MOVE_MAX * MOVE_RATIO and that a SET insn exists for moving the value into machine registers. Note that there were already checks in place for having misaligned move operations when one or more of the operands were unaligned. On Arm this now permits optimizing uint64_t bar64(const uint8_t *rData1) { uint64_t buffer; memcpy(&buffer, rData1, sizeof(buffer)); return buffer; } from ldr r2, [r0] @ unaligned sub sp, sp, #8 ldr r3, [r0, #4] @ unaligned strd r2, [sp] ldrd r0, [sp] add sp, sp, #8 to mov r3, r0 ldr r0, [r0] @ unaligned ldr r1, [r3, #4] @ unaligned PR target/102125 - (ARM Cortex-M3 and newer) missed optimization. memcpy not needed operations gcc/ChangeLog: PR target/102125 * gimple-fold.c (gimple_fold_builtin_memory_op): Allow folding memcpy if the size is not more than MOVE_MAX * MOVE_RATIO. --- gcc/gimple-fold.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/gcc/gimple-fold.c b/gcc/gimple-fold.c index 3f2c176cff6..d9ffb5006f5 100644 --- a/gcc/gimple-fold.c +++ b/gcc/gimple-fold.c @@ -67,6 +67,8 @@ along with GCC; see the file COPYING3. If not see #include "tree-vector-builder.h" #include "tree-ssa-strlen.h" #include "varasm.h" +#include "memmodel.h" +#include "optabs.h" enum strlen_range_kind { /* Compute the exact constant string length. */ @@ -957,14 +959,17 @@ gimple_fold_builtin_memory_op (gimple_stmt_iterator *gsi, = build_int_cst (build_pointer_type_for_mode (char_type_node, ptr_mode, true), 0); - /* If we can perform the copy efficiently with first doing all loads - and then all stores inline it that way. Currently efficiently - means that we can load all the memory into a single integer - register which is what MOVE_MAX gives us. */ + /* If we can perform the copy efficiently with first doing all loads and + then all stores inline it that way. Currently efficiently means that + we can load all the memory with a single set operation and that the + total size is less than MOVE_MAX * MOVE_RATIO. */ src_align = get_pointer_alignment (src); dest_align = get_pointer_alignment (dest); if (tree_fits_uhwi_p (len) - && compare_tree_int (len, MOVE_MAX) <= 0 + && (compare_tree_int + (len, (MOVE_MAX + * MOVE_RATIO (optimize_function_for_size_p (cfun)))) + <= 0) /* FIXME: Don't transform copies from strings with known length. Until GCC 9 this prevented a case in gcc.dg/strlenopt-8.c from being handled, and the case was XFAILed for that reason. @@ -1000,6 +1005,7 @@ gimple_fold_builtin_memory_op (gimple_stmt_iterator *gsi, if (type && is_a (TYPE_MODE (type), &mode) && GET_MODE_SIZE (mode) * BITS_PER_UNIT == ilen * 8 + && have_insn_for (SET, mode) /* If the destination pointer is not aligned we must be able to emit an unaligned store. */ && (dest_align >= GET_MODE_ALIGNMENT (mode)